Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.

Abstract: A power amplification device configured to switching-amplify a high-frequency input signal and output a switching-amplified signal. The device includes a feedback circuit configured to output a feedback signal including a portion of the switching-amplified signal; a subtractor configured to output an error signal indicating a difference between the input signal and the feedback signal; a comparator configured to compare the error signal with a threshold voltage and generate an on/off pulse signal based on a result of the comparison; a one-shot circuit configured to be set in an on-state for a time period using a rising timing of the pulse signal as a trigger; and an amplifier configured to switching-amplify the input signal by a logical OR between the generated on/off pulse signal and an output signal from the one-shot circuit, and output the switching-amplified signal.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal is coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.

Abstract: A combination equalizer and automatic gain control (AGC) is provided for high-speed receivers. The combination circuit comprises a first AGC having an input to accept a communication signal and an input to accept a first control signal. The first AGC modifies the communication signal gain in response to the first control signal, to supply a first stage signal at an output. An equalizer has an input to accept the first stage signal and an input to accept a second control signal. The equalizer modifies the frequency characteristics of the first stage signal in response to the second control signal, to supply an equalized signal at an output. A second AGC has an input to accept the equalized signal and an input to accept a third control signal. The second AGC modifies the equalized signal gain in response to the third control signal, to supply a second stage signal at an output.

Abstract: A device including a gain control element coupled prior to or within a radio frequency (RF) power amplifier (PA) with an adaptive parametric PA protection circuit is described. In an exemplary embodiment, the device includes a gain control element coupled prior to a radio frequency power amplifier with a power stage with corresponding transistor breakdown threshold values, having an adaptive parametric PA protection circuit configured to receive at least one power stage drain-source voltage parameter value, at least one power stage drain-gate voltage parameter value, and at least one power stage drain-source current parameter value, and including an adaptive parametric PA protection circuit having a first section for processing the parameter values and a second section for generating a gain correction signal to adjust the gain control element with optimal power added efficiency (PAE) for the power stage within the corresponding transistor breakdown threshold values.

Abstract: An apparatus comprises an amplifier circuit and a detection circuit. The amplifier circuit includes a high voltage supply rail, a low voltage supply rail, and an output stage. The detection circuit is electrically coupled to the amplifier output stage and generates an indication when the output voltage at the output stage exceeds a specified output voltage threshold value. The amplifier circuit further includes a bias circuit configured to bias the amplifier circuit with a first bias current value when the output voltage is less than the specified output voltage threshold value, and bias the amplifier circuit with a second bias current value when the output voltage exceeds the specified output voltage threshold value.

Abstract: The invention provides a variable gain amplifier system for use in a burst mode receiver, said system comprising an amplifier adapted to amplify a signal; a gain control module; a dc offset compensation module adapted to derive a compensation signal as a function of the amplifier gain. Compared to existing methods for dc offset compensation in variable gain amplifier, the system and method for dc offset compensation allows fast adjustment of rapidly changing dc offsets that occur in applications where the gain of the variable gain amplifier is adjusted rapidly.

Abstract: Apparatus and methods for biasing a power amplifier are provided. In one embodiment, a packaged circuit includes a power amplifier, a bond wire electrically connected between a system voltage source and a supply input of the power amplifier, a current source, a reference resistor electrically connected between the system voltage source and the current source, and a comparator. The comparator is configured to compare a sense voltage that is based on a voltage across the bond wire to a reference voltage that is based on a voltage across the reference resistor. The comparator is configured to generate a saturation control signal for clamping a bias current of the power amplifier when the sense voltage exceeds the reference voltage.

Abstract: A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.

Abstract: A relationship is established between measurable characteristics of the DC power input to a power amplifier and the RF output power level. A power circuit is configured to measure the input supply current to the power amplifier and to utilize the relationship between the input supply current and the applied input supply voltage to the output power level, thereby normalizing the output power of an amplified communication signal.

Abstract: Methods and devices for increasing a sensor resolution are disclosed. In one example, a two measurement process is used. A first measurement is used to effectively measure across a full range (e.g. 0 to 5 VDC) of the sensor. This first measurement may identify the current operating point of the sensor (e.g. 3.5 VDC). A second measurement may then be made to effectively measure across a sub-range of the sensor that encompasses the current operating point of the sensor (e.g. across a sub-range of 3.0 to 4.0 VDC for a current operating point of 3.5 VDC). The gain of the amplifier may be raised during the second measurement to produce a higher resolution measurement. In some cases, the first measurement may be used to determine an appropriate offset that may be applied so as to scale the amplifier to the desired sub-range of sensor that includes the current operating point of the sensor. In some cases, the two measurements may be used together to compute an effectively higher resolution measurement signal.

Abstract: Embodiments of the present invention provide a hybrid analog to digital converter that may include a DAC coupled to a hybrid analog to digital converter input; an integrator having an input coupled to the hybrid analog to digital converter input and the DAC, and generating an integrator output; a comparator coupled to the integrator output and having a comparator output; a successive approximation register coupled to the comparator output; and a counter coupled to the comparator output to generate an hybrid analog to digital converter output. The hybrid analog to digital converter may be operable as a successive approximation register converter and a continuous time sigma delta converter.

Abstract: A protection circuit for a power amplifier connected as a negative feedback loop around the power amplifier. The negative feedback loop comprises a detector circuit, a driver circuit and an attenuator circuit. The detector circuit receives output voltage from the power amplifier and generates a signal when the output voltage exceeds a predefined threshold. The driver circuit filters the signal received from the detector circuit to maintain feedback loop stability and adjusts the feedback loop bandwidth and gain to provide a filtered signal. The attenuator circuit receives the filtered signal and attenuates the input voltage of the power amplifier to reduce the output voltage of the power amplifier to a level below the predefined threshold.

Abstract: A digitally-controlled analog gain circuit supports at plurality of gain settings in which gain changes are made from a first setting to a new setting in response to a clocking signal of a non-uniform rate. The non-uniform rate clocking signal can be created pseudo randomly by applying a periodic sequence of clock pulses to a linear feedback shift register. Alternatively, the non-uniform rate clock signal can be created by applying a noise source to a phase detector input of a phase locked loop. The clocking signal can be generated by an oscillator, or as a sequence of pulses output by a zero crossing detector. Finally, the gain circuit can apply positive gain to the signal. Alternatively, the gain circuit can apply a negative gain (attenuation) to the signal.

Abstract: An automatic gain control circuit including a variable gain amplifier (11) adapted to receive a received signal (R) and to output an amplified signal (A) to an analog to digital converter (20), and a gain controller (12) which is connected to said variable gain amplifier (11) for receiving said amplified signal (A) and for controlling a gain of said variable gain amplifier (11). The gain controller (12) is adapted to determine an occurrence of a threshold event each time the amplified signal (A) has reached a predetermined threshold, decrease the gain of the variable gain amplifier (11) at each occurrence of a threshold event, measure a delay since the last threshold event, increase the gain of the variable gain amplifier (11) if the delay is greater than a delay specified value and if the gain of the variable gain amplifier (11) is not maximum.

Abstract: A radio receiver adapted to alternatively receive data over a communication channel in a first mode and a second mode. The second mode facilitates reception of data at higher data rates than the first mode. The radio receiver comprises a signal-processing unit and a control unit. The signal processing unit is adapted to determine a quality condition of the communication channel. The control unit is adapted to determine, based on the quality condition, whether the communication channel facilitates operation in the second mode and assess at least one configuration condition, one of the at least one configuration condition being that the communication channel is determined to facilitate operation in the second mode. The control unit is further adapted to configure the radio receiver to operate in the second mode when all of at least one configuration condition are fulfilled or to operate in the first mode otherwise. A method for controlling the radio receiver is also disclosed.

Abstract: A system includes a power amplifier, a preamplifier, a first temperature sensor, and a bias generator. The power amplifier has a first gain, which is a function of a temperature of the power amplifier. The preamplifier has a second gain, amplifies an input signal, and outputs an amplified signal to the power amplifier. The first temperature sensor senses the temperature and generates a first signal. The bias generator generates a first biasing signal to bias the power amplifier, generates a second biasing signal to bias the preamplifier, and adjusts the second gain by adjusting the second biasing signal based on the first signal. The adjusted second gain compensates a change in the first gain due to the change in the temperature.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

Abstract: An apparatus for controlling a power amplifier configured to amplify radio frequency (RF) signal includes a detector and a controller. The detector is configured to detect a power level of the RF signal with respect to a predetermined power threshold and to generate a corresponding detection signal. The controller is configured to provide a control voltage to an output transistor of the amplifier based on the detection signal. The control voltage has a low voltage value, which is substantially the same as a value of a supply voltage, when the detection signal indicates that the power level is below the power threshold, and the control voltage has a high voltage value when the detection signal indicates that the power level is above the power threshold. The controller generates the high voltage value by boosting the supply voltage.

Abstract: An apparatus for sensing power amplifier current includes a system voltage source that is used to develop a reference voltage, a wire bond structure connected between the system voltage source and a power amplifier, where a sense voltage developed across the wire bond structure is indicative of a current flowing through the power amplifier, and a current source configured to compensate the reference voltage for changes in resistance of the wire bond structure due to a temperature coefficient of the wire bond structure.

Abstract: A current-restriction circuit includes an input terminal to which an input voltage is input, an output terminal from which an output voltage is output, a driver transistor connected to the input terminal as well as the output terminal, a sense transistor connected to the output terminal as well as the input terminal via a sense resistor, a first operational amplifier circuit, and a bias-voltage change circuit. Control terminals of the driver transistor and the sense transistor are connected together and connected to an output terminal of the first operational amplifier circuit. The first operational amplifier circuit receives both a bias voltage with reference to an electrical potential at the input terminal and a decrease in a voltage at the sense resistor. The bias-voltage change circuit keeps the bias voltage below a predetermined bias voltage according to a voltage difference between the input voltage and the output voltage.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: A method for low noise signal amplification includes modifying a signal by way of a first amplification stage and conveying the modified signal to a second amplification stage. The method continues with comparing an output of the second amplification stage with a signal ground in a low-frequency feedback loop and changing a bias voltage for the first amplification stage as a result of the comparing step.

Abstract: A complex switch control system including many switches, a switching voltage control circuit and a comparator is provided. The switching voltage control circuit converts an operating voltage into a switching voltage according to the states of the switches. The comparator compares the switching voltage with a reference voltage and outputs a switch state signal to a keyboard controller. A duty cycle of the switch state signal corresponds to the states of the switches.

Abstract: A circuit arrangement and method for power regulation and an amplifier arrangement for power regulation are described.

Abstract: A driver circuit for a semiconductor laser diode (LD) is disclosed, in which the driver circuit drives the LD in the differential mode and lowers the power consumption thereof. The driver circuit includes a differential unit to provide the modulation current to the LD, a voltage converter to provide a positive power supply to the differential unit, a detector to detect the common mode voltage of the differential outputs of the unit, and a comparing unit to control the voltage converter dynamically such that the output common mode voltage is set in a preset reference level.

Abstract: An amplifying device comprises a first amplifying unit (91-97) capable of changing its gain in a stepwise manner, a second amplifying unit 99 cascade-connected to the first amplifying unit (91-97), the second amplifying unit being capable of changing its gain in a stepwise manner, and a gain controller 100 controls the gain setting of the first amplifying 91-97 unit and the second amplifying unit 99. The first amplifying unit has a gain variable range necessary to amplifying the input signal to the prescribed desired level. The second amplifying unit has a gain variable range narrower than that of the first amplifying unit. When the gain controller changes the gain setting, the gain controller uses the second amplifying unit preferentially over the first amplifying unit.

Abstract: An auto gain controller is provided. The auto gain controller includes a variable gain amplification unit configured to receive differential input signals, adjust an amplification gain based on an auto gain control voltage and output differential output signals. The auto gain controller also includes a peak detector configured to detect at least one peak value among the amplified differential output signals, a comparator configured to compare the at least one detected peak value with a reference voltage and generate a comparison signal, and a voltage adjusting circuit configured to adjust the auto gain control voltage and the reference voltage based on the comparison signal.

Abstract: An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

Abstract: Variable gain amplifiers with controllable gain gradient over temperature. A variable gain amplification circuit comprises an input terminal receiving an input signal, an output terminal outputting an output signal, and a control terminal receiving a first gain control signal. The relationship between gain of the variable gain amplification circuit and temperature is programmable rather than temperature independent, and is controlled by the first gain control signal obtained by a second gain control signal and a third gain control signal.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.

Abstract: A method of fast predictive automatic gain control is disclosed including estimating channel gain applied to a received signal, predicting channel gain at a subsequent time by applying temporal correlation statistics to the estimated channel gain, determining a predicted receiver gain which reduces variance between the predicted channel gain and a predetermined target power level, and applying the predicted receiver gain to the received signal. The method may include applying linear minimum mean-squared error prediction to the estimated channel gain. The method may include predicting error variance at the subsequent time by applying the temporal correlation statistics to the estimated channel gain and combining the predicted channel gain and the predicted error variance.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

Abstract: A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.

Abstract: A gain adjustment device and a method thereof are provided. The device includes a first processing module, a gain adjustment circuit, a second processing module, and a gain control module. The first processing module receives an input signal and generates a first signal. An operating voltage of the first processing module is a first voltage. The gain adjustment circuit receives the first signal and adjusts a gain of the first signal according to a gain control signal to output a third signal. The second processing module receives the third signal and generates a second signal. An operating voltage of the second processing module is a second voltage. The gain control module generates the gain control signal according to the first voltage and the second voltage.

Abstract: A receiving apparatus may achieve optimal RF and IF gain control while suppressing saturated amplification due to interference. The receiving apparatus includes an RF variable gain Amp that amplifies a received RF signal, a mixer that converts an output signal of the RF variable gain Amp into an IF signal, an IF variable gain Amp that amplifies the IF signal, a demodulator that demodulates an output signal of the IF variable gain Amp, and an AGC circuit. The AGC circuit sets a period of gain control for the RF variable gain Amp to be shorter than a period of gain control for the IF variable gain Amp when gains of the RF variable gain Amp and the IF variable gain Amp are controlled based on the output signal of the IF variable gain Amp.

Abstract: A system and method for modulating the sound pressure that is output from an audio transducer is disclosed. In one embodiment, the method includes receiving an audio signal and placing the audio signal across a voice coil of the transducer. In addition, a voltage is applied across a field coil of the transducer, the field coil being separate from the voice coil. And the voltage that is applied across the field coil is adjusted so as to modulate the sound pressure output from the audio transducer.

Abstract: Some embodiments discussed relate to an apparatus comprising a power amplifier module. The power amplifier module includes a plurality of sensors, and a first digital communication port configured to provide a monitor signal from at least one of the plurality of sensors. The apparatus includes a transceiver module coupled to provide an signal to an input of the power amplifier the transceiver module including a second digital communication port configured to receive the monitor signal from the first digital communication port, a processing unit configured to generate at least one of a bias control signal and a back-off signal dependent upon the monitor signal, and a power controller to receive the at least one of bias control signal and the back-off signal and provide at least one further input signal to the power amplifier based on at least one of the bias control signal and the back-off signal.

Abstract: A count control signal generating section for generating a count control signal on the basis of an output signal of a variable gain amplifier; an up/down counter for performing an up-count operation or a down-count operation on the basis of the count control signal; a gain control signal generating section for generating a gain control signal to be supplied to the variable gain amplifier on the basis of a count value of the up/down counter; and a state detector section for outputting a state detection signal indicating whether a state of a circuit operation is a steady state or another state are provided. When the state detection signal indicates that the state of the circuit operation is the steady state, the operation of at least one of the up/down counter and the gain control signal generating section is controlled so as to fix the gain control signal.

Abstract: A gain circuit includes an analog section with variable gain and a digital section with variable gain. The gain steps for the digital section have a higher resolution than the gain steps for the analog section. In some implementations, gain steps can be achieved much finer than 0.1 db or less without sensitivity to device tolerances.

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract: Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: A gain control circuit and its gain control method, said gain control method comprising the following steps: firstly, outputting continuously a counter value; next, generating a ramp wave signal based on said counter value, and at a voltage where a control voltage signal intersects said ramp wave signal, obtaining an initial counter value based on said ramp wave signal, thus determining an initial voltage gain of an amplifier circuit; then, when a high or low voltage of an output signal of said amplifier circuit is greater or less than a predetermined detection voltage upper or lower limit, adjusting a DC voltage level of said ramp wave signal with a detection signal; and finally, obtaining at said voltage a counter value less than said initial counter value based on said ramp wave signal, hereby reducing said initial voltage gain based on said counter value.

Abstract: A low noise variable gain amplifier and method for processing received signals in an ultrasound medical imaging system is disclosed. Unlike solutions known from the prior art, the signals are amplified by a binary-coded gain amplifier having its amplification factor progressively increased during the penetration of the transmitted pulse into a patient's body. This allows enhancing both the system dynamic range and Signal to Noise Ratio.

Abstract: A generator for use with an electrosurgical device is provided. The generator has a gain stage electrically disposed between a first voltage rail and a second voltage rail, wherein the gain stage includes an input and an output. A voltage source operably coupled to the gain stage input and configured to provide an input signal thereto responsive to a drive control signal is also provided. The generator also has one or more sensors configured to sense an operational parameter of the amplifier and to provide a sensor signal corresponding thereto and a controller adapted to receive the sensor signal(s) and in response thereto provide a drive control signal to the voltage source.

Abstract: A device including a gain control element coupled prior to or within a radio frequency (RF) power amplifier (PA) with an adaptive parametric PA protection circuit is described. In an exemplary embodiment, the device includes a gain control element coupled prior to a radio frequency power amplifier with a power stage with corresponding transistor breakdown threshold values, having an adaptive parametric PA protection circuit configured to receive at least one power stage drain-source voltage parameter value, at least one power stage drain-gate voltage parameter value, and at least one power stage drain-source current parameter value, and including an adaptive parametric PA protection circuit having a first section for processing the parameter values and a second section for generating a gain correction signal to adjust the gain control element with optimal power added efficiency (PAE) for the power stage within the corresponding transistor breakdown threshold values.

Abstract: An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.