Including Current Mirror Amplifier Patents (Class 330/288)
  • Patent number: 10256778
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Patent number: 10250202
    Abstract: Power amplification system with adjustable common base bias. A power amplification system can include a cascode amplifier coupled to a radio-frequency input signal and coupled to a radio-frequency output. The power amplification system can further include a biasing component configured to apply one or more biasing signals to the cascode amplifier, the biasing component including a bias controller and one or more bias components. Each respective bias component may be coupled to a respective bias transistor.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: April 2, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip John Lehtola, Scott W Coffin
  • Patent number: 10230332
    Abstract: Apparatus and methods for biasing low noise amplifiers are provided herein. In certain configurations, a low noise amplifier (LNA) includes an input, an output, a transconductance device, a cascode device, a bias current source, and a feedback bias circuit. The transconductance device generates an amplified signal by amplifying an input signal received at the input, and provides the amplified signal to the output via the cascode device. The bias current source generates a bias current that flows through the cascode device and the transconductance device. The feedback bias circuit provides feedback from the LNA's output to the LNA's input to control an input bias voltage of the transconductance device.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Engin Ibrahim Pehlivanoglu
  • Patent number: 10218324
    Abstract: At least some embodiments are directed to a system that comprises a differential input transistor pair (DITP) comprising first and second transistors, a first feedback loop coupled to the first transistor, and a second feedback loop coupled to the second transistor. When a differential voltage applied to the input stage is within a first range, the first and second feedback loops control a tail current supplied to the DITP, where the tail current at least partially determines a transconductance of the DITP. When the differential voltage is within a second range, the transconductance of the DITP is at least partially determined by a first resistor in the first feedback loop or by a second resistor in the second feedback loop.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 26, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas K. Pulijala
  • Patent number: 10148226
    Abstract: A bias circuit includes first to fourth bipolar transistors and a filter circuit. The third bipolar transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: December 4, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Soga
  • Patent number: 10027320
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 17, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun Goo Won, Youn Suk Kim, Yoshiyuki Tonami, Ki Joong Kim
  • Patent number: 9996093
    Abstract: A semiconductor integrated circuit for a regulator includes the following: a voltage controlling transistor; a controlling circuit; a first and second transistor; a first external terminal to connect a current voltage converting element; a first and second voltage comparing circuit which compares a converted voltage with a predetermined comparison voltage and determines which is large or small; and a first and second output terminal which externally outputs a result of comparison by the first and second voltage comparing circuit, respectively. When a current larger than a predetermined open-circuit abnormality detecting current value flows in the first transistor, output of the first voltage comparing circuit is inverted. When a current larger than a predetermined short-circuit abnormality detecting current value flows in the second transistor, output of the second voltage comparing circuit is inverted.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 12, 2018
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Yoichi Takano, Shinichiro Maki
  • Patent number: 9813030
    Abstract: System-on-chip (SOC) products using high frequency, wideband, highly linear, CMOS and BiCMOS processes will be the next evolution of wireless and wireline communications integrated circuits. Aspects described herein can provide enhanced overall performance over existing prior art single-ended, wideband RF amplifier topologies. A single-ended third order intermodulation distortion nulling circuit can extend the dynamic range for wideband amplifiers up to an order-of-magnitude, without a DC power or noise figure (NF) penalty. The application of distortion nulling can be extended to all the building blocks used in CMOS/BiCMOS RF transceivers to improve performance. The application of this concept to all of the building blocks in an RF transceiver will allow the dynamic range of the transceiver to be increased without suffering a DC power dissipation increase or a significant noise increase.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 7, 2017
    Inventors: Wais M. Ali, Lloyd F. Linder
  • Patent number: 9722542
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 1, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 9698853
    Abstract: Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: July 4, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Paul Raymond Andrys, David Steven Ripley, Matthew Lee Banowetz, Kyle James Miller
  • Patent number: 9690316
    Abstract: An integrated circuit includes: a source current generation block suitable for generating a source current; a first mirroring block suitable for generating first and second mirroring currents corresponding to the source current; a second mirroring block suitable for generating a third mirroring current and a reference current corresponding to the first mirroring current; a first correction block suitable for correcting a current mismatch between the source current, the first mirroring current and the second mirroring current based on the third mirroring current; and a second correction block suitable for correcting a current mismatch between the first mirroring current, the third mirroring current and the reference current based on the second mirroring current.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Gun-Hee Yun
  • Patent number: 9661695
    Abstract: A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 23, 2017
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Guangjie Cai, Ho Ming (Karen) Wan, Chun Fai Wong, Tai Yin Wong
  • Patent number: 9654155
    Abstract: According to some implementation, a power amplifier includes a plurality of pairs of transistors, each pair of transistors including a common emitter transistor and a common base transistor arranged in a cascode configuration. The power amplifier further includes electrical connections implemented to connect the plurality of pairs in a parallel configuration between an input node and an output node. According to some implementations, the electrical connections are configured to distribute a collector current to all of the common base transistors to thereby reduce likelihood of damage to one or more common base transistors during a thermal run-away event.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 16, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 9444418
    Abstract: A transistor cell can be modeled as a transistor with a collector, a base, and an emitter operating with a current at the collector to produce a minimum transconductance in the transistor cell that increases a current gain and improves at least one operating characteristic of the transistor cell. The operating characteristics include bandwidth, gain, and output power.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 13, 2016
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 9413313
    Abstract: Multimode power amplifier bias circuit with selectable bandwidth. In some embodiments, a bias circuit for a power amplifier can include a first bipolar junction transistor (BJT) configured to pass a reference current. The first BJT can be coupled with a second BJT that performs at least some amplification for the power amplifier. The first and second BJTs can be configured as a current mirror. The bias circuit can further include a coupling circuit that couples the collector and the base of the first BJT. The coupling circuit can include a switchable element to allow the coupling circuit to be in a first state or a second state. The first state can be configured to yield a first bandwidth for the bias circuit, and the second state can be configured to yield a second bandwidth for the bias circuit.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: August 9, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Ramanan Bairavasubramanian, Michael Lynn Gerard, Philip H. Thompson
  • Patent number: 9379669
    Abstract: A calibration solution for a power amplifier array comprising a plurality of amplifier cells is presented that improves the linearity and efficiency of the power amplifier, especially when only a small number of the amplifier cells are active. To that end, a bias control word is selected from a predetermined bias table for each of the active power amplifier cells. An average of the selected bias control words is then used to bias an input stage of each active power amplifier cell. The solution presented herein provides techniques for determining the bias control words, as well as using the bias control words.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: June 28, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Ossi Toivonen, Sami Vilhonen
  • Patent number: 9372351
    Abstract: A circuit includes a front-end circuit, a receiver stage and a controller. An example front-end circuit includes a common base input device, a first current mirror and a second current mirror, where the common base input device has its emitter coupled to a photodiode, its collector coupled to an input of the first current mirror, and its base coupled to a reference voltage to reverse bias the photodiode and where an output of the first current mirror is input into the second current mirror. In another example, a voltage drop resistor is coupled to a cancellation signal output of the first current mirror and an operational transimpedance amplifier (OTA) has inputs coupled to the voltage drop resistor and to a reference voltage and an output coupled to a compensating impedance and to a control input of a variable current source designed to feed the emitter signal input.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: June 21, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Theron Lee Jones, Richard Dean Davis
  • Patent number: 9310817
    Abstract: Embodiments of the invention generally provide an device that regulates a negative output voltage from a power supply using a positive representation of the negative output voltage. To convert the negative voltage to a positive voltage, the device changes the negative voltage into a current using, for example, a current generator that outputs a current corresponding to the negative voltage received from the power supply. This current is then transferred from the negative voltage domain to the positive voltage domain and is fed through a voltage generator that outputs a positive voltage corresponding to the current. By doing so, the negative voltage output is transformed into a corresponding positive voltage. This positive voltage may then be compared to a positive reference voltage to determine an error signal for adjusting the power supply.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 12, 2016
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Mark Pude
  • Patent number: 9287832
    Abstract: A power amplifying module includes a radio frequency amplifying circuit including an amplifying circuit configured to amplify an input signal and output an amplified signal, and a bias circuit of an emitter-follower type configured to bias the amplifying circuit to an operating point, and a constant voltage generating circuit configured to generate, from a first reference voltage, a first constant voltage applied to a base side of a transistor of the bias circuit and a second constant voltage applied to a collector side of the transistor.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 15, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroshi Hagisawa, Satoshi Sakurai
  • Patent number: 9214929
    Abstract: An AC-inverting amplifier for a waveform conversion circuit includes a first MOS transistor of a first conductivity type having a gate that receives an input signal, a drain that provides an inverted amplified output signal, and a source coupled to a first power supply voltage. A current source provides a first bias current and a second bias current in proportion to the first bias current. The second bias current is coupled to the drain of the first MOS transistor to bias the first MOS transistor. The first bias current has a magnitude that is determined by a DC voltage applied at the gate of the first MOS transistor.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Zhengxiang Wang
  • Patent number: 9203368
    Abstract: A power amplifier includes: a first transistor having a gate, a drain, and a source that is grounded; a second transistor having a gate, a drain, and a source that is connected to the drain of the first transistor; a capacitor connected between the gate of the second transistor and a grounding point; an idling current control circuit having a positive temperature coefficient and making an idling current flowing through the first transistor proportional to an ambient temperature; and a drain voltage control circuit having a positive temperature coefficient and making a drain voltage on the first transistor proportional to the ambient temperature.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: December 1, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Miyo Miyashita, Yoshinori Takahashi, Kazuya Yamamoto
  • Patent number: 9182770
    Abstract: A voltage regulator includes a current bridge and first and second current paths coupling a current mirror to respective first and second voltage-to-current converters. The current mirror controls a second current dependent on a first current. The first voltage-to-current converter controls the first current dependent on either a reference voltage or a feedback voltage derived from the regulator's output voltage, and the second voltage-to-current converter controls the second current dependent on the other of the feedback and reference voltages. Voltage-to-current conversion by the first converter is independent of voltage-to-current conversion by the second converter. An output transistor stage coupled to the second current path controls the output voltage dependent on the voltage in the second current path indicative of a deviation of the second current from a target current value dependent on the reference voltage.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 10, 2015
    Assignee: ST-Ericsson SA
    Inventors: Willem Groeneweg, Nedyalko Slavov
  • Patent number: 9176511
    Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Nam Van Dang, Rajeev Jain, Terrence Brian Remple, Jingcheng Zhuang, Mong Chit Wong
  • Patent number: 9166533
    Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: October 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas D. Marra, Aristotele Hadjichristos, Nathan M. Pletcher
  • Patent number: 9130509
    Abstract: A device includes a low noise amplifier (LNA) for amplifying an input signal, with the LNA including a first transistor configured to receive the input signal, a second transistor configured to receive a bias current and forming a current mirror for the first transistor, and an operational amplifier (op amp) operative to generate a bias voltage for the first and second transistors to match operating points of the first and second transistors.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Xu, Timothy Paul Pals, Kevin Hsi Huai Wang
  • Publication number: 20150130647
    Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Tetsuro ITAKURA, Masanori FURUTA, Akihide SAI, Junya MATSUNO, Yohei HATAKEYAMA
  • Patent number: 9030259
    Abstract: A system for pre-charging a current minor includes a controller configured to provide a first current and an additional current to a current minor to rapidly charge a capacitance associated with the current minor based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: May 12, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Robert Michael Fisher, Michael L. Hageman, David Steven Ripley
  • Patent number: 9000846
    Abstract: Some embodiments of the system comprise a current mirror with two switches (a first switch and a second switch) and two compensation circuits (a first compensation circuit and a second compensation circuit). In one embodiment, the first compensation circuit adjusts a drain voltage of the second switch based on a drain voltage of the first switch, and the second compensation circuit adjusts a current through the first switch based on the drain voltage of the second switch.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 7, 2015
    Assignee: VIA Technologies, Inc.
    Inventor: Yeong-Sheng Lee
  • Publication number: 20150061771
    Abstract: An AC-inverting amplifier for a waveform conversion circuit includes a first MOS transistor of a first conductivity type having a gate that receives an input signal, a drain that provides an inverted amplified output signal, and a source coupled to a first power supply voltage. A current source provides a first bias current and a second bias current in proportion to the first bias current. The second bias current is coupled to the drain of the first MOS transistor to bias the first MOS transistor. The first bias current has a magnitude that is determined by a DC voltage applied at the gate of the first MOS transistor.
    Type: Application
    Filed: May 15, 2014
    Publication date: March 5, 2015
    Inventor: Zhengxiang Wang
  • Publication number: 20150061772
    Abstract: Circuits and methods to reduce the size of output capacitors of LDOs or amplifiers are disclosed. Nonlinear mirroring of the load current allows scaling of gain or adapting small signal impedance of a pass transistor depending on other inputs, in case of a preferred embodiment, allows to reduce small signal impedance at the gate of the pass transistor as the load current increases, hence allowing to reduce the size of an output capacitor without compromising stability of the system.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventor: Ambreesh Bhattad
  • Publication number: 20150061770
    Abstract: Various embodiments provide a bias circuit for a radio frequency (RF) power amplifier (PA) to provide a direct current (DC) bias voltage, with bias boosting, to the RF PA. The bias circuit may include a bias transistor that forms a current mirror with an amplifier transistor of the RF PA. The bias circuit may further include a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor. The bias circuit may further include a second resistor coupled between the drain terminal of the bias transistor and the RF PA (e.g., the gate terminal of the amplifier transistor). An amount of bias boosting of the DC bias voltage provided by the bias circuit may be based on an impedance value of the second resistor.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Sifen Luo, Kerry Burger, George Nohra
  • Patent number: 8913050
    Abstract: A plurality of transistors in which ratios of a channel length L to a channel width W, ?=W/L, are different from each other is provided in parallel as output side transistors 105a to 105c in a current mirror circuit 101 which amplifies a photocurrent of a photoelectric conversion device and an internal resistor is connected to each of the output side transistors 105a to 105c in series. The sum of currents which flow through the plurality of transistors and the internal resistor is output, whereby a transistor with large amount of ? can be driven in a linear range with low illuminance, and a transistor with small amount of ? can be driven in a linear range with high illuminance, so that applicable illuminance range of the photoelectric conversion device can be widened.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Atsushi Hirose
  • Publication number: 20140361835
    Abstract: Some embodiments of the system comprise a current mirror with two switches (a first switch and a second switch) and two compensation circuits (a first compensation circuit and a second compensation circuit). In one embodiment, the first compensation circuit adjusts a drain voltage of the second switch based on a drain voltage of the first switch, and the second compensation circuit adjusts a current through the first switch based on the drain voltage of the second switch.
    Type: Application
    Filed: July 11, 2013
    Publication date: December 11, 2014
    Inventor: Yeong-Sheng Lee
  • Patent number: 8907725
    Abstract: Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 8903342
    Abstract: A high dynamic range precision variable amplitude controller includes a gain portion configured to apply a controllable amount of amplitude adjustment to an input signal. The gain portion includes two or more amplification stages each amplification stage having branches that are cross-coupled with branches of the other amplification stage. A control portion controls the current supply to the two or more amplification stages to control the amount of amplitude adjustment by the gain portion. The amplitude controller also includes a load portion that provides balanced impedances to the cross-coupled branches of the amplification stages throughout the amplitude control range.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 2, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 8901474
    Abstract: An optical transceiver and/or optical network, and methods of monitoring optical transceivers, may be useful for increasing the dynamic range and/or determining the received signal strength and/or link budget of the optical transceiver and/or a different optical transceiver in the optical network. The circuitry generally comprises a photodiode configured to generate a first current responsive to an optical signal, a current mirror configured to produce a second current equal or proportional to the first current, and a nonlinear element configured to produce a first voltage from the first current.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Source Photonics, Inc.
    Inventor: Mohammad Azadeh
  • Patent number: 8901998
    Abstract: A current-voltage converter with a current reflector, for which the input current includes a fixed component and a variable component, includes an input for the current to be converted, an output for the converted voltage, two constant current sources each connected between the output and a respective reference voltage, at least one MOSFET transistor mounted in series with each constant current source, and a resistor for converting the current into a voltage, arranged between the output and ground. The gate of each MOSFET transistor is connected to one of the reference voltages. The input for the current to be converted is connected to the output through one of the MOSFET transistors. The converted further includes, for each MOSFET transistor, means for re-injecting into at least one of the current sources, a current equal to the current absorbed in the gates of the MOSFET transistors.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: December 2, 2014
    Assignee: Devialet
    Inventors: Mathias Moronvalle, Pierre-Emmanuel Calmel
  • Publication number: 20140347130
    Abstract: The invention provides a semiconductor integrated circuit device and a high-frequency power amplifier module capable of reducing variations in the transmission power characteristics. The semiconductor integrated circuit device and the high-frequency power amplifier module each include, for example, a bandgap reference circuit, a regulator circuit, and a reference-voltage correction circuit which is provided between the bandgap reference circuit and the regulator circuit and which includes a unity gain buffer. The reference-voltage correction circuit corrects variations in a bandgap voltage from the bandgap reference circuit. The reference-voltage correction circuit includes first to third resistance paths having mutually different resistance values, and corrects the variations by selectively supplying a current which reflects an output voltage of the unity gain buffer to any one of the first to third resistance paths.
    Type: Application
    Filed: December 5, 2012
    Publication date: November 27, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masanori Iijima, Fuminori Morisawa
  • Publication number: 20140340154
    Abstract: Embodiments relate to systems and methods for image lag mitigation for a buffered direct injection readout circuit with current mirror. A photo detector device is coupled to a buffered direct injection (BDI) circuit, in which an operational amplifier and other elements communicate the output signal from the detector to subsequent stages. The BDI output is transmitted to a first current mirror, which can be implemented as a S├Ąckinger current mirror. The first current mirror is coupled to a second current mirror, one of whose outputs is a fixed bias current. Image lag can be controlled by the fixed bias current, rather than the photocurrent produced directly by the optical detector. In aspects, the negative feedback provided by the first current mirror can increase the modulation of the second current mirror. This gain factor can reduce image lag to a significantly lower point than the lag experienced by known BDI-current-modulated readout circuitry without S├Ąckinger current mirror.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 20, 2014
    Inventor: Minlong Lin
  • Patent number: 8878612
    Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 4, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Poh Boon Leong, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 8854139
    Abstract: There is described an amplification stage comprising: a current mirror circuit comprising a reference transistor arranged to receive a current associated with an input signal and an output transistor providing a current source for an output signal line; a current sink to the output signal line, under the control of the input signal; circuitry arranged to maintain equality between the drain/collector voltages on the transistors of the current mirror circuit.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Nujira Limited
    Inventor: Russell Fagg
  • Patent number: 8854140
    Abstract: A current mirror circuit having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation producing current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Frank J. DeCaro, John C. Tremblay
  • Patent number: 8847684
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 30, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Patent number: 8841970
    Abstract: Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 23, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Arash Mehrabi, Thurman S. Deyerle, IV, Guoqing Miao
  • Publication number: 20140232467
    Abstract: A high-frequency amplifier module includes a driver-stage amplifier 3 that amplifies an RF signal input thereto from an RF input terminal 1, and a final-stage amplifier 5 that amplifies the signal amplified by the driver-stage amplifier 3 and outputs the signal after the amplification to an RF output terminal 7. The driver-stage amplifier 3 is fabricated on a silicon substrate 11, while the final-stage amplifier 5 is fabricated on a gallium arsenide substrate. This configuration downsizes the cost while maintaining a high-frequency characteristic comparable to that in the case where all components of an entire module are fabricated on a gallium arsenide substrate 71.
    Type: Application
    Filed: August 24, 2012
    Publication date: August 21, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji Mukai, Kenichi Horiguchi, Morishige Hieda, Katsuya Kato, Yoshihito Hirano, Kazuya Yamamoto, Hiroyuki Joba, Teruyuki Shimura
  • Patent number: 8803612
    Abstract: A low-noise amplifier with high linearity has two common source FET amplifying stages, where the amplifier performance is linearized by use of a second stage active biasing circuit including a current mirror with a feedback network. The linearity improvement technique is employed on a 0.5-2 GHz flat gain amplifier. The improvement causes nodegradation to other RF parameters and allows for the amplifier circuit to be realized in a gallium arsenide microwave monolithic integrated circuit.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Scientific Components Corporation
    Inventors: Ben Zee Min Ooi, Chee Ling Wong, Cheng Wei Hoh
  • Patent number: 8791759
    Abstract: An amplifier for an integrated circuit has a plurality of ratioed current mirrors connected to each other in a stacked configuration. Each ratio mirror has at least two resistors and at least two bipolar transistors connected to each other via said at least two resistors. Each amplifying transistor, contains a capacitor, and potentially and inductor, to internally match the transistors that make up the amplifying stack. DC, harmonic and s-parameter simulations are performed to provide an optimal impedance for each of the stacked transistors to maximize the RF power output of each stacked layer and the amplifier.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 29, 2014
    Assignees: The United States of America as Represented by the Secretary of the Army, The George Washington University
    Inventors: Ali Darwish, Thomas J. Farm, Mona Zaghloul
  • Patent number: 8791761
    Abstract: A radio frequency (RF) power amplifier is disclosed. The power amplifier includes an output stage circuit, an exponential type bias circuit and a voltage-current transformation circuit. The output stage circuit receives a first system voltage and outputs an output current. The exponential type bias circuit receives a bias current, wherein a relationship between the bias current and output current is exponential, and when the bias current is zero current, and the output current is zero current. The voltage-current transformation circuit transforms the first system voltage into a second current so that the bias current is in proportion to the first system voltage, and thus the relationship between the output current and the first system voltage is exponential. The bias current is equal to times of the sum of the first current and the second current.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 29, 2014
    Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Jaw-Ming Ding, Wei-Hsuan Lee
  • Patent number: 8760227
    Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: June 24, 2014
    Assignee: Atmel Corporation
    Inventors: Armin Prohaska, Terje Saether, Holger Vogelmann
  • Publication number: 20140139290
    Abstract: A system for pre-charging a current minor includes a controller configured to provide a first current and an additional current to a current minor to rapidly charge a capacitance associated with the current minor based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.
    Type: Application
    Filed: October 23, 2013
    Publication date: May 22, 2014
    Applicant: Skyworks Solutions, Inc.
    Inventors: Robert Michael Fisher, Michael L. Hageman, David S. Ripley