Including Current Mirror Amplifier Patents (Class 330/288)
  • Patent number: 8073078
    Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: December 6, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Daniel L. Kaczman, Manish N. Shah
  • Publication number: 20110285466
    Abstract: A power amplifier circuit has a Gm amplifier, first and second transistors, third and fourth transistors consisting a mirror circuit, fifth and sixth transistors consisting a mirror circuit, seventh and eighth transistors consisting a mirror circuit, a ninth transistor of the first conductivity type which is connected at a first end thereof to the first power supply rail, connected at a second end thereof to a signal output terminal for outputting an amplified signal, and connected at a control terminal thereof to the inverting output terminal, and a tenth transistor of the second conductivity type connected at a first end thereof to the signal output terminal, connected at a second end thereof to the second power supply rail, and connected at a control terminal thereof to the noninverting output terminal.
    Type: Application
    Filed: February 28, 2011
    Publication date: November 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Takida, Ryota Miwa
  • Patent number: 8058909
    Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: November 15, 2011
    Assignee: NEC Corporation
    Inventor: Hiroyuki Okada
  • Publication number: 20110260796
    Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 27, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi TANAKA, Fuminori MORISAWA, Makoto TABEI
  • Publication number: 20110227653
    Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 22, 2011
    Applicant: STMicroelectronics (Crolles2) SAS
    Inventor: Hubert Degoirat
  • Patent number: 8022767
    Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit configured to receive an input signal. A bias circuit is configured to receive an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit is in communication with the bias circuit. The second Class AB amplifier circuit is configured to generate an output signal. A current mirror circuit is arranged between the first Class AB amplifier circuit and the bias circuit. A common-mode feedback circuit is configured to generate a feedback signal based on the output signal.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 20, 2011
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20110210795
    Abstract: A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amplification transistor which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit comprising a replicating transistor. The amplification transistor amplifies an RF signal and a bias current of the bias control circuit is supplied to the bias transistor. The transistors are fabricated by the same semiconductor manufacturing process, and have the same variation of gate length. The gate length monitor circuit generates a detection voltage depending on the gate length. According to the detection voltage, the bias control circuit controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor.
    Type: Application
    Filed: February 17, 2011
    Publication date: September 1, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Ikuma OHTA, Norio HAYASHI, Takayuki TSUTSUI, Fuminori MORISAWA, Masatoshi HASE
  • Patent number: 8004362
    Abstract: Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor (102) that is used for the bias circuit, and all of or part of the other unit transistors are connected in parallel and used as amplifier (101).
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: August 23, 2011
    Assignee: NEC Corporation
    Inventor: Tomohisa Hirayama
  • Patent number: 7999619
    Abstract: The present disclosure relates to a class AB amplifier output stage.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: August 16, 2011
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 7994861
    Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 9, 2011
    Assignee: Skyworks Solutions, Inc.
    Inventors: Robert Michael Fisher, Michael L. Hageman, David S. Ripley
  • Patent number: 7994859
    Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: August 9, 2011
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20110133842
    Abstract: A radio-frequency amplifier includes a common gate amplification stage configured to be biased in a saturation condition with a first current and configured to receive an input signal as a gate-source voltage and to generate an output voltage as an amplified replica of the input signal. A feedback transistor is configured to be biased in a saturation condition with a second current and coupled to the common gate amplification stage so as to have a gate-drain voltage corresponding to a difference between the output voltage and the input signal.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 9, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Ranieri Guerra, Giuseppe Palmisano
  • Patent number: 7948319
    Abstract: One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a first current path that includes a first degeneration resistance device and to generate an output current that flows through a second current path that includes a second degeneration resistance device. The output current can be substantially proportional to the input current. The system also includes a degeneration control circuit configured to maintain a substantially constant degeneration voltage across each of the first and second degeneration resistance devices.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Rajarshi Mukophadhyay, Sharifi Reza
  • Patent number: 7917120
    Abstract: An RF mixer provides extended dynamic range with reduced noise by utilizing degeneration inductors in the RF input section of a doubly balanced mixer. Degeneration inductors are also utilized in a mixer having a class AB input section. A current mirror in the class AB input section is also inductively degenerated for further noise reduction. The input section is biased by an all-NPN bandgap reference cell which is tightly integrated into the input section so as to reduce the power supply voltage required for the reference cell. The mixer can be optimized for wide input voltage ranges or low distortion.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: March 29, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 7915958
    Abstract: An amplifier comprises an input terminal that inputs an AC voltage signal; an amplifying unit having a transistor for amplifying the input AC voltage signal; a current detecting unit connected internally of said amplifying unit; and a control-current source controlled by said current detecting unit that drives an input stage of the transistor.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Ooyabu
  • Patent number: 7915948
    Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 7911274
    Abstract: The variable transconductance circuit includes: a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal; first and second MOS transistors for converting the current signal received to a square-root compressed voltage signal; and third and fourth MOS transistors for converting the square-root compressed voltage signal to a linear current signal. A bias current at the first and second MOS transistors and a bias current at the third and fourth MOS transistors are varied to control transconductance.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroyasu Morikawa, Masamichi Katada, Marie Nishinaka
  • Patent number: 7907012
    Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Sandro Herrera
  • Patent number: 7898335
    Abstract: There is provided an amplifier circuit includes: an amplifying transistor; a first transistor having a DC current amplification factor generally equal to the DC current amplification factor of the amplifying transistor and constituting a current mirror circuit in conjunction with the amplifying transistor; and a current source circuit being operable to supply a current to the first transistor and including a second transistor having opposite conductivity type to the conductivity type of the first transistor. The second transistor is operated in a saturation region at a power supply voltage lower than an operating voltage range so that the DC current amplification factor of the amplifying transistor can be detected.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: March 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Teraguchi
  • Publication number: 20110032037
    Abstract: A power amplifier bias circuit having a controllable current profile includes a first transistor device configured as a switch, and configured to receive a non-regulated system voltage, and a plurality of resistors configured to provide a current and configured to determine an amount of a bias current that flows through a second transistor device, where the second transistor device is part of a current mirror comprising a third transistor device and the amount of bias current flowing through the second transistor device determines a power output of the third transistor device.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 10, 2011
    Applicant: Skyworks Solutions, Inc.
    Inventors: Li-hung Kang, Younkyu Chung
  • Patent number: 7876158
    Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: January 25, 2011
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Yut Hoong Chow, Hiang Teik Tan
  • Publication number: 20110006847
    Abstract: A circuit includes a first transistor in a common-collector configuration and a heterojunction bipolar transistor (HBT) in a common-emitter configuration. The first transistor has a base coupled to an input node for receiving a pulsed signal. A collector of the first transistor is coupled to a first voltage source node. A base of the HBT is coupled to an emitter of the first transistor. A collector of the HBT is coupled to a second voltage source node configured to bias the HBT normally off. The HBT operating isothermally when the pulsed signal has a short-pulse width and a low duty cycle. The first transistor drives the HBT when the pulsed signal is received at the base of the first transistor to output an amplified pulsed signal at the collector of the HBT.
    Type: Application
    Filed: April 3, 2009
    Publication date: January 13, 2011
    Applicant: LEHIGH UNIVERSITY
    Inventors: Subrata Halder, Renfeng Jin, James C.M. Hwang
  • Publication number: 20110001565
    Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal.
    Type: Application
    Filed: August 3, 2010
    Publication date: January 6, 2011
    Inventor: Sehat Sutardja
  • Patent number: 7863985
    Abstract: An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: January 4, 2011
    Assignee: Texas Instruments Incorporation
    Inventors: Marco Corsi, Kenneth G. Maclean
  • Patent number: 7843372
    Abstract: In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takahiro Kawano
  • Publication number: 20100295620
    Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit configured to receive an input signal. A bias circuit is configured to receive an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit is in communication with the bias circuit. The second Class AB amplifier circuit is configured to generate an output signal. A current mirror circuit is arranged between the first Class AB amplifier circuit and the bias circuit. A common-mode feedback circuit is configured to generate a feedback signal based on the output signal.
    Type: Application
    Filed: August 3, 2010
    Publication date: November 25, 2010
    Inventor: Sehat Sutardja
  • Publication number: 20100271134
    Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Yut Hoong Chow, Hiang Teik Tan
  • Publication number: 20100264987
    Abstract: An amplifier with bias stabilizer includes first to forth transistors, an amplifier unit and a resistor. The first transistor and the second transistor are connected in series between first and second power supplies and generate a first current. The third transistor is connected in a current mirror configuration to the second transistor and generates a second current corresponding to the first current. The amplifier unit generates an output signal based on an input signal and includes a fourth transistor, the fourth transistor generating a control voltage according to the second current so as to control the first transistor. The resistor is connected in series to at least one of the first to fourth transistors.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 21, 2010
    Inventor: Tachio YUASA
  • Patent number: 7812668
    Abstract: A multi-input operational amplifier comprises two transconductors, two current mirrors, and a current source. Each transconductor generates a current according to a corresponding voltage difference. When the voltage difference is less than or equal to zero, the current is a constant. When the voltage difference exceeds zero, the current is proportional to the voltage difference.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: October 12, 2010
    Assignee: Advanced Analog Technology, Inc.
    Inventor: Yung Ching Chang
  • Publication number: 20100245151
    Abstract: Techniques for detecting jammer signals in a received signal are described. In one aspect, high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. In another aspect, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block, which can be used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. The digital jammer detection circuit aids in the determination of the presence of jammer signals within the received signal, the determination of which may be variable due to programmability of the digital jammer detection circuit as described.
    Type: Application
    Filed: October 20, 2009
    Publication date: September 30, 2010
    Applicant: QUALCOMM Incorporated
    Inventors: Harish S. Muthali, Shreyas Sen
  • Patent number: 7804286
    Abstract: An amplifier/comparator includes a multitude of output stages all sharing the same input stage. One or more of the output stages are amplification stages and have compensated output signals. A number of other output stages are not compensated and provide comparison signals. Each uncompensated output stage is adapted to switch to a first state if it detects a first input signal as being greater than a second signal, and further to switch to a second state if it detects the first input signal as being smaller than the second signal. By varying the channel-width (W) to channel-length (L) ratio (W/L) of the transistors disposed in the output stages, the trip points of the comparators and/or the electrical characteristics of the amplifiers are selectively varied.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: September 28, 2010
    Assignee: Linear Technology Corporation
    Inventor: Damon Lee
  • Patent number: 7795980
    Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: September 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James R. Griffiths, David M. Gonzalez, Elie A. Maalouf
  • Publication number: 20100219892
    Abstract: The present invention relates to a circuit configuration for detecting and rapidly limiting large current increase based on high current injection at the output terminal (out). In particular, a gate-controlled switching device (PO), controlled by a driver circuit (40) through a low resistive element (RO) and passed through by a current overshoot, will be alternatively driven by the circuit of the present invention while having its control terminal charged by the high injected current. Thus, when large voltage increase generated by a steep front impulse with a positive slope is detected by the capacitor (C) and transmitted to the gate terminal (GateN), the circuit of the present invention bypasses the driver circuit (40) while injecting a significant current peak issued from the transistor (P3) towards the gate terminal (GateP) of the gate-controlled switching device (PO), whereas the capacitor (C) is discharging very slowly through the gate terminal (GateN).
    Type: Application
    Filed: July 17, 2006
    Publication date: September 2, 2010
    Applicant: NXP B.V.
    Inventor: Guillaume De Cremoux
  • Patent number: 7777573
    Abstract: An operational amplifier includes an amplifying circuit and a bais current generating circuit. The bias current generating circuit generates a bias current to the amplifying circuit. The amplifying circuit comprises a current adjusting unit and a current mirror. The current adjusting circuit has a storage element, receives a reference current and generating a passing current. The passing current is gradually adjusted utilizing the storage element according to a control signal. The current mirror receives the passing current to generate the bias current.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: August 17, 2010
    Assignee: Himax Technologies Limited
    Inventor: Ching-Chung Lee
  • Patent number: 7772926
    Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: August 10, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Eric Modica, Derek Bowers
  • Patent number: 7746120
    Abstract: A signal receiving device includes: a first conversion unit comprising a first input terminal to which a signal including a voltage signal and a reference voltage is inputted, and a first output terminal which output a first current signal voltage-current converted from the signal; a second conversion unit comprising a second input terminal to which the reference voltage is inputted, and a second output terminal which output a second current signal voltage-current converted from the reference voltage; a current mirror circuit comprising a third input terminal to which the second current signal is inputted, and a third output terminal which output a third current signal corresponding to the second current signal; and an output unit connected to both the first and third output terminals.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: June 29, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20100134188
    Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.
    Type: Application
    Filed: July 16, 2009
    Publication date: June 3, 2010
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak JO, Yoo Sam Na, Yoo Hwan Kim
  • Publication number: 20100127776
    Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 27, 2010
    Inventors: Yut Hoong CHOW, Hiang Teik TAN
  • Patent number: 7724092
    Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: May 25, 2010
    Assignee: QUALCOMM, Incorporated
    Inventors: Xiaohong Quan, Marzio Pedrali-Noy
  • Patent number: 7714659
    Abstract: Embodiments of the invention show a bias circuit for providing a biasing signal at a bias connection. The bias circuit includes a bias transistor and a feedback node, wherein the feedback node is coupled to a control terminal of the bias transistor via a first impedance element. The feedback node is furthermore coupled to the bias connection via a second impedance element. The control terminal of the bias transistor is coupled to the bias connection via a bypass-coupling path, which bypasses the first impedance element and the second impedance element, such that there is a feedback path via the bypass-coupling path and via the bias transistor from the bias connection to the feedback node.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: May 11, 2010
    Assignee: Infineon Technologies AG
    Inventor: Thomas Leitner
  • Publication number: 20100103043
    Abstract: This invention describes new and improved phased shifted injection oscillator, a phased shifted injection locked push-push oscillator and a phased array antennas (PAA). The PAAs in accordance with an exemplary embodiment of the present invention are low cost, and therefore can be used in various commercial applications, such as wireless communication or satellite mobile television.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 29, 2010
    Inventor: Alberto Milano
  • Publication number: 20100097141
    Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
    Type: Application
    Filed: October 21, 2008
    Publication date: April 22, 2010
    Inventor: Sandro HERRERA
  • Publication number: 20100045384
    Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.
    Type: Application
    Filed: September 10, 2009
    Publication date: February 25, 2010
    Inventors: Robert Michael Fisher, Michael L. Hageman, David S. Ripley
  • Patent number: 7663442
    Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Feng Chen
  • Patent number: 7649419
    Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: January 19, 2010
    Assignee: Qimonda AG
    Inventors: Josef Hoelzle, Reinhold Unterricker
  • Publication number: 20100007422
    Abstract: There is provided an amplifier circuit includes: an amplifying transistor; a first transistor having a DC current amplification factor generally equal to the DC current amplification factor of the amplifying transistor and constituting a current mirror circuit in conjunction with the amplifying transistor; and a current source circuit being operable to supply a current to the first transistor and including a second transistor having opposite conductivity type to the conductivity type of the first transistor. The second transistor is operated in a saturation region at a power supply voltage lower than an operating voltage range so that the DC current amplification factor of the amplifying transistor can be detected.
    Type: Application
    Filed: May 12, 2009
    Publication date: January 14, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takayuki Teraguchi
  • Publication number: 20100007424
    Abstract: According to some embodiments, an apparatus may comprise an amplifier, wherein the amplifier comprises: an output stage formed of a positive output terminal providing a positive output voltage and a negative output terminal providing a negative output voltage; a load tank coupled in parallel with the output stage and configured to filter signals received at the amplifier; and a negative resistance block coupled in parallel with the output stage and the load tank.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 14, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Anup Savla, Roger Brockenbrough
  • Patent number: 7642854
    Abstract: An amplifier circuit is disclosed having an output transistor for driving a complex load over a drive frequency range, wherein in the lower part of the range an inductive component of the load dominates and in the upper part the inductive component does not dominate. The amplifier circuit includes a current mirror circuit that is connected upstream of the output transistor and has a shunt path to a second potential, for the purpose of relatively reducing a DC current flowing through the output transistor in comparison with an AC current flowing through the latter.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: January 5, 2010
    Assignee: Infineon Technologies AG
    Inventors: Xianghua Shen, Markus Schimper
  • Patent number: 7639081
    Abstract: A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 29, 2009
    Assignee: Texas Instuments Incorporated
    Inventors: Abhijith Arakali, Sunil Rafeeque
  • Patent number: 7636014
    Abstract: The present invention relates to an trans-conductance amplifier, cooperating with a digital programmable current mirrors, can be applied to digital programmable current-mode integrated circuits, voltage control oscillators, adaptive frequency adjust mechanism, adaptive continuous analog filters via the corresponding trans-conductance adaptation controlled by the digital control signals. The present invention disclosed a digital programmable current mirror suitable for the second stage of the trans-conductance amplifier so as to reform the fixed gain trans-conductance amplifier to be digitally programmable.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: December 22, 2009
    Assignee: Holtek Semiconductor Inc.
    Inventor: Hung-Chang Chen