Abstract: A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.

Abstract: A circuit for amplifying a signal representing a variation in resistance of a variable resistance comprising at least one first load linked to an output terminal of a first transistor whose other terminal is associated with a variable resistance, in such a way as to allow the recovery of the amplified signal at the terminals of the first load.

Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.

Abstract: There is provided a power amplifying apparatus with dual-current control mode, including: a transistor mirror circuit adjusting currents respectively flowing through a main path and a mirror path connected in parallel to a power source terminal; a resistor mirror circuit adjusting the respective currents of the main path and the mirror path; a current controlling unit controlling a control current flowing through the main path with a pre-set constant current; a voltage adjusting unit providing a bias adjustment signal that corresponds to a difference voltage between a first voltage of a first node on the main path to which a current is output from the resistor mirror circuit and a second voltage of a second node on the mirror path to which a current is output from the resistor mirror circuit; and a bias circuit unit adjusting a bias of a power amplifying unit.

Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Abstract: A transimpedance amplifier includes a first MOS transistor, a current mirror circuit, a second MOS transistor, a load and a first feed back resistor. The first MOS transistor has a gate terminal to which a photodiode is connected. An output current of the first MOS transistor is input to the current mirror. The second MOS transistor has a gate terminal to which a voltage of an output terminal of the current mirror circuit is input. A source of the second MOS transistor is grounded. A polarity of the second MOS transistor is same as a polarity of the first MOS transistor. A first feedback resistor is connected between the gate terminal of the first MOS transistor and a drain terminal of the second MOS transistor. The second MOS transistor outputs a voltage corresponding to the voltage of the output terminal from the drain terminal.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.

Abstract: Systems and methods for implementing an up-conversion mixer with signal processing are disclosed.

Abstract: The present invention relates to an operational amplifier comprising an input-stage circuit, a floating current mirror circuit, and an output-stage circuit. The input-stage circuit receives an input signal and produces a control signal. The floating current mirror circuit is coupled to the input-stage circuit, and produces a mirror current according to the control signal. The output-stage circuit is coupled to the floating current mirror circuit, and produces a driving signal according to the mirror current. When the operational amplifier is operating in the static mode, the output-stage circuit further produces a static current according to the mirror current. Thereby, by using the floating current mirror circuit, the purpose of low power consumption can be achieved while driving to the high-voltage mode or to the low-voltage mode.

Abstract: A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.

Abstract: An amplifier including a high supply voltage source and a low supply voltage source and two parallel signal paths. Each signal path is connected to the high and the low supply voltage sources and includes a first amplifier and a second amplifier. The two signal paths are connected to each other only at a common input node and a common output node, so that the respective first amplifiers operate independently of each other. The first amplifiers are configured to convert at least a part of an input voltage signal into a signal current. The signal paths are configured so that the signal current in use drives the respective second amplifier to provide an amplified output current to the common output node.

Abstract: A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core.

Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.

Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.

Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.

Abstract: A power amplifier circuit can be linked to an antenna arrangement of a communication system for transmission of ASK RF data signals. The power amplifier circuit includes an amplifier core with several cascode amplifier cells in parallel. Each cascode amplifier cell is composed of three NMOS transistors in triode mounting between an output terminal connected to the antenna arrangement, and an earth terminal. A first transistor of each cascode amplifier cell is controlled by a carrier frequency signal, whereas a second transistor of each cascode amplifier cell is controlled by a smoothing control loop in order to modulate data to be transmitted on carrier frequency by amplitude shift keying. The smoothing control loop is provided for generating an increasing gate voltage for the second transistors on the basis of an increasing current ramp from a first minimum current value to a second maximum current value during a “0” to “1” data transition.

Abstract: An amplifier for an integrated circuit has a plurality of ratioed current mirrors connected to each other in a stacked configuration. Each ratio mirror has at least two resistors and at least two bipolar transistors connected to each other via said at least two resistors. Each amplifying transistor, contains a capacitor, and potentially and inductor, to internally match the transistors that make up the amplifying stack. DC, harmonic and s-parameter simulations are performed to provide an optimal impedance for each of the stacked transistors to maximize the RF power output of each stacked layer and the amplifier.

Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.

Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.

Abstract: Provided is an output circuit capable of allowing a more sufficient output current to flow. When a drain current of a PMOS transistor (12) is large, a PMOS transistor (13) operates in the non-saturation region. At this time, gate voltages of NMOS transistors (14 and 17) have risen to around a power supply terminal voltage. Therefore, a gate-source voltage of an NMOS transistor (17) increases, and a sufficient output current flows.

Abstract: An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: There is provided a bias circuit including a power amplifier in which influence of variation of a gate length L is reduced and variation of a gain among products is low. Two NPN- and PNP-type current mirror circuits 101 (NPN type) and 102 (PNP type) are inserted on an input side of a bias circuit 103. It is designed that a gate length of a transistor Q1 on an output side of the current mirror circuit 101 is longer than that of the other transistor. In this manner, even when an error is generated, influence of the error can be suppressed to be small.

Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.

Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.

Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the buffered signal to the amplifier as the feedback signal.

Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.

Abstract: The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.

Abstract: A current switching system is described. This system includes first and second mirrored devices coupled to each other and a coupled terminal, and the first and second mirrored devices are coupled to an input terminal and an output terminal; a storage element in element in parallel with the first mirrored device and the first degeneration device; a variable impedance device coupled between the coupled terminal and a low voltage device; and a current mirroring accuracy enhancing circuit coupled between the coupled terminal and a high voltage device, wherein the variable impedance device dynamically changes a current at the coupled terminal to a second level depending when a threshold is met, and an impedance on the coupled terminal remains low both before switching and during switching.

Abstract: A trans-impedance amplifier (TIA) for an optical receiver is disclosed, where the TIA stabilizes the cross point in the output thereof independent of the variation of the power supply. The TIA of the invention includes an amplifier section, a source follower, and a bias generator. A transistor in the source follower to define the current flowing in the source follower and another transistor in the bias generator constitute a current-mirror circuit. The operating point of the other transistor in the bias generator depends on the variation of the power supply. The output level of the amplifier section follows the variation of the power supply.

Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.

Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: A semiconductor circuit including an input terminal, an impedance converting portion configured to receive an input signal from the input terminal and to output an output signal corresponding to the input signal, an input impedance of the semiconductor circuit being higher than an output impedance of the semiconductor circuit, a detecting portion connected to a node between the input terminal and the impedance converting portion, and configured to detect whether the input signal is higher than a predetermined threshold, and a variable impedance connected to a reference voltage and the node, an impedance of the variable impedance configured to decrease after the input signal is detected as higher than the predetermined threshold.

Abstract: Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.

Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Abstract: Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror.

Abstract: A power amplifier circuit has a Gm amplifier, first and second transistors, third and fourth transistors consisting a mirror circuit, fifth and sixth transistors consisting a mirror circuit, seventh and eighth transistors consisting a mirror circuit, a ninth transistor of the first conductivity type which is connected at a first end thereof to the first power supply rail, connected at a second end thereof to a signal output terminal for outputting an amplified signal, and connected at a control terminal thereof to the inverting output terminal, and a tenth transistor of the second conductivity type connected at a first end thereof to the signal output terminal, connected at a second end thereof to the second power supply rail, and connected at a control terminal thereof to the noninverting output terminal.

Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.

Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.

Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit configured to receive an input signal. A bias circuit is configured to receive an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit is in communication with the bias circuit. The second Class AB amplifier circuit is configured to generate an output signal. A current mirror circuit is arranged between the first Class AB amplifier circuit and the bias circuit. A common-mode feedback circuit is configured to generate a feedback signal based on the output signal.

Abstract: A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amplification transistor which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit comprising a replicating transistor. The amplification transistor amplifies an RF signal and a bias current of the bias control circuit is supplied to the bias transistor. The transistors are fabricated by the same semiconductor manufacturing process, and have the same variation of gate length. The gate length monitor circuit generates a detection voltage depending on the gate length. According to the detection voltage, the bias control circuit controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor.

Abstract: Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor (102) that is used for the bias circuit, and all of or part of the other unit transistors are connected in parallel and used as amplifier (101).

Abstract: The present disclosure relates to a class AB amplifier output stage.

Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal.

Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: A radio-frequency amplifier includes a common gate amplification stage configured to be biased in a saturation condition with a first current and configured to receive an input signal as a gate-source voltage and to generate an output voltage as an amplified replica of the input signal. A feedback transistor is configured to be biased in a saturation condition with a second current and coupled to the common gate amplification stage so as to have a gate-drain voltage corresponding to a difference between the output voltage and the input signal.

Abstract: One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a first current path that includes a first degeneration resistance device and to generate an output current that flows through a second current path that includes a second degeneration resistance device. The output current can be substantially proportional to the input current. The system also includes a degeneration control circuit configured to maintain a substantially constant degeneration voltage across each of the first and second degeneration resistance devices.

Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.