Including Plural Amplifier Channels Patents (Class 330/295)
  • Patent number: 11159125
    Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 26, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Gerard Bouisse, Christian Cassou
  • Patent number: 11146220
    Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include a phase distortion compensation circuit that can compensate for input impedance variations that could otherwise lead to reduced efficiency and power performance. In one specific embodiment, the phase distortion compensation circuit is used to compensate for input impedance variations in the peaking amplifiers of a Doherty amplifier. In such embodiments, the phase distortion compensation circuit can absorb the non-linear input impedances of the peaking amplifiers in a way that may facilitate improved phase maintenance between the carrier and peaking stages of the Doherty amplifier.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventor: Hao Zhang
  • Patent number: 11139785
    Abstract: An LNA circuit includes: paths provided between an input and an output terminals, an LNA provided in at least one path, and a selector selecting one path. The LNA includes: a MOS transistor coupled between a first and a second power supplies, a first inductor coupled to a source of the MOS transistor, a capacitor formed between a gate and the source of the MOS transistor, a second inductor coupled between the gate of the MOS transistor and the input terminal, and a changeover switch coupled parallelly with at least one of the capacitor, and the first and the second inductors. The selector switches between a first state that one path is selected and the changeover switch is on, and a second state that another path is selected and the changeover switch is off. Alternatively, the one path and the another path are respectively provided without and with the LNA.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 5, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Norimasa Hiraoka
  • Patent number: 11128259
    Abstract: A power amplification apparatus, a remote radio unit, and a base station are provided to improve power amplification efficiency. The power amplification apparatus includes an envelope modulator, a main power amplifier, and a first auxiliary power amplifier. The envelope modulator is configured to obtain an envelope voltage based on a received envelope signal and output the envelope voltage to the drain of the main power amplifier. The main power amplifier is connected to the envelope modulator and configured to use the envelope voltage as an operating voltage, and is connected to the first auxiliary power amplifier, to output the envelope voltage to a drain of the first auxiliary power amplifier. The first auxiliary power amplifier is configured to use the envelope voltage received from the main power amplifier as an operating voltage.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 21, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shunzhong Zhang, Lipeng Zhang, Zhonghua Cai
  • Patent number: 11101227
    Abstract: Coupled line structures for wideband applications are provided herein. In certain embodiments, a coupled line structure includes one transmission line that is segmented in a metal layer and another that is substantially continuous in the metal layer, thereby allowing tighter spacing and higher coupling between the transmission lines relative to what is achievable if both transmission lines were continuous. The high coupling in turn aids in achieving wide bandwidth.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 24, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mir A. Faiz, Song Lin, Xudong Wang
  • Patent number: 11069276
    Abstract: A display apparatus includes a display panel, a gate driver, a data driver and a gamma reference voltage generator. The display panel is configured to display an image based on input image data. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The gamma reference voltage generator includes a plurality of gamma amplifiers having varied bias currents. The gamma reference voltage generator is configured to generate gamma reference voltages and to output the gamma reference voltages to the data driver.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunho Lim, Bongho Bae, Ok-Kwon Shin, Chongguk Lee, Myeong Bin Lim, Sehui Jang
  • Patent number: 11043983
    Abstract: A first transmitting circuit transmits a first transmission signal of a first frequency band for 2G. A second transmitting circuit transmits a second transmission signal of a second frequency band for 2G. The second frequency band is higher than the first frequency band. A bypass terminal is connected to an output end of the second transmitting circuit. A third transmitting circuit transmits a third transmission signal of a third frequency band for 4G or 5G. A frequency of a harmonic wave of the third transmission signal overlaps the second frequency band. A substrate includes a ground layer. The ground layer is disposed between part of the second transmitting circuit and part of the third transmitting circuit.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 22, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Naoya Matsumoto
  • Patent number: 11025207
    Abstract: Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: PSEMI CORPORATION
    Inventors: Kashish Pal, John Birkbeck
  • Patent number: 11018629
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, Inc.
    Inventors: Seungkee Min, Margaret A. Szymanowski
  • Patent number: 10985718
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 10978999
    Abstract: Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 10972054
    Abstract: Embodiments of systems and method for automatically biasing power amplifiers using a controllable current source are disclosed. In an embodiment, a bias controller for a power amplifier includes a first reference device source/drain interface, a first controllable current source configured to generate a first reference current in response to a first current control signal and to provide the first reference current to the first reference device source/drain interface, a first reference device gate interface, a first current-to-voltage controller configured to generate a first stabilized voltage in response to the first reference current and to provide the first stabilized voltage to the first reference device gate interface, and a first power amplifier (PA) interface configured to output a first control voltage in response to the first stabilized voltage.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 6, 2021
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma
  • Patent number: 10965254
    Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mattia Fausto Moretti, Paolo Pulici, Alessio Facen
  • Patent number: 10903357
    Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 26, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, George Pete Imthurn, Sivakumar Kumarasamy
  • Patent number: 10903182
    Abstract: Embodiments of a method and device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and a carrier amplifier die, a first peaking amplifier die, and a second peaking amplifier die on the mounting surface. The carrier amplifier die includes a first output bond pad that has a first length and a first width. The first peaking amplifier die includes a second output bond pad including a first main pad portion having a second length and a second width and including a first side pad portion having a third length and a third width. At least one of the second width or the third width is greater than the first width. The second peaking amplifier includes a third output bond pad. A first wirebond array is coupled between the third output bond pad and at least the first side pad portion.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 26, 2021
    Assignee: NXP USA, Inc.
    Inventors: Lu Wang, Elie A. Maalouf
  • Patent number: 10903806
    Abstract: An integrated circuit that includes a die with an active radio frequency (RF) unit embedded thereon; a first port for receiving an output signal from the active RF unit; a harmonic filter that comprises a first harmonic filter inductor; and a first RF inductive load that is electrically coupled to the first port and is magnetically coupled to the first harmonic filter inductor.
    Type: Grant
    Filed: September 18, 2016
    Date of Patent: January 26, 2021
    Assignee: DSP GROUP LTD.
    Inventors: Sergey Anderson, Ron Pongratz
  • Patent number: 10861806
    Abstract: An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 8, 2020
    Assignee: NXP USA, INC.
    Inventors: Yu-Ting David Wu, Enver Krvavac, Jeffrey Kevin Jones
  • Patent number: 10862433
    Abstract: A semiconductor device and an amplifier assembly implementing the semiconductor device are disclosed. The semiconductor device, which is a type of Doherty amplifier, includes first transistor elements for a carrier amplifier of the Doherty amplifier and second transistor elements for a peak amplifier. A feature of the Doherty amplifier is that the first transistor elements and the second transistor elements are disposed alternatively on a common semiconductor substrate.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 8, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masahiro Tanomura
  • Patent number: 10862434
    Abstract: A Doherty power amplifier includes input circuitry that provides input signals to asymmetric carrier and peaking amplifiers (e.g., a peaking-to-carrier size ratio, ? is greater than 1.15) with an absolute value of an input phase offset between 15 degrees and 165 degrees or between 195 degrees and 345 degrees. Carrier and peaking amplifier output signals are combined at a combining node. A complex combining load matching circuit, which is connected to the combining node, provides a complex impedance, ZL, with a non-zero reactive portion, xn. The output circuit between the peaking amplifier and the combining node has an electrical length of 0 or n*180 degrees (n=an integer value). The output circuit between the carrier amplifier and the combining node has an electrical length, ?x, where a difference between the electrical lengths of the peaking output circuit and the carrier output circuit is equal to the input phase offset.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventor: Roy McLaren
  • Patent number: 10848112
    Abstract: An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 24, 2020
    Assignee: Qatar Founation for Education, Science, and Community Development
    Inventors: Chadi Daher Geha, Jose Silva-Martinez, Cam V. Nguyen
  • Patent number: 10819247
    Abstract: This DC power supply device comprises: a transformer having a primary magnetic core, a secondary magnetic core, at least one primary coil wound on the primary magnetic core, and a plurality of secondary coils wound on the secondary magnetic core; and at least one bridge composed of transistors. The DC power supply device has: a primary circuit connected to the primary coil; and a plurality of secondary circuits respectively connected to the plurality of secondary coils and each having a first secondary resonance capacitor, a second secondary resonance capacitor, and a smoothing circuit. The primary circuit and the plurality of secondary circuits are electrically insulated from each other by the transformer. In the plurality of secondary circuits, output parts of respective smoothing circuits are serially connected to each other. The primary magnetic core and the secondary magnetic core are disposed to face each other with an insulator disposed therebetween.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: October 27, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Mamoru Tsuruya
  • Patent number: 10804585
    Abstract: Aspects of the subject disclosure may include, for example, a system that performs operations including receiving first electromagnetic waves on an outer surface of a transmission medium, detecting a degradation of a signal quality of the first electromagnetic waves due to first electric fields of the first electromagnetic waves inducing first currents in an obstruction disposed on the outer surface of the transmission medium, and generating second electromagnetic waves having second electric fields that induce second currents in the obstruction that are lower in magnitude than the first currents, the electromagnetic waves having a cutoff frequency. Other embodiments are disclosed.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 13, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Paul Shala Henry, Robert Bennett, Farhad Barzegar, Irwin Gerszberg, Donald J. Barnickel, Thomas M. Willis, III
  • Patent number: 10804867
    Abstract: Quadrature amplifier having envelope control. In some embodiments, an amplifier system can include a quadrature amplifier having first and second amplifiers configured to amplify first and second signals in quadrature relative to each other, with each of the first and second amplifiers including a cascode stage with input and output transistors arranged in a cascode configuration. The amplifier system can further include an envelope tracking bias circuit coupled to the quadrature amplifier and configured to provide a bias signal to the output transistor of the cascode stage of at least one of the first and second amplifiers.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 13, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip John Lehtola, Serge Francois Drogi
  • Patent number: 10797653
    Abstract: A consecutive Doherty amplifier is disclosed. The Doherty amplifier includes a carrier amplifier, a power splitter, a peak amplifier, and a phase compensator. The carrier amplifier receives a radio frequency signal with interposing any signal splitters. The power splitter splits an output of the carrier amplifier into first and second split signals. The phase compensator transfers the second split signal to the peak amplifier. The first split signal is combined with the output of the peak amplifier.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Andrey Grebennikov, James Wong, Naoki Watanabe
  • Patent number: 10790783
    Abstract: Amplifiers for radio-frequency applications. In some embodiments, a power amplifier die can include a semiconductor substrate and a plurality of narrow band power amplifiers implemented on the semiconductor substrate. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: September 29, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 10778151
    Abstract: Embodiments of the disclosure relate to a multi-mode power management system supporting fifth-generation new radio (5G-NR). The multi-mode power management system includes first tracker circuitry and second tracker circuitry each capable of supplying an envelope tracking (ET) modulated or an average power tracking (APT) modulated voltage. In examples discussed herein, the first tracker circuitry and the second tracker circuitry have been configured to support third-generation (3G) and fourth-generation (4G) power amplifier circuits in various 3G/4G operation modes. The multi-mode power management system is adapted to further support a 5G-NR power amplifier circuit(s) in various 5G-NR operation modes based on the existing first tracker circuitry and/or the existing second tracker circuitry.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10778152
    Abstract: Systems and methods related to linear load modulated power amplifiers. A power amplifier (PA) system can include a divider that splits a signal into two portions, a first portion directed to an attenuator that attenuates the first portion so that the first portion and the second portion have different powers and a second portion directed to a phase shift component that shifts a phase of the second portion so that the first portion and the second portion have different phases. The PA system can also include a Doherty amplifier circuit where a carrier amplifier amplifies the attenuated first portion and a peaking amplifier amplifies the phase-shifted second portion. The carrier amplifier includes a Class AB driver stage and a Class B output. The peaking amplifier includes a Class B driver stage a Class B output stage.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 15, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Aleksey A. Lyalin, Russ Alan Reisner, Ramon Antonio Beltran Lizarraga
  • Patent number: 10734966
    Abstract: According to an aspect of present disclosure, a phase shifter for providing a desired phase shift to a very high frequency signal fabricated as part of the an integrated circuit comprises a first coil segment and a second coil segment together forming an inductor of first inductance value, a first capacitor of first capacitance value electrically connected parallel the inductor, a second capacitor of second capacitance value electrically connected between the first coil segment and the second coil segment and a resistor of a first resistance value electrically connected parallel to the second capacitor, in that, the inductor, first capacitor, second capacitor and the resistor together operative as a phase shifter such that when a input signal of a first frequency is presented across the first capacitor, the output signal across the resistor is phase shifted version of the input signal shifted in phase by a first angle.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 4, 2020
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Rakesh Kumar
  • Patent number: 10686417
    Abstract: A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: June 16, 2020
    Assignee: CAMBRIDGE CONSULTANTS LIMITED
    Inventors: Bryan James Donoghue, Desmond Phillips, Tan Robert, Peter-Contesse Herve
  • Patent number: 10686423
    Abstract: A phase-shifting circuit 1 includes a signal conductor 2 that transmits signals, and a dielectric body 3 that is disposed to overlap the signal conductor 2, said phase-shifting circuit changing the phase of the signals by changing the area of an overlapping section 5 where the signal conductor 2 and the dielectric body 3 overlap each other. The phase-shifting circuit further includes a transformer unit 7 for matching impedance between the overlapping section 5 and non-overlapping section 6 where the signal conductor 2 and the dielectric body 3 do not overlap each other, said transformer unit being provided at end sections of the dielectric body 3, said end sections being on the input side and output side of the signals.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 16, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Satoshi Yoshihara, Seiji Kado, Nobuaki Kitano
  • Patent number: 10680560
    Abstract: A communication unit includes a plurality of parallel radio frequency, RF, signal paths. Located between a first RF signal path of the plurality of parallel RF signal paths comprising at least one first RF amplifier and a second signal path comprising at least one second RF amplifier is one of a shared inductor or shared transformer. The at least one first RF amplifier is coupled to a supply voltage via a first switch and at least one second RF amplifier is coupled to the supply voltage via a second switch, and the first switch is closed that provides the supply voltage to the at least one second RF amplifier whilst the second switch is opened.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: June 9, 2020
    Assignee: MediaTek, Inc.
    Inventors: Chih-Hao Sun, Po-Yun Hsiao, Chin-Yen Chao, Yi-Bin Lee
  • Patent number: 10673387
    Abstract: An amplifier package may include a transistor, an output impedance matching circuit and one or more radial stub harmonic traps coupled to a control terminal of the transistor or to an output terminal of the transistor. The output impedance matching circuit and the radial stub harmonic traps may be formed on a single substrate or separate substrates, which may be formed from gallium nitride. Each radial stub harmonic trap may provide a low resistance path to ground for signal energy above a fundamental operating frequency of the amplifier, such as harmonic frequencies thereof.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 2, 2020
    Assignee: NXP USA, Inc.
    Inventors: Ramanujam Srindhi Embar, Roy McLaren
  • Patent number: 10658983
    Abstract: An amplifier has an N number of input networks connected to an input terminal to receive an input signal, a first amplifier to amplify one output signal from the N number of input networks, a (N?1) number of secondary amplifiers to amplify the remaining (N?1) number of output signals, except for the one output signal, from the N number of input networks, where the amplification order of the (N?1) number of secondary amplifiers is determined based on the power level of each output signal from the N number of input networks when the first amplifier is operational, an N number of output networks which are arranged, and a first bias network to supply a D.C. bias voltage to at least one of the N number of output networks. An electrical length of the first bias network is less than 90 degrees.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 19, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Thomas Martin Hone, Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 10630242
    Abstract: A Doherty amplifier has a first amplifier path that includes a first amplifier, a second amplifier path that includes a second amplifier, a power divider, and a short-circuited stub. The power divider receives an RF signal and divides the RF signal into first and second input signals. The power divider includes first and second power divider outputs that produce the first and second input signals, respectively. The short-circuited stub is coupled between the first power divider output and the first amplifier or between the second power divider output and the second amplifier. The first and second amplifier paths are characterized by first and second frequency-dependent insertion phases, respectively. A slope of the first or second frequency-dependent insertion phase is altered by the short-circuited stub. The power divider produces the first and second input signals with a quadrature phase shift.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Roy McLaren
  • Patent number: 10630241
    Abstract: An embodiment of an amplifier includes a first amplifier with a first output terminal, a second amplifier with a second output terminal, and a plurality of microstrip transmission lines electrically connected to the amplifiers. The transmission lines include an impedance inverter line electrically connected between the first and second output terminals, and an output line electrically connected between the second output terminal and an output of the amplifier, where the output line forms a portion of an output impedance transformer. The amplifier also includes a directional coupler formed from a main line and a coupled line positioned in proximity to the main line, where the main line is formed from a portion of one of the transmission lines. The amplifier may also include a module substrate with a plurality of metal layers, where the main line and the coupled line are formed from different portions of the metal layers.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Abdulrhman M. S. Ahmed, Ebrahim M. Al Seragi
  • Patent number: 10629552
    Abstract: An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yu-Ting David Wu, Enver Krvavac, Jeffrey Kevin Jones
  • Patent number: 10608594
    Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Komatsuzaki, Shintaro Shinjo, Keigo Nakatani, Shohei Imai
  • Patent number: 10566183
    Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Ide
  • Patent number: 10547279
    Abstract: An amplifier for amplifying radio frequency signals comprising: a signal splitter configured to split an input radio frequency signal into two or more signals; and two or more switching power amplifiers. Each of the switching power amplifiers is configured to amplify a respective signal of the two or more signals using an active device and output a respective amplified signal at a respective output terminal of the switching power amplifier when the switching power amplifier is activated. Each of the two or more switching power amplifiers has a different maximum output power. The amplifier further comprises: an output node connected to each of the output terminals of the switching power amplifiers to combine the amplified signals and output a combined amplified signal; and control circuitry configured to issue control signal to control bias voltages provided to a gate of each of the active devices of the switching power amplifier to selectively activate and deactivate the active devices.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gavin Watkins
  • Patent number: 10530415
    Abstract: The invention relates to an HF circuit, for example for use in front-end circuits, having improved signal quality in carrier aggregation. According to the invention, a signal path between a duplexer and a diplexer comprises a phase shifter.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 7, 2020
    Assignee: SnapTrack, Inc.
    Inventors: Juha Ellä, Edgar Schmidhammer, Gabriele Kolb, Ratko Jovovic
  • Patent number: 10498292
    Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, INC.
    Inventors: Enver Krvavac, Joseph Gerard Schultz, Yu-Ting David Wu, Nick Yang
  • Patent number: 10491176
    Abstract: An amplifier circuit includes a first adjustable amplification path and a second adjustable amplification path; wherein the first adjustable amplification path and the second adjustable amplification path are configurable in different operating modes selected from a linear operating mode, an efficient operating mode, and an intermediate operating mode to amplify a transmission signal based at least in part on a characteristic of the transmission signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joonhoi Hur, Paul Draxler
  • Patent number: 10483928
    Abstract: A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasushi Oyama, Takayuki Tsutsui, Kazuhito Nakai
  • Patent number: 10476439
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Patent number: 10476442
    Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Margaret A. Szymanowski, Sarmad K. Musa, Fernando A. Santos, Mahesh K. Shah
  • Patent number: 10411654
    Abstract: An amplifier has an N number of input networks connected to an input terminal to receive an input signal, a first amplifier to amplify one output signal from the N number of input networks, a (N?1) number of secondary amplifiers to amplify the remaining (N?1) number of output signals, except for the one output signal, from the N number of input networks, where the amplification order of the (N?1) number of secondary amplifiers is determined based on the power level of each output signal from the N number of input networks when the first amplifier is operational, an N number of output networks which are arranged, and a first bias network to supply a D.C. bias voltage to at least one of the N number of output networks. An electrical length of the first bias network is less than 90 degrees.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Thomas Martin Hone, Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 10411665
    Abstract: A resonant cavity combined solid-state amplifier system including a resonant cavity having at least one output port coupled to a high-power transmission line. A plurality of high-power transistors are each configured to generate a variable amount of power input directly into the resonant cavity. The plurality of high-power transistors may be configured such that a failure of one or more of the plurality of high-power transistors does not substantially impede operation of the resonant cavity. A plurality of output impedance matching networks each coupled to one of the plurality of high-power transistors and extending into the resonant cavity are configured to match an impedance of each transistor to an impedance of the resonant cavity and configured to electromagnetically couple power from each of the plurality of high-power transistors into the resonant cavity to provide a combined high-power output to the high-power transmission line.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 10, 2019
    Assignee: Diversified Technologies, Inc.
    Inventors: Erik G. Johnson, Marcel P. J. Gaudreau, John Kinross-Wright, Frederick Marvin Niell, III, David B. Cope
  • Patent number: 10389315
    Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chulkyu Lee, Shih-Wei Chou, Ying Duan
  • Patent number: 10355645
    Abstract: A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyeon Seok Hwang, Jong Soo Lee, Seung Chul Pyo
  • Patent number: 10340858
    Abstract: A distributed amplifier (DA) is disclosed. The DA includes a first plurality of inductive elements coupled in series forming a first plurality of connection nodes. The DA also includes a second plurality of inductive elements coupled in series forming a second plurality of connection nodes. The DA further includes a plurality of amplifier cells that each has a main transistor and a cascode transistor coupled into a cascode configuration. The cascode transistor has a current input coupled to a corresponding one of the first plurality of connection nodes. An input transistor has a control terminal coupled to a corresponding one of the second plurality of connection nodes, a current input terminal configured to provide a bias tuning for the DA, and a third current output terminal coupled to a control terminal of the main transistor and configured to provide a separate bias tuning for the DA.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 2, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kevin Wesley Kobayashi