Abstract: Techniques for implementing an internal optical communication link in a power amplifier system are disclosed. In one embodiment, the techniques may be realized as a power amplifier system that includes a panel, an optical link, and a controller. The panel includes a plurality of signal endpoints and a first optical interface, the first optical interface being coupled to each of the plurality of signal endpoints. The optical link is coupled to the first optical interface. The controller is configured to manage operation of the power amplifier system and is coupled to the optical link via a second optical interface. The controller communicates with each of the plurality of signal endpoints over the optical link.

Abstract: The present subject matter relates to active balun circuits. An active balun circuit includes a plurality of transistors; an output transmission line connected to output terminals of the transistors; an input transmission line; and a plurality of serial capacitors coupled to an input terminal of the transistors and the input transmission line.

Abstract: A power amplifier impedance adjustment circuit is disclosed. In one aspect, the impedance adjustment circuit includes an input node configured to receive a radio frequency (RF) signal from a power amplifier, an output node configured to provide the RF signal to an antenna switch die, a plurality of electrical components arranged between the input node and the output node, and at least one switch configured to selectively electrically connect at least one of the electrical components to the input node and the output node. For each state of the at least one switch, the impedance adjustment circuit is configured to adjust an impedance of the power amplifier from a natural tune point in a direction towards a target tuned impedance point when viewed on a Smith chart.

Abstract: Methods and apparatus for implementing a power amplifier circuit assembly an uneven power splitter which feeds two power amplifiers of different amplifier classes are described. By supplying different amounts of power to different amplifier circuits having different performance curves, an overall combined amplifier performance having a relatively uniform, e.g., flat, performance curve over a wide range of frequencies is achieved. In at least some embodiments one of the amplifiers is a class B power amplifier and the other amplifier is a class C power amplifier. In some but not necessarily all embodiments a phase shift is introduced on a signal path to one of the power amplifiers to compensate for a difference in phase shifts introduced by the power amplifiers which are used in parallel.

Abstract: A device includes an amplifier having an input terminal and an output terminal. The input terminal is configured to receive a radio frequency (RF) input signal. The device includes an output network coupled to the output terminal of the power amplifier and a first passively tunable integrated circuit (PTIC) coupled to the output network. The first PTIC includes a direct-current (DC) bias voltage input terminal configured to receive a fixed bias voltage, a control signal input terminal configured to receive a time-varying control signal, wherein the fixed bias voltage in combination with the time-varying control signal sets an operating reference point of the first PTIC, and an input terminal electrically connected to the output terminal of the amplifier, wherein a change in an output voltage signal generated by the power amplifier causes the first PTIC to modify a first effective impedance of a load presented to the power amplifier via the output network.

Abstract: A radio-frequency generator, including a power amplifier module including a power amplifier, a pickup module connected to an output of the power amplifier to generate a pickup signal, and an output configured to be connected to the respective output of the amplifier and configured to output a radio-frequency output signal. The radio-frequency generator includes a measurement module configured to receive the pickup signal and to generate a measurement signal based on the one pickup signal; and a radio-frequency signal generation module configured to generate two or more carrier signals of different frequency, and to provide a drive signal as input to the power amplifier module, and a regulation module configured to receive the measurement signal, and to regulate the power of the radio-frequency output signal based on the measurement signal.

Abstract: A second member is joined in surface contact with a first surface of a first member including a semiconductor region made from an elemental semiconductor. The second member includes a radio-frequency amplifier circuit made from a compound semiconductor. A conductive protrusion projects from the second member toward a side opposite to the first member. The first member includes a temperature measurement element that detects a temperature.

Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.

Abstract: The present disclosure provides a reconfigurable power amplifier (PA) based on a PIN switch and a design method thereof. The reconfigurable PA based on a PIN switch includes an input port, an input matching circuit, the PIN switch, a gate bias circuit, a transistor, a drain bias circuit, an output matching circuit and an output port, where the input matching network includes an input end connected to a power input end, and an output end connected to a gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain bias circuit is connected in parallel with a drain, the drain of the transistor is connected to an input end of the output matching circuit, and an output end of the output matching circuit serves as a power output.

Abstract: Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.

Abstract: An RF amplifier includes an amplifier input, a transistor die with a transistor and a transistor input terminal, a fundamental frequency impedance matching circuit coupled between the amplifier input and the transistor input terminal, and a harmonic frequency termination circuit coupled between the transistor input terminal and a ground reference node. The harmonic frequency termination circuit includes a first inductance coupled between the transistor input terminal and a first node, and a tank circuit coupled between the first node and the ground reference node. The tank circuit includes a first capacitance coupled between the first node and the ground reference node, and a second inductance coupled between the first node and the ground reference node. The tank circuit is configured to shunt signal energy at or near a second harmonic frequency, while appearing as an open circuit to signal energy at a fundamental frequency of operation of the RF amplifier.

Abstract: A power amplifier module includes a substrate, an amplifier circuit including a plurality of transistors to be mounted on the substrate and a bump connected to the plurality of transistors, a harmonic termination circuit and an output matching circuit that are disposed in or on the substrate and configured to be electrically connected to the amplifier circuit, a connection pad disposed on the substrate and configured to be connected to the bump, and a plurality of connection wiring lines branching from the connection pad. The plurality of connection wiring lines include at least a first connection wiring line that connects the connection pad and the harmonic termination circuit to each other, a second connection wiring line that connects the connection pad and the output matching circuit to each other, and a third connection wiring line that connects the connection pad and an external power supply to each other.

Abstract: A Doherty amplifier includes a peaking amplifier, a carrier amplifier, and a combining node electrically connected to the carrier amplifier and the peaking amplifier. The Doherty amplifier includes a harmonic control circuit coupled to the combining node. The harmonic control circuit includes an inductor and a capacitor and the inductor and capacitor are connected in series between the first current conducting terminal and a ground reference node. An inductance value of the inductor of the harmonic control circuit and a capacitance value of the capacitor of the harmonic control circuit are selected to terminate second order harmonic components of a fundamental frequency of a signal generated by the carrier amplifier.

Abstract: Examples disclosed herein relate to a Doherty Power Amplifier (“DPA”) with integrated second harmonic injection. The DPA includes an amplifier circuit having a carrier amplifier and a peaking amplifier, and a combiner network coupled to the amplifier circuit, the combiner network having a plurality of transmission lines and a LC resonant circuit to inject a second harmonic from the carrier amplifier into the peaking amplifier.

Abstract: A barely Doherty dual envelope tracking (BD2E) circuit has a transmitter chain that includes an envelope tracking (ET) circuit that controls a Doherty dual power amplifier array. The ET circuit provides two control signals (supply voltage signals) that are used to control or modulate a carrier amplifier and a peaking amplifier independently of one another. The BD2E circuit includes an improved impedance inverter that isolates the peaking amplifier from the carrier amplifier to allow this independent control. By providing independent control, greater linearity may be provided while preserving the efficiency of the circuit.

Abstract: A power amplifier device includes a semiconductor substrate; a plurality of first transistors that are provided on the semiconductor substrate and receive input of a radio-frequency signal; a plurality of second transistors that are provided on the semiconductor substrate and electrically connected to the respective plurality of first transistors, and output a radio-frequency output signal obtained by amplifying the radio-frequency signal; a plurality of first bumps provided so as to overlay the respective plurality of first transistors; and a second bump provided away from the plurality of first bumps and provided so as not to overlay the plurality of first transistors and the plurality of second transistors. When viewed in plan from a direction perpendicular to a surface of the semiconductor substrate, a first transistor and a first bump, a second transistor, the second bump, a second transistor, and a first transistor and a first bump are arranged in sequence.

Abstract: A dual amplifier apparatus is disclosed. The apparatus includes an energy module having a controller and a first and second power amplifier circuit coupled to the controller. The first and second power amplifier circuits are configured to receive and amplify an input signal to generate a first output signal into a load coupled to the output of the first and second power amplifier circuit. A power rating of the first amplifier circuit is different from a power rating of the second amplifier circuit. The controller is configured to select the first or the second power amplifier circuit.

Abstract: Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.

Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.

Abstract: Low-load-modulation, broadband power amplifiers and method of use are described. The amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the fully-on and fully backed-off states of the amplifier. With lower load modulation, the power amplifiers described herein exhibit better power-handling capability and RF fractional bandwidth as compared to conventional amplifiers.

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Abstract: The present invention relates to a high-frequency semiconductor device. A conventional high-frequency semiconductor device including an input second-order harmonic matching circuit has such a problem that gain decrease occurs. In a high-frequency semiconductor device (100) of the present invention, two adjacent unit transistor cells (7) and (8) are connected to one input second-order harmonic matching circuit (19) provided on an upper surface of a semiconductor substrate (1). The input second-order harmonic matching circuit (19) includes a first capacitor (13), a first inductor (14), a second capacitor (15), and a second inductor (16). The first capacitor (13) and the first inductor (14) resonate at the frequency of a fundamental wave, and each of impedances as seen by input electrodes of the two unit transistor cells (7) and (8) is short-circuited at the frequency of a second-order harmonic.

Abstract: A Doherty amplifier includes a divider configured to divide input power into first input power and second input power, and a carrier amplifier configured to amplify the first input power. The Doherty amplifier includes an adaptive attenuator configured to attenuate the second input power, the adaptive attenuator being configured to increase an attenuation amount upon detecting that the second input power is less than a predetermined value. The Doherty amplifier includes a peaking amplifier configured to amplify the attenuated second input power, and a combiner configured to combine output power of the carrier amplifier with output power of the peaking amplifier.

Abstract: A semiconductor device and an amplifier assembly implementing the semiconductor device are disclosed. The semiconductor device, which is a type of Doherty amplifier, includes first transistor elements for a carrier amplifier of the Doherty amplifier and second transistor elements for a peak amplifier. A feature of the Doherty amplifier is that the first transistor elements and the second transistor elements are disposed alternatively on a common semiconductor substrate.

Abstract: Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An output impedance-matching element can be relied upon. In one example, the output impedance-matching element can include an output strip line, a shunt capacitor connected between the output strip line and ground, an output capacitor connected between the output strip line and an output bonding pad, and an inductive strip line connected between the output bonding pad and ground.

Abstract: Apparatus and methods for a low-load-modulation power amplifier are described. Low-load-modulation power amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the power amplifier's fully-on and fully backed-off states. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained.

Abstract: A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.

Abstract: A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance is adjusted to match one of an impedance of the differential antenna, an impedance of the first PA, and an impedance of the second PA, based on the ripples detected by the ripple detector.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

Abstract: A high-efficiency amplifier is configured so that short stubs are provided in a line between a first substrate end and a second substrate end of a substrate, and among the short stubs, short stubs provided at locations other than both ends of the line include two short stubs and which are adjacent to each other, and which are provided at locations at which the two short stubs are to be electromagnetically coupled to each other.

Abstract: An amplifier device includes a substrate, a composite packaged amplifier having a bottom plate and an output plate, a first amplifier and a second amplifier provided on the bottom plate, a combining node that combines an output of the first amplifier with an output of the second amplifier, an output matching circuits provided on the bottom plate, that has a first transmission line provided between the first amplifier and the combining node, and a second transmission line provided between the combining node and the second amplifier, a third transmission line having one transmission line on which the output plate is mounted and other transmission line that connects the one transmission line to the external port, and wirings connecting to one terminal of the output plate and the combining node. A length of the output plate and the other transmission line is equal or less than ?/4 radian for a signal.

Abstract: An amplifier includes an input matching network; at least one transistor; an input lead coupled to the at least one transistor; a ground terminal coupled to the transistor; an output lead coupled to the at least one transistor; an output matching circuit coupled to the output lead and to the at least one transistor; and a baseband impedance enhancement circuit having at least one reactive element coupled to the input matching network. The baseband impedance enhancement circuit is configured to reduce resonances of a baseband termination.

Abstract: The present disclosure relates to added isolation between transistors in a multiple path amplifier circuit. The multiple path amplifier circuit includes a substrate, a first transistor on the substrate in a first path, and a second transistor on the substrate in a second path. The multiple path amplifier circuit also includes at least one electrical connection associated with the first and the second transistors and positioned to at least partially extend between the first path and the second path.

Abstract: Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

Abstract: An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground.

Abstract: Exemplary aspects are directed to a power-amplification circuit including multiple in-parallel circuit paths, each including a power amplifier driving an immittance converter. Current from each output of the respective immittance converters is combined for delivery to a load. In a more specific example, a control circuit may be used to modulate, such as by enabling or disabling power delivered from, one or more of the power amplifiers for fast, coarse resetting of the overall power delivered to the load, and/or to modulate one or more of the modulate immittance converters (e.g., via a phase or signal-timing adjustment) to finely tune the resetting of the overall power delivered to the load. Using the control circuit for providing both the coarse adjustment and the fine adjustment, and fast acting precise delivery of overall power delivered to a load may be realized for any of a variety of applications.

Abstract: A radio frequency amplifier circuit is provided. A matching circuit is configured on a radio frequency path of an input end or an output end of an amplifier. An inductance-capacitance resonance circuit and the matching circuit share an inductor included in the matching circuit to generate a corresponding resonance frequency. The matching circuit provides an input impedance or an output impedance matching two fundamental tones in a radio frequency signal at a first frequency and a second frequency. The inductance-capacitance resonance circuit provides a filtering path for filtering a signal component outside a frequency band formed by the first frequency and the second frequency in the radio frequency signal.

Abstract: In each E-class inverter, an internal voltage detection circuit detects an internal voltage of a resonant type power supply circuit or a matching circuit and adjusts a phase of a driving signal of a MOSFET based on a detected voltage. It is thus possible to match a phase of a current voltage of a sine waveform of each inverter and combine power highly efficiently. Since power combining is performed highly efficiently without using a variable capacitor and variable inductor, it is possible to suppress upsizing of elements and achieve downsizing of a power amplifier circuit.

Abstract: Spatial power-combining devices with reduced dimensions are disclosed. Spatial power-combining devices are provided that employ a hybrid structure including both a planar splitter/combiner and an antipodal antenna array. Planar splitters may be arranged to divide an input signal while antipodal antenna arrays may be arranged to combine amplified signals. In other applications, the order may be reversed such that antipodal antenna arrays are arranged to divide an input signal while a planar combiner is arranged to combine amplified signals. Advantages of such spatial power-combining devices include reduced size and weight while maintaining suitable performance for operation in desired frequency bands.

Abstract: A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure is to amplify transmission signals in a wireless communication system, and a transmitting device may include an antenna array including a plurality of antenna elements, a plurality of amplification chains for amplifying signals transmitted through the plurality of the antenna elements, and a power supply line for supplying powers to the plurality of the amplification chains. Herein, the powers used by power amplifiers included in at least one amplification chain of the plurality of the amplification chains may be divided by filtering or by independent pads and branch-lines.

Abstract: A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) has the capability of maintaining high linearity and high efficiency against load mismatch. The reconfigurable PA includes a switch to alternatively connect to a pre-determined resistive load or a pre-determined pure reactive load (jX), i.e., short, open, or finite reactance between an output quadrature coupler and ground. The biasing of Doherty mode is adaptive dependent on the value of reactive loading (jX). The Doherty operation of this PA is based on an architecture configured from a balanced amplifier, e.g., a quasi-balanced amplifier.

Abstract: A Doherty amplifier includes: a transistor for a carrier amplifier; a transistor for a peak amplifier; a transmission line connected between an output terminal of the transistor for the carrier amplifier and an output terminal of the transistor for the peak amplifier; a stub that is connected in parallel to the output terminal of the transistor for the peak amplifier and that is capacitive and inductive in a working frequency band; and an output matching circuit connected to the output terminal of the transistor for the peak amplifier, the transmission line, and an output load, the output matching circuit to transform an impedance of the output load into an impedance lower than the impedance of the output load.

Abstract: A power amplifier circuit includes a first path and a second path between an input terminal and an output terminal, a first amplifier located in the first path operative in a first mode, a second amplifier located in the second path operative in a second mode, a first matching circuit between the first amplifier and the output terminal in the first path, a first capacitor having a first end connected to the output terminal side of the first matching circuit, and a second end, a first inductor having a first end connected to the second end of the first capacitor and a second end grounded, and a short-circuit switch connected in parallel with the first inductor. The short-circuit switch short-circuits the first and second ends of the first inductor in the first mode and is placed in an open-circuit position in the second mode.

Abstract: A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.

Abstract: A method and transmitter for a Doherty power amplifier are provided. According to one aspect, a radio transmitter includes, for each carrier frequency, a filter, a main path and a peak path. The filter suppresses signals outside the selected frequency band to produce a filter output. The main path is configured to make a first adjustment of a magnitude and phase of the filter output to produce a main path signal. The peak path is configured to make a second adjustment of the magnitude and phase of the filter output to produce a peak path signal, a difference between the first adjustment and the second adjustment being dependent on the carrier frequency. Main path signals for each carrier frequency produce a composite main path signal. Peak path signals for each carrier frequency produce a composite peak path signal.

Abstract: A method for making a wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, the amplifier including: a signal source adapted to generate an input signal; a hybrid coupler or a splitter network adapted to receive the input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input the first output signal; a peak amplifier adapted to receive as input the second output signal; an output network arranged between the carrier and peak amplifiers and a delivery node adapted to be connected to a load, the output network including a recombination node adapted to receive the signals output by the carrier amplifier and the peak amplifier, and a transmission line implemented as a printed circuit track applied to an insulating substrate, wherein capacitors are inserted on the track wh