Including Plural Amplifier Channels Patents (Class 330/295)
  • Patent number: 11736067
    Abstract: A semiconductor device and an amplifier assembly implementing the semiconductor device are disclosed. The semiconductor device, which is a type of Doherty amplifier, includes first transistor elements for a carrier amplifier of the Doherty amplifier and second transistor elements for a peak amplifier. A feature of the Doherty amplifier is that the first transistor elements and the second transistor elements are disposed alternatively on a common semiconductor substrate.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masahiro Tanomura
  • Patent number: 11722101
    Abstract: Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An output impedance-matching element can be relied upon. In one example, the output impedance-matching element can include an output strip line, a shunt capacitor connected between the output strip line and ground, an output capacitor connected between the output strip line and an output bonding pad, and an inductive strip line connected between the output bonding pad and ground.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: August 8, 2023
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Gerard Bouisse, Andrew Alexander, Andrew Patterson
  • Patent number: 11705869
    Abstract: Apparatus and methods for a low-load-modulation power amplifier are described. Low-load-modulation power amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the power amplifier's fully-on and fully backed-off states. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 18, 2023
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Bi Ngoc Pham, Gerard Bouisse
  • Patent number: 11689245
    Abstract: A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: June 27, 2023
    Assignee: Stichting IMEC Nederland
    Inventors: Erwin Allebes, Johan van den Heuvel, Gaurav Singh
  • Patent number: 11677355
    Abstract: A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance is adjusted to match one of an impedance of the differential antenna, an impedance of the first PA, and an impedance of the second PA, based on the ripples detected by the ripple detector.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: June 13, 2023
    Assignee: Movandi Corporation
    Inventors: Ahmadreza Rofougaran, Maryam Rofougaran, Sam Gharavi
  • Patent number: 11671058
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: June 6, 2023
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal
  • Patent number: 11658621
    Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 23, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Ralph D. Moore, Jesse Bankman
  • Patent number: 11621674
    Abstract: A high-efficiency amplifier is configured so that short stubs are provided in a line between a first substrate end and a second substrate end of a substrate, and among the short stubs, short stubs provided at locations other than both ends of the line include two short stubs and which are adjacent to each other, and which are provided at locations at which the two short stubs are to be electromagnetically coupled to each other.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: April 4, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eigo Kuwata, Makoto Kimura, Jun Kamioka
  • Patent number: 11569788
    Abstract: An amplifier device includes a substrate, a composite packaged amplifier having a bottom plate and an output plate, a first amplifier and a second amplifier provided on the bottom plate, a combining node that combines an output of the first amplifier with an output of the second amplifier, an output matching circuits provided on the bottom plate, that has a first transmission line provided between the first amplifier and the combining node, and a second transmission line provided between the combining node and the second amplifier, a third transmission line having one transmission line on which the output plate is mounted and other transmission line that connects the one transmission line to the external port, and wirings connecting to one terminal of the output plate and the combining node. A length of the output plate and the other transmission line is equal or less than ?/4 radian for a signal.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 31, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: James Wong
  • Patent number: 11552597
    Abstract: An amplifier includes an input matching network; at least one transistor; an input lead coupled to the at least one transistor; a ground terminal coupled to the transistor; an output lead coupled to the at least one transistor; an output matching circuit coupled to the output lead and to the at least one transistor; and a baseband impedance enhancement circuit having at least one reactive element coupled to the input matching network. The baseband impedance enhancement circuit is configured to reduce resonances of a baseband termination.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 10, 2023
    Assignee: WOLFSPEED, INC.
    Inventors: Richard Wilson, Marvin Marbell, Michael LeFevre
  • Patent number: 11533025
    Abstract: The present disclosure relates to added isolation between transistors in a multiple path amplifier circuit. The multiple path amplifier circuit includes a substrate, a first transistor on the substrate in a first path, and a second transistor on the substrate in a second path. The multiple path amplifier circuit also includes at least one electrical connection associated with the first and the second transistors and positioned to at least partially extend between the first path and the second path.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 20, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Lei Zhao, Fabian Radulescu
  • Patent number: 11496102
    Abstract: Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: November 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Harauchi, Yoshinobu Sasaki, Miyo Miyashita, Kazuya Yamamoto
  • Patent number: 11483186
    Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Bryan Casper, James Jaussi, Chintan Thakkar, Stefan Shopov
  • Patent number: 11463055
    Abstract: An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Wenming Li, Tong Qiao, Yunfei Wang
  • Patent number: 11411536
    Abstract: Exemplary aspects are directed to a power-amplification circuit including multiple in-parallel circuit paths, each including a power amplifier driving an immittance converter. Current from each output of the respective immittance converters is combined for delivery to a load. In a more specific example, a control circuit may be used to modulate, such as by enabling or disabling power delivered from, one or more of the power amplifiers for fast, coarse resetting of the overall power delivered to the load, and/or to modulate one or more of the modulate immittance converters (e.g., via a phase or signal-timing adjustment) to finely tune the resetting of the overall power delivered to the load. Using the control circuit for providing both the coarse adjustment and the fine adjustment, and fast acting precise delivery of overall power delivered to a load may be realized for any of a variety of applications.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 9, 2022
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Kawin Surakitbovorn, Juan Rivas-Davila, Lei Gu
  • Patent number: 11405005
    Abstract: A radio frequency amplifier circuit is provided. A matching circuit is configured on a radio frequency path of an input end or an output end of an amplifier. An inductance-capacitance resonance circuit and the matching circuit share an inductor included in the matching circuit to generate a corresponding resonance frequency. The matching circuit provides an input impedance or an output impedance matching two fundamental tones in a radio frequency signal at a first frequency and a second frequency. The inductance-capacitance resonance circuit provides a filtering path for filtering a signal component outside a frequency band formed by the first frequency and the second frequency in the radio frequency signal.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 2, 2022
    Assignee: RichWave Technology Corp.
    Inventor: Cheng-Min Lin
  • Patent number: 11387794
    Abstract: In each E-class inverter, an internal voltage detection circuit detects an internal voltage of a resonant type power supply circuit or a matching circuit and adjusts a phase of a driving signal of a MOSFET based on a detected voltage. It is thus possible to match a phase of a current voltage of a sine waveform of each inverter and combine power highly efficiently. Since power combining is performed highly efficiently without using a variable capacitor and variable inductor, it is possible to suppress upsizing of elements and achieve downsizing of a power amplifier circuit.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 12, 2022
    Assignees: DENSO CORPORATION, National University Corporation Toyohashi University of Technology
    Inventors: Takanari Sasaya, Tetsuo Hirano, Takashi Ohira, Naoki Sakai, Takaaki Masaki
  • Patent number: 11387791
    Abstract: Spatial power-combining devices with reduced dimensions are disclosed. Spatial power-combining devices are provided that employ a hybrid structure including both a planar splitter/combiner and an antipodal antenna array. Planar splitters may be arranged to divide an input signal while antipodal antenna arrays may be arranged to combine amplified signals. In other applications, the order may be reversed such that antipodal antenna arrays are arranged to divide an input signal while a planar combiner is arranged to combine amplified signals. Advantages of such spatial power-combining devices include reduced size and weight while maintaining suitable performance for operation in desired frequency bands.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Soack Dae Yoon, Dana Jay Sturzebecher, Patrick Courtney
  • Patent number: 11374539
    Abstract: A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 28, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsuya Kato
  • Patent number: 11362625
    Abstract: A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) has the capability of maintaining high linearity and high efficiency against load mismatch. The reconfigurable PA includes a switch to alternatively connect to a pre-determined resistive load or a pre-determined pure reactive load (jX), i.e., short, open, or finite reactance between an output quadrature coupler and ground. The biasing of Doherty mode is adaptive dependent on the value of reactive loading (jX). The Doherty operation of this PA is based on an architecture configured from a balanced amplifier, e.g., a quasi-balanced amplifier.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: University of Central Florida
    Inventor: Kenle Chen
  • Patent number: 11362690
    Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure is to amplify transmission signals in a wireless communication system, and a transmitting device may include an antenna array including a plurality of antenna elements, a plurality of amplification chains for amplifying signals transmitted through the plurality of the antenna elements, and a power supply line for supplying powers to the plurality of the amplification chains. Herein, the powers used by power amplifiers included in at least one amplification chain of the plurality of the amplification chains may be divided by filtering or by independent pads and branch-lines.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byungjoon Park, Daehyun Kang, Jihoon Kim, Hyunchul Park, Juho Son
  • Patent number: 11336233
    Abstract: A Doherty amplifier includes: a transistor for a carrier amplifier; a transistor for a peak amplifier; a transmission line connected between an output terminal of the transistor for the carrier amplifier and an output terminal of the transistor for the peak amplifier; a stub that is connected in parallel to the output terminal of the transistor for the peak amplifier and that is capacitive and inductive in a working frequency band; and an output matching circuit connected to the output terminal of the transistor for the peak amplifier, the transmission line, and an output load, the output matching circuit to transform an impedance of the output load into an impedance lower than the impedance of the output load.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 17, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shuichi Sakata, Shintaro Shinjo, Keigo Nakatani, Koji Yamanaka
  • Patent number: 11309844
    Abstract: A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kiichiro Takenaka
  • Patent number: 11309842
    Abstract: A power amplifier circuit includes a first path and a second path between an input terminal and an output terminal, a first amplifier located in the first path operative in a first mode, a second amplifier located in the second path operative in a second mode, a first matching circuit between the first amplifier and the output terminal in the first path, a first capacitor having a first end connected to the output terminal side of the first matching circuit, and a second end, a first inductor having a first end connected to the second end of the first capacitor and a second end grounded, and a short-circuit switch connected in parallel with the first inductor. The short-circuit switch short-circuits the first and second ends of the first inductor in the first mode and is placed in an open-circuit position in the second mode.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Hisanori Namie, Hideyuki Satou, Yoshiaki Sukemori
  • Patent number: 11283411
    Abstract: A method for making a wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, the amplifier including: a signal source adapted to generate an input signal; a hybrid coupler or a splitter network adapted to receive the input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input the first output signal; a peak amplifier adapted to receive as input the second output signal; an output network arranged between the carrier and peak amplifiers and a delivery node adapted to be connected to a load, the output network including a recombination node adapted to receive the signals output by the carrier amplifier and the peak amplifier, and a transmission line implemented as a printed circuit track applied to an insulating substrate, wherein capacitors are inserted on the track wh
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 22, 2022
    Assignee: GatesAir, Inc.
    Inventors: Carlo Bombelli, Silvio Coradi
  • Patent number: 11283474
    Abstract: A method and transmitter for a Doherty power amplifier are provided. According to one aspect, a radio transmitter includes, for each carrier frequency, a filter, a main path and a peak path. The filter suppresses signals outside the selected frequency band to produce a filter output. The main path is configured to make a first adjustment of a magnitude and phase of the filter output to produce a main path signal. The peak path is configured to make a second adjustment of the magnitude and phase of the filter output to produce a peak path signal, a difference between the first adjustment and the second adjustment being dependent on the carrier frequency. Main path signals for each carrier frequency produce a composite main path signal. Peak path signals for each carrier frequency produce a composite peak path signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: March 22, 2022
    Assignee: Telefonaktiebolaset LM Ericsson (Publ)
    Inventor: Yiming Shen
  • Patent number: 11277098
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 15, 2022
    Assignee: NXP USA, Inc.
    Inventors: Xavier Hue, Margaret Szymanowski, Xin Fu
  • Patent number: 11271527
    Abstract: A Doherty power amplifier comprises a splitter network, a first amplifier path comprising at least a first sub-amplifier and a first output matching network; and a second amplifier path comprising at least a second sub-amplifier amplifier and a second output matching network. The Doherty power amplifier further comprises a load modulation network comprising four transmission lines. Each transmission line is a quarter wavelength line at a fundamental frequency of the input signal.
    Type: Grant
    Filed: February 11, 2018
    Date of Patent: March 8, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Zhancang Wang
  • Patent number: 11251829
    Abstract: A radio frequency module is provided. A matching circuit includes an inductor which is connected in series to the power amplifier and is formed in a substrate. The substrate includes a ground layer, a low permittivity portion, and a high permittivity portion. The ground layer at least partially overlaps with a first input terminal of the low-noise amplifier in a plan view from a thickness direction of the substrate. The low permittivity portion at least partially overlaps with the first input terminal in a plan view from the thickness direction, and is provided between the first input terminal and the ground layer. The high permittivity portion is in contact with the inductor and has the permittivity greater than the permittivity of the low permittivity portion.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: February 15, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tetsuro Harada
  • Patent number: 11245364
    Abstract: The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 8, 2022
    Assignee: Ampleon Netherlands B.V.
    Inventors: Abdul Raheem Qureshi, Sergio Carlos da Conceicao Pires
  • Patent number: 11223336
    Abstract: A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: January 11, 2022
    Assignee: NXP USA, Inc.
    Inventors: Xin Fu, Margaret A. Szymanowski
  • Patent number: 11223335
    Abstract: The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 11, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Nan Sun, Linxiao Shen
  • Patent number: 11217056
    Abstract: An embodiment of this disclosure provides an automated payment apparatus. The apparatus includes a photodiode current integrator configured to charge an integration capacitor. The photodiode current integrator includes a first feedback resistor connected along a negative feedback path of an operational amplifier between an output of the operational amplifier and a negative input of the operational amplifier. The photodiode current integrator also includes a second feedback resistor connected along a positive feedback path of the operational amplifier between the output of the operational amplifier and a positive input of the operational amplifier. The photodiode current integrator also includes an integration capacitor connected to the positive input of the operational amplifier and to common circuit ground. The photodiode current integrator also includes a reset switch connected to the positive input of the operational amplifier and to common circuit ground or to additional voltage source.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 4, 2022
    Assignee: Crane Payment Innovations, Inc.
    Inventor: Volodymyr Barchuk
  • Patent number: 11201593
    Abstract: A Doherty amplifier system is disclosed with a carrier amplifier configured to amplify a first portion of a radio frequency (RF) signal. A peaking amplifier with a peaking output is configured to amplify a second portion of the RF signal when it is above a power level threshold. A first inductor is coupled between the main output and a first middle node, and a second inductor is coupled between the first middle node and the peaking output. The first inductor and the second inductor are configured to have a first magnetic coupling to form a first impedance inverter. A third inductor is coupled between the peaking output and a second middle node, and a fourth inductor is coupled between the second middle node and an RF signal output. The third inductor and the fourth inductor are configured to have a second magnetic coupling to form a second impedance inverter.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 14, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11189902
    Abstract: An apparatus and method for electrical power splitting with a reduced physical size by using reactive electrical components, producing an increase in signal isolation among output ports and a reduction in internal electrical losses, and operable over a large bandwidth extending from DC to microwave frequencies. Attenuators with capacitors in parallel are used inboard of each output port to achieve extended broadband operation. 2-way and N-way power splitters and corresponding power combiners are described.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 30, 2021
    Assignee: Scientific Components Corporation
    Inventors: Sahar Merhav, Amir Yerushalmy
  • Patent number: 11190144
    Abstract: A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 30, 2021
    Assignee: pSemi Corporation
    Inventor: Michael P. Gaynor
  • Patent number: 11171610
    Abstract: A transformer-based Doherty power amplifier includes a main power amplifier path and an auxiliary power amplifier path which are connected in parallel. The main power amplifier path includes a main power amplifier, and the auxiliary power amplifier path includes an auxiliary power amplifier. The transformer-based Doherty power amplifier further includes a first linear network circuit or a second linear network circuit. The first linear network circuit is arranged at an input of the main power amplifier and is used to compensate for variations of an input capacitance of the main power amplifier, so as to improve the linearity of the main power amplifier. The second linear network circuit is arranged at an input of the auxiliary power amplifier and is used to compensate for variations of an input capacitance of the auxiliary power amplifier, so as to improve the linearity of the auxiliary power amplifier.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 9, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiangchuan Ren, Ruofan Dai
  • Patent number: 11159125
    Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 26, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Gerard Bouisse, Christian Cassou
  • Patent number: 11146220
    Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include a phase distortion compensation circuit that can compensate for input impedance variations that could otherwise lead to reduced efficiency and power performance. In one specific embodiment, the phase distortion compensation circuit is used to compensate for input impedance variations in the peaking amplifiers of a Doherty amplifier. In such embodiments, the phase distortion compensation circuit can absorb the non-linear input impedances of the peaking amplifiers in a way that may facilitate improved phase maintenance between the carrier and peaking stages of the Doherty amplifier.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventor: Hao Zhang
  • Patent number: 11139785
    Abstract: An LNA circuit includes: paths provided between an input and an output terminals, an LNA provided in at least one path, and a selector selecting one path. The LNA includes: a MOS transistor coupled between a first and a second power supplies, a first inductor coupled to a source of the MOS transistor, a capacitor formed between a gate and the source of the MOS transistor, a second inductor coupled between the gate of the MOS transistor and the input terminal, and a changeover switch coupled parallelly with at least one of the capacitor, and the first and the second inductors. The selector switches between a first state that one path is selected and the changeover switch is on, and a second state that another path is selected and the changeover switch is off. Alternatively, the one path and the another path are respectively provided without and with the LNA.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 5, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Norimasa Hiraoka
  • Patent number: 11128259
    Abstract: A power amplification apparatus, a remote radio unit, and a base station are provided to improve power amplification efficiency. The power amplification apparatus includes an envelope modulator, a main power amplifier, and a first auxiliary power amplifier. The envelope modulator is configured to obtain an envelope voltage based on a received envelope signal and output the envelope voltage to the drain of the main power amplifier. The main power amplifier is connected to the envelope modulator and configured to use the envelope voltage as an operating voltage, and is connected to the first auxiliary power amplifier, to output the envelope voltage to a drain of the first auxiliary power amplifier. The first auxiliary power amplifier is configured to use the envelope voltage received from the main power amplifier as an operating voltage.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 21, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shunzhong Zhang, Lipeng Zhang, Zhonghua Cai
  • Patent number: 11101227
    Abstract: Coupled line structures for wideband applications are provided herein. In certain embodiments, a coupled line structure includes one transmission line that is segmented in a metal layer and another that is substantially continuous in the metal layer, thereby allowing tighter spacing and higher coupling between the transmission lines relative to what is achievable if both transmission lines were continuous. The high coupling in turn aids in achieving wide bandwidth.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 24, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mir A. Faiz, Song Lin, Xudong Wang
  • Patent number: 11069276
    Abstract: A display apparatus includes a display panel, a gate driver, a data driver and a gamma reference voltage generator. The display panel is configured to display an image based on input image data. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The gamma reference voltage generator includes a plurality of gamma amplifiers having varied bias currents. The gamma reference voltage generator is configured to generate gamma reference voltages and to output the gamma reference voltages to the data driver.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunho Lim, Bongho Bae, Ok-Kwon Shin, Chongguk Lee, Myeong Bin Lim, Sehui Jang
  • Patent number: 11043983
    Abstract: A first transmitting circuit transmits a first transmission signal of a first frequency band for 2G. A second transmitting circuit transmits a second transmission signal of a second frequency band for 2G. The second frequency band is higher than the first frequency band. A bypass terminal is connected to an output end of the second transmitting circuit. A third transmitting circuit transmits a third transmission signal of a third frequency band for 4G or 5G. A frequency of a harmonic wave of the third transmission signal overlaps the second frequency band. A substrate includes a ground layer. The ground layer is disposed between part of the second transmitting circuit and part of the third transmitting circuit.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 22, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Naoya Matsumoto
  • Patent number: 11025207
    Abstract: Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: PSEMI CORPORATION
    Inventors: Kashish Pal, John Birkbeck
  • Patent number: 11018629
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, Inc.
    Inventors: Seungkee Min, Margaret A. Szymanowski
  • Patent number: 10985718
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 10978999
    Abstract: Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 10972054
    Abstract: Embodiments of systems and method for automatically biasing power amplifiers using a controllable current source are disclosed. In an embodiment, a bias controller for a power amplifier includes a first reference device source/drain interface, a first controllable current source configured to generate a first reference current in response to a first current control signal and to provide the first reference current to the first reference device source/drain interface, a first reference device gate interface, a first current-to-voltage controller configured to generate a first stabilized voltage in response to the first reference current and to provide the first stabilized voltage to the first reference device gate interface, and a first power amplifier (PA) interface configured to output a first control voltage in response to the first stabilized voltage.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 6, 2021
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma
  • Patent number: 10965254
    Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mattia Fausto Moretti, Paolo Pulici, Alessio Facen