Including Plural Amplifier Channels Patents (Class 330/295)
  • Patent number: 10686423
    Abstract: A phase-shifting circuit 1 includes a signal conductor 2 that transmits signals, and a dielectric body 3 that is disposed to overlap the signal conductor 2, said phase-shifting circuit changing the phase of the signals by changing the area of an overlapping section 5 where the signal conductor 2 and the dielectric body 3 overlap each other. The phase-shifting circuit further includes a transformer unit 7 for matching impedance between the overlapping section 5 and non-overlapping section 6 where the signal conductor 2 and the dielectric body 3 do not overlap each other, said transformer unit being provided at end sections of the dielectric body 3, said end sections being on the input side and output side of the signals.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 16, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Satoshi Yoshihara, Seiji Kado, Nobuaki Kitano
  • Patent number: 10686417
    Abstract: A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: June 16, 2020
    Assignee: CAMBRIDGE CONSULTANTS LIMITED
    Inventors: Bryan James Donoghue, Desmond Phillips, Tan Robert, Peter-Contesse Herve
  • Patent number: 10680560
    Abstract: A communication unit includes a plurality of parallel radio frequency, RF, signal paths. Located between a first RF signal path of the plurality of parallel RF signal paths comprising at least one first RF amplifier and a second signal path comprising at least one second RF amplifier is one of a shared inductor or shared transformer. The at least one first RF amplifier is coupled to a supply voltage via a first switch and at least one second RF amplifier is coupled to the supply voltage via a second switch, and the first switch is closed that provides the supply voltage to the at least one second RF amplifier whilst the second switch is opened.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: June 9, 2020
    Assignee: MediaTek, Inc.
    Inventors: Chih-Hao Sun, Po-Yun Hsiao, Chin-Yen Chao, Yi-Bin Lee
  • Patent number: 10673387
    Abstract: An amplifier package may include a transistor, an output impedance matching circuit and one or more radial stub harmonic traps coupled to a control terminal of the transistor or to an output terminal of the transistor. The output impedance matching circuit and the radial stub harmonic traps may be formed on a single substrate or separate substrates, which may be formed from gallium nitride. Each radial stub harmonic trap may provide a low resistance path to ground for signal energy above a fundamental operating frequency of the amplifier, such as harmonic frequencies thereof.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 2, 2020
    Assignee: NXP USA, Inc.
    Inventors: Ramanujam Srindhi Embar, Roy McLaren
  • Patent number: 10658983
    Abstract: An amplifier has an N number of input networks connected to an input terminal to receive an input signal, a first amplifier to amplify one output signal from the N number of input networks, a (N?1) number of secondary amplifiers to amplify the remaining (N?1) number of output signals, except for the one output signal, from the N number of input networks, where the amplification order of the (N?1) number of secondary amplifiers is determined based on the power level of each output signal from the N number of input networks when the first amplifier is operational, an N number of output networks which are arranged, and a first bias network to supply a D.C. bias voltage to at least one of the N number of output networks. An electrical length of the first bias network is less than 90 degrees.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 19, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Thomas Martin Hone, Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 10630242
    Abstract: A Doherty amplifier has a first amplifier path that includes a first amplifier, a second amplifier path that includes a second amplifier, a power divider, and a short-circuited stub. The power divider receives an RF signal and divides the RF signal into first and second input signals. The power divider includes first and second power divider outputs that produce the first and second input signals, respectively. The short-circuited stub is coupled between the first power divider output and the first amplifier or between the second power divider output and the second amplifier. The first and second amplifier paths are characterized by first and second frequency-dependent insertion phases, respectively. A slope of the first or second frequency-dependent insertion phase is altered by the short-circuited stub. The power divider produces the first and second input signals with a quadrature phase shift.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Roy McLaren
  • Patent number: 10630241
    Abstract: An embodiment of an amplifier includes a first amplifier with a first output terminal, a second amplifier with a second output terminal, and a plurality of microstrip transmission lines electrically connected to the amplifiers. The transmission lines include an impedance inverter line electrically connected between the first and second output terminals, and an output line electrically connected between the second output terminal and an output of the amplifier, where the output line forms a portion of an output impedance transformer. The amplifier also includes a directional coupler formed from a main line and a coupled line positioned in proximity to the main line, where the main line is formed from a portion of one of the transmission lines. The amplifier may also include a module substrate with a plurality of metal layers, where the main line and the coupled line are formed from different portions of the metal layers.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Abdulrhman M. S. Ahmed, Ebrahim M. Al Seragi
  • Patent number: 10629552
    Abstract: An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yu-Ting David Wu, Enver Krvavac, Jeffrey Kevin Jones
  • Patent number: 10608594
    Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Komatsuzaki, Shintaro Shinjo, Keigo Nakatani, Shohei Imai
  • Patent number: 10566183
    Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Ide
  • Patent number: 10547279
    Abstract: An amplifier for amplifying radio frequency signals comprising: a signal splitter configured to split an input radio frequency signal into two or more signals; and two or more switching power amplifiers. Each of the switching power amplifiers is configured to amplify a respective signal of the two or more signals using an active device and output a respective amplified signal at a respective output terminal of the switching power amplifier when the switching power amplifier is activated. Each of the two or more switching power amplifiers has a different maximum output power. The amplifier further comprises: an output node connected to each of the output terminals of the switching power amplifiers to combine the amplified signals and output a combined amplified signal; and control circuitry configured to issue control signal to control bias voltages provided to a gate of each of the active devices of the switching power amplifier to selectively activate and deactivate the active devices.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gavin Watkins
  • Patent number: 10530415
    Abstract: The invention relates to an HF circuit, for example for use in front-end circuits, having improved signal quality in carrier aggregation. According to the invention, a signal path between a duplexer and a diplexer comprises a phase shifter.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 7, 2020
    Assignee: SnapTrack, Inc.
    Inventors: Juha Ellä, Edgar Schmidhammer, Gabriele Kolb, Ratko Jovovic
  • Patent number: 10498292
    Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, INC.
    Inventors: Enver Krvavac, Joseph Gerard Schultz, Yu-Ting David Wu, Nick Yang
  • Patent number: 10491176
    Abstract: An amplifier circuit includes a first adjustable amplification path and a second adjustable amplification path; wherein the first adjustable amplification path and the second adjustable amplification path are configurable in different operating modes selected from a linear operating mode, an efficient operating mode, and an intermediate operating mode to amplify a transmission signal based at least in part on a characteristic of the transmission signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joonhoi Hur, Paul Draxler
  • Patent number: 10483928
    Abstract: A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasushi Oyama, Takayuki Tsutsui, Kazuhito Nakai
  • Patent number: 10476442
    Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Margaret A. Szymanowski, Sarmad K. Musa, Fernando A. Santos, Mahesh K. Shah
  • Patent number: 10476439
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Patent number: 10411665
    Abstract: A resonant cavity combined solid-state amplifier system including a resonant cavity having at least one output port coupled to a high-power transmission line. A plurality of high-power transistors are each configured to generate a variable amount of power input directly into the resonant cavity. The plurality of high-power transistors may be configured such that a failure of one or more of the plurality of high-power transistors does not substantially impede operation of the resonant cavity. A plurality of output impedance matching networks each coupled to one of the plurality of high-power transistors and extending into the resonant cavity are configured to match an impedance of each transistor to an impedance of the resonant cavity and configured to electromagnetically couple power from each of the plurality of high-power transistors into the resonant cavity to provide a combined high-power output to the high-power transmission line.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 10, 2019
    Assignee: Diversified Technologies, Inc.
    Inventors: Erik G. Johnson, Marcel P. J. Gaudreau, John Kinross-Wright, Frederick Marvin Niell, III, David B. Cope
  • Patent number: 10411654
    Abstract: An amplifier has an N number of input networks connected to an input terminal to receive an input signal, a first amplifier to amplify one output signal from the N number of input networks, a (N?1) number of secondary amplifiers to amplify the remaining (N?1) number of output signals, except for the one output signal, from the N number of input networks, where the amplification order of the (N?1) number of secondary amplifiers is determined based on the power level of each output signal from the N number of input networks when the first amplifier is operational, an N number of output networks which are arranged, and a first bias network to supply a D.C. bias voltage to at least one of the N number of output networks. An electrical length of the first bias network is less than 90 degrees.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Thomas Martin Hone, Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 10389315
    Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chulkyu Lee, Shih-Wei Chou, Ying Duan
  • Patent number: 10355645
    Abstract: A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyeon Seok Hwang, Jong Soo Lee, Seung Chul Pyo
  • Patent number: 10340858
    Abstract: A distributed amplifier (DA) is disclosed. The DA includes a first plurality of inductive elements coupled in series forming a first plurality of connection nodes. The DA also includes a second plurality of inductive elements coupled in series forming a second plurality of connection nodes. The DA further includes a plurality of amplifier cells that each has a main transistor and a cascode transistor coupled into a cascode configuration. The cascode transistor has a current input coupled to a corresponding one of the first plurality of connection nodes. An input transistor has a control terminal coupled to a corresponding one of the second plurality of connection nodes, a current input terminal configured to provide a bias tuning for the DA, and a third current output terminal coupled to a control terminal of the main transistor and configured to provide a separate bias tuning for the DA.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 2, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kevin Wesley Kobayashi
  • Patent number: 10333470
    Abstract: Apparatus and methods for envelope tracking systems are provided. In certain configurations, an envelope tracking system includes a digital filter that generates a filtered envelope signal based on a digital envelope signal representing an envelope of a radio frequency signal, a buck converter controllable by the filtered envelope signal and including an output electrically connected to a power amplifier supply voltage, a digital-to-analog converter module including an output electrically connected to the output of the buck converter and that provides an output current, and a digital shaping and delay circuit configured to generate a shaped envelope signal based on shaping the filtered envelope signal. The shaped envelope signal controls a magnitude of the output current, and the digital shaping and delay circuit controls a delay of the shaped envelope signal to align the output of the digital-to-analog converter module and the output of the buck converter.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 25, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Sabah Khesbak, Yevgeniy A. Tkachenko, David Steven Ripley, Robert John Thompson
  • Patent number: 10320335
    Abstract: An RF amplifier includes an amplifier chip on a flange having an input and an output comprising a parasitic capacitance and a parasitic inductance, a first chip capacitor coupled to the output of the output of the amplifier by a first plurality of bond wires, and a second chip capacitor coupled to the first chip capacitor by a second plurality of bond wires, and an output impedance matching network having an input coupled to the output of the second chip capacitor by a third plurality of bond wires, and an output, and a phase shift between the input and the output of less than 90 degrees, wherein the phase shift from the output of the amplifier chip to the output of the output impedance matching network is 180 degrees.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 11, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Haedong Jang, Bjoern Herrmann, Zulhazmi Mokhti, Richard Wilson
  • Patent number: 10291182
    Abstract: A power amplifier module includes a power amplifier circuit and a control IC. The power amplifier circuit includes a bipolar transistor that amplifies power of an RF signal and outputs an amplified signal. The control IC includes an FET, which serves as a bias circuit that supplies a bias signal to the bipolar transistor. The FET is operable at a threshold voltage lower than that of the bipolar transistor, thereby making it possible to decrease the operating voltage of the power amplifier module.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 14, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Yasuhisa Yamamoto
  • Patent number: 10291185
    Abstract: Systems and methods related to linear load modulated power amplifiers. A power amplifier (PA) system can include a divider that splits a signal into two portions, a first portion directed to an attenuator that attenuates the first portion so that the first portion and the second portion have different powers and a second portion directed to a phase shift component that shifts a phase of the second portion so that the first portion and the second portion have different phases. The PA system can also include a Doherty amplifier circuit where a carrier amplifier amplifies the attenuated first portion and a peaking amplifier amplifies the phase-shifted second portion. The carrier amplifier includes a Class AB driver stage and a Class B output. The peaking amplifier includes a Class B driver stage a Class B output stage.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 14, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Aleksey A. Lyalin, Russ Alan Reisner, Ramon Antonio Beltran Lizarraga
  • Patent number: 10284146
    Abstract: An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 7, 2019
    Assignee: NXP USA, Inc.
    Inventors: Yu-Ting Wu, Nick Yang, Joseph Gerard Schultz
  • Patent number: 10277179
    Abstract: A radio-frequency (RF) power amplifier includes a matching network comprising at least one matching network circuit corresponding to at least one symmetry node, at least one detector for detecting power of a detected signal at the symmetry node of the matching network, and generating at least one control signal according to the power of the detected signal, wherein the detected signal is an odd harmonic of an RF signal when the RF power amplifier operates in a differential mode or an even harmonic of the RF signal when the RF power amplifier operates in a common mode, and at least one adjusting circuit for adjusting the RF signal according to the at least one control signal.
    Type: Grant
    Filed: October 1, 2017
    Date of Patent: April 30, 2019
    Assignee: MEDIATEK INC.
    Inventors: Jui-Chih Kao, Ming-Da Tsai, Po-Sen Tseng
  • Patent number: 10263570
    Abstract: The present invention provides an amplifier arrangement for amplifying a broadband signal, the amplifier arrangement comprising a signal splitter configured to receive the broadband signal and output a first split signal and a second split signal, and a balanced amplifier that is coupled to the signal splitter and is configured to amplify the first split signal and the second split signal and is configured to output a single amplified broadband signal based on the amplified first split signal and the amplified second split signal. The present invention further provides a respective method.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 16, 2019
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Orell Garten, Raimon Göritz
  • Patent number: 10228464
    Abstract: A method and circuit are provided for implementing enhanced CMOS inverter based optical Transimpedance Amplifiers (TIAs). A transimpedence amplifier (TIA) includes a photo-detector, and the TIA is formed by a first TIA inverter and a second TIA inverter. The first TIA inverter has an input from a cathode side of the photo-detector and the second inverter has an input from an anode side of the photo-detector. A replica TIA is formed by two replica inverters, coupled to a respective input to a first operational amplifier and a second operational amplifier. The first operational amplifier and the second operational amplifier have a feedback configuration for respectively regulating a set voltage level at the cathode side of the photo-detector input of the first inverter and at the anode side of the photo-detector input of the second inverter.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew B. Frank, Raymond A. Richetta
  • Patent number: 10218315
    Abstract: Embodiments described herein relate to a Doherty amplifier. The Doherty amplifier may include a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output. The Doherty amplifier may also include a combining network configured for combining signals emerging at outputs of the amplifiers. The signals are combined at a combining node. The combining network includes a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier. The combining network also includes a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier. The combining network also includes a first 180 degrees phase shifter and a second 180 degrees phase shifter. Additionally, the combining network includes a third impedance inverter.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: February 26, 2019
    Assignee: Ampleon Netherlands B.V.
    Inventor: Xavier Bruno Jean Moronval
  • Patent number: 10218326
    Abstract: A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jiang Chen, Jeremy Goldblatt, Jose Cabanillas
  • Patent number: 10204992
    Abstract: Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 12, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Walter H. Nagy, Lyndon Pattison
  • Patent number: 10171037
    Abstract: Embodiments of the disclosure relate to a multi-mode power management system supporting fifth-generation new radio (5G-NR). The multi-mode power management system includes first tracker circuitry and second tracker circuitry each capable of supplying an envelope tracking (ET) modulated or an average power tracking (APT) modulated voltage. In examples discussed herein, the first tracker circuitry and the second tracker circuitry have been configured to support third-generation (3G) and fourth-generation (4G) power amplifier circuits in various 3G/4G operation modes. The multi-mode power management system is adapted to further support a 5G-NR power amplifier circuit(s) in various 5G-NR operation modes based on the existing first tracker circuitry and/or the existing second tracker circuitry.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 1, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10171039
    Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: David Seebacher, Christian Schuberth, Peter Singerl, Tim Canning, Richard Wilson, Haedong Jang
  • Patent number: 10153734
    Abstract: An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 11, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Poh-Boon Leong, Chia-Liang (Leon) Lin
  • Patent number: 10148228
    Abstract: A Doherty amplifier is able to enhance efficiency in low-power and high-power RF communication states by enabling carrier and peaking amplifiers as required, and controlling bias modulation, depending on traffic loading levels in each of a set of consecutive communications timeslots. For example, if, in a low-power state, traffic loading levels do not exceed a relatively lower threshold in a communications timeslot, carrier amplifiers are selectively enabled as needed, peaking amplifiers are not enabled, and carrier amplifier bias levels are kept substantially constant. If, in an intermediate-power state, the lower threshold is exceeded but a relatively higher threshold is not exceeded, all carrier amplifiers are enabled, peaking amplifiers are selectively enabled, and bias levels are kept substantially constant. If, in a high-power state, the higher threshold is exceeded, all carrier and peaking amplifiers can be enabled, and the peaking amplifier bias tracks the RF envelope of the received RF signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 4, 2018
    Assignee: NXP USA, INC.
    Inventors: Donald Vernon Hayes, Joseph Staudinger, Abdulrhman M. S. Ahmed
  • Patent number: 10116276
    Abstract: An RF power amplifier circuit includes a power divider, multiple power amplification circuits and a power combiner that cooperatively perform power amplification on an RF input signal so as to output an RF output signal, and an impedance conversion circuit that has a circuit terminal coupled to one of the power divider and the power combiner which has a microstrip structure, and that is configured such that a conversion impedance, which is an impedance seen into the impedance conversion circuit from the circuit terminal, matches an impedance seen into the power divider or the power combiner from the circuit terminal. The microstrip structure has a physical length associated with the conversion impedance.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 30, 2018
    Assignee: National Chi Nan University
    Inventors: Yo-Sheng Lin, Chien-Chin Wang
  • Patent number: 10103690
    Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 16, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Naveen Yanduru, Chris Stephens, Jean-Marc Mourant, Chuying Mao
  • Patent number: 10090295
    Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 2, 2018
    Assignee: NXP B.V.
    Inventors: Jozef Reinerus Maria Bergervoet, Gerben Willem de Jong, Gian Hoogzaad
  • Patent number: 10069618
    Abstract: RF circuitry, which includes RF RX circuitry, an RF PA, RF TDD switching circuitry, and RF TX switching circuitry, is disclosed. The RF TX switching circuitry is coupled between the RF PA and the RF TDD switching circuitry. The RF PA receives and amplifies an RF input signal to provide an RF TX signal. During a first CA FDD-TDD operating mode, the RF TX signal has a first FDD TX carrier frequency, the RF TDD switching circuitry forwards a first filtered RF TDD RX signal to the RF RX circuitry, and the RF TX switching circuitry provides isolation between the RF PA and the RF TDD switching circuitry. During a first TDD TX operating mode, the RF TX signal has a first TDD TX carrier frequency and the RF TX switching circuitry forwards the RF TX signal to the RF TDD switching circuitry.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: September 4, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10055493
    Abstract: Generating a playlist may include designating a seed track in an audio library; identifying audio tracks in the audio library having constructs that are within a range of a corresponding construct of the seed track, where the constructs for the audio tracks are derived from frequency representations of the audio tracks, and the corresponding construct for the seed track is derived from a frequency representation of the seed track; and generating the playlist using at least some of the audio tracks that were identified.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 21, 2018
    Assignee: Google LLC
    Inventors: Geremy A. Heitz, III, Adam Berenzweig, Jason E. Weston, Ron J. Weiss, Sally A. Goldman, Thomas Walters, Samy Bengio, Douglas Eck, Jay M. Ponte, Ryan M. Rifkin
  • Patent number: 10051563
    Abstract: Disclosed are an adaptive power controllable WIFI adjusting method and device, wherein the method includes the following steps that are suitable for a WIFI mobile terminal to execute: determining a WIFI adjustment object as well as an adjustment target value by detecting a current WIFI application environment and/or communication status; obtaining a current value of the WIFI adjustment object by detecting the WIFI adjustment object; comparing the adjustment target value with the current value, and coupling back a comparison result; performing an initial adjustment and a fine adjustment on the WIFI adjustment object according to the coupled-back comparison result, and making a value of the adjustment object obtained after the adjustments consistent with the adjustment target value through precise adjustment, calibration, and correction.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: August 14, 2018
    Assignee: ZTE Corporation
    Inventor: Shaowu Shen
  • Patent number: 10038418
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 31, 2018
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 10038408
    Abstract: A chopper stabilized amplifier that utilizes a multi-frequency chopping signal to reduce chopping artifacts. By utilizing a multi-frequency chopping signal, the amplifier DC offset and flicker noise are translated to the higher chopping frequencies but are also smeared, or spread out in frequency and consequently lowered in amplitude. This lower amplitude signal allows for less stringent filtering requirements.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 31, 2018
    Assignee: Cactus Semiconductor, Inc.
    Inventor: Scott Cameron McLeod
  • Patent number: 10033335
    Abstract: A Doherty power amplifier includes a main device in a main amplifier circuit and an auxiliary device in an auxiliary amplifier circuit arranged in parallel with the main amplifier circuit. The Doherty power amplifier further includes a load modulation network including a first open-circuited transmission line connected to an output of the main device; a second open-circuited transmission line connected to an output of the auxiliary device; and an impedance transformation and phase compensation network connected with the output of the main device and the output of the auxiliary device for providing a combined output power. The first and second open-circuited transmission lines are arranged directly adjacent one another to form, during operation, a mutual coupling therebetween.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 24, 2018
    Assignee: City University of Hong Kong
    Inventors: Wing Shing Chan, Xin Yu Zhou, Shao Yong Zheng, Shi Chang Chen, Derek Ho
  • Patent number: 10027352
    Abstract: A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 17, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Daniele Mastantuono, Sven Mattisson, Roland Strandberg, Lars Sundström
  • Patent number: 10020782
    Abstract: A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device may include a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 10, 2018
    Assignee: DSP GROUP LTD.
    Inventors: Avi Cohen, Ron Pongratz
  • Patent number: 10009711
    Abstract: Approaches, techniques, and mechanisms are disclosed for allowing multiple distinct and diverse wireless services (e.g., Wi-Fi, Bluetooth, Radio Frequency for Consumer Electronics (RF4CE), ZigBee, etc.) to share common frequencies while utilizing a single set of antennas. Among other potential benefits, the techniques may permit the sharing of common frequencies amongst multiple services with reduced (or no) interference amongst the services relative to conventional designs, which, depending on the embodiment, may increase performance, improving manufacturability, save design and material cost, and so forth. According to one embodiment, a multi-input directional coupler printed circuit may be implemented for multiple wireless services. This device may include a single directional coupler with reduced or no loss, placed in series with two combiners that provide high isolation for wireless signals.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 26, 2018
    Assignee: TiVo Solutions Inc.
    Inventor: Gary L. Sanders
  • Patent number: 9998196
    Abstract: An antenna device includes: antennas; magnetic oscillation element units converting electrical energy to high-frequency power; and a modulator outputting electrical energy input from outside to at least two magnetic oscillation element units, with a time difference to differentiate phases of high-frequency power converted from electrical energy by at least two magnetic oscillation element units. The magnetic oscillation element units respectively include a pair of electrodes, and further include, between the pair of electrodes, a PIN layer, a free layer, and an intermediate layer. A resistance value of an element configured by the PIN, free and intermediate layers changes according to the angle between the magnetization direction of the PIN layer and the magnetization direction of the free layer. The antennas transmit electromagnetic waves to open space outside the magnetic oscillation element units with the supply of high-frequency power.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 12, 2018
    Assignee: DENSO CORPORATION
    Inventors: Koutarou Mizunuma, Yuu Watanabe, Yasushi Kouno, Eiichi Okuno, Takuya Fuse, Hirokazu Ohyabu