Including Plural Amplifier Channels Patents (Class 330/295)
  • Patent number: 9564864
    Abstract: The disclosure relates to an enhanced Doherty amplifier that provides significant performance improvements over conventional Doherty amplifiers. The enhanced Doherty amplifier includes a power splitter, combining node, a carrier path, and a peaking path. The power splitter is configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output. The carrier path includes carrier power amplifier circuitry, a carrier input network coupled between the carrier splitter output and the carrier power amplifier circuitry, and a carrier output network coupled between the carrier power amplifier circuitry and the Doherty combining node.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: February 7, 2017
    Assignee: Cree, Inc.
    Inventor: Raymond Sydney Pengelly
  • Patent number: 9553676
    Abstract: Methods and systems for split voltage domain receiver circuits are disclosed and may comprise amplifying received electrical signals in a plurality of partial voltage domains, and combining the amplified received signals, utilizing a stacked cascode amplifier for each partial voltage domain, into a single differential signal in a single voltage domain. The stacked cascode amplifiers may comprise a feedback loop having a comparator which controls a current source in each domain. The signals may be received from a photodiode, which may be integrated in the integrated circuit. The amplified signals may be combined via stacked common source or common emitter amplifiers. The received signals via may be amplified by stacked inverters. The amplified received signals may be AC or DC coupled prior to the combining. The received electrical signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked and may be controlled by feedback loops.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 24, 2017
    Assignee: Luxtera, Inc.
    Inventor: Brian Welch
  • Patent number: 9548702
    Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 17, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Sabah Khesbak
  • Patent number: 9548709
    Abstract: Techniques for simultaneously receiving multiple transmitted signals with independent gain control are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a low noise amplifier (LNA) and first and second receive circuits. The LNA amplifies a receiver input signal and provides (i) a first amplified signal for a first set of at least one transmitted signal being received and (ii) a second amplified signal for a second set of at least one transmitted signal being received. The first receive circuit scales the first amplified signal based on a first adjustable gain selected for the first set of transmitted signal(s). The second receive circuit scales the second amplified signal based on a second adjustable gain selected for the second set of transmitted signal(s). The first and second adjustable gains may be independently selected, e.g., based on the received powers of the transmitted signals.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 17, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Vladimir Aparin
  • Patent number: 9515368
    Abstract: One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: December 6, 2016
    Assignee: NXP B.V.
    Inventors: Maristella Spella, Raf Lodewijk Jan Roovers
  • Patent number: 9503035
    Abstract: There is provided a high-frequency amplifier including a divider, a plurality of amplifiers for amplifying a high-frequency signal distributed by the divider and outputting the amplified high-frequency signal, a combiner for combining amplified high-frequency signals, a base substrate, a conductor pattern that is connected to a ground end of each of the amplifiers, and a ground electrode. Each of the conductor patterns has a first conductive portion. A slot is disposed between the two conductor patterns connected to the corresponding adjacent amplifiers. Between the adjacent amplifiers, two vias are formed so that the slot is sandwiched between the vias. One of the two conductor patterns is connected to the ground electrode via one of the two vias, and the other one of the conductor patterns is connected to the ground electrode via the other one of the two vias.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 22, 2016
    Assignee: TDK CORPORATION
    Inventors: Tomohiko Shibuya, Atsushi Ajioka, Atsushi Tsumita, Sadaharu Yoneda
  • Patent number: 9503030
    Abstract: A radio frequency power amplifier comprises an input and output terminals, a main and peak amplifier stages, and an output power combiner for combining a main output signal and a peak output signal into an output signal. The output power combiner comprises a first combiner terminal electrically coupled to a main output terminal, a second combiner terminal electrically coupled to a peak output terminal, a first transition structure extending from the first combiner terminal in a first direction to a first end, a second transition structure extending from the second combiner terminal in the first direction to a second end, a first electrical conductor arranged between the first and the second ends, and a second electrical conductor arranged between the second combiner terminal and the output terminal. The first electrical conductor extends in a second direction perpendicular to the first direction. The second electrical conductor extends in the first direction.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: November 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Igor Ivanovich Blednov
  • Patent number: 9494957
    Abstract: Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Yeshwant Nagaraj Kolla, Dhaval Rajeshbhai Shah
  • Patent number: 9496832
    Abstract: There is provided an amplifier arrangement comprising: a main amplifier connected to receive an input signal and generate an amplified version of the input signal; an additional amplifier, having a smaller geometry than the main amplifier, connected to receive the input signal and generate an amplified version thereof; and wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: November 15, 2016
    Assignee: SnapTrack, Inc.
    Inventor: Martin Paul Wilson
  • Patent number: 9459637
    Abstract: Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Yeshwant Nagaraj Kolla, Dhaval Rajeshbhai Shah
  • Patent number: 9444500
    Abstract: The present invention relates to a modulation circuit of a digital transmitter, a digital transmitter, and a signal modulation method. The modulation circuit includes: a first synchronizing circuit and a digital modulator, where the first synchronizing circuit separately perform phase delay on a first local-frequency signal or a second local-frequency signal to obtain corresponding delay signals, and perform phase adjustment on a digital baseband signal by using the delay signals, to generate a first adjusted signal and a second adjusted signal; and the digital modulator modulates the first adjusted signal by using the first local-frequency signal, to generate a first radio-frequency signal, and modulates the second adjusted signal by using the second local-frequency signal, to generate a second radio-frequency signal.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: September 13, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wufeng Wang, Min Yi, Nianyong Zhu, Bingxuan Mo
  • Patent number: 9437914
    Abstract: A power processing circuit includes a first portion, a second portion, a third portion, a resistor, a first coupling portion, and a second coupling portion. The first portion, the second portion, and the third portion are connected to respective external components. The resistor is used for isolating signals between the second portion and the third portion. The first coupling portion and the second coupling portion are substantially U-shaped coupling structures and are positioned at different sides of the resistor. The first coupling portion is connected to the first portion, the second portion, and ground. The second coupling portion is connected to the first portion, the third portion, and ground.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 6, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yu-Chih Chueh
  • Patent number: 9438187
    Abstract: An amplifying device of an embodiment includes: a first amplifier amplifying a first component of an input signal; a first output circuit having an input connected to an output of the first amplifier and converting impedance seen from an output of the first output circuit to make the converted impedance seen from the first amplifier; a second amplifier amplifying a second component of the input signal with a bias deeper than that of the first amplifier; a second output circuit having an input connected to an output of the second amplifier, having a longer electrical length than that of the first output circuit part, and converting impedance seen from an output of the second output circuit to make the converted impedance seen from the second amplifier; and a combiner combining the first component amplified by the first amplifier and the second component amplified by the second amplifier.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 9438175
    Abstract: In one embodiment, a cascode amplifier includes an amplifier circuit, a replica circuit, a bias circuit, and a feedback circuit. The amplifier circuit includes a first transistor and a second transistor. The second transistor is cascode-connected to the first transistor. The replica circuit includes a third transistor and a fourth transistor. The third transistor has a control terminal connected to a control terminal of the first transistor. The fourth transistor is cascode-connected to the third transistor. The bias circuit applies a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor. The feedback circuit performs a feedback control of a voltage of the control terminal of the third transistor. The feedback circuit reduces the difference between a reference current and a current at a predetermined point of the replica circuit.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kohei Onizuka
  • Patent number: 9438174
    Abstract: An amplifier comprises a first amplifier circuit, a second amplifier circuit, a hybrid-coupler circuit and a termination. The hybrid-coupler circuit comprises an output port and an isolation port. The termination in this context is connected to the isolation port of the hybrid-coupler circuit. The termination comprises a first switch, a first capacitor and a first inductance.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 6, 2016
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Sebastian Stempfl, Bernhard Kaehs, Uwe Dalisda, Lothar Schenk
  • Patent number: 9413301
    Abstract: A noise-canceling LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises a first and a second amplifier branch, each having an input terminal connected to an input terminal of the LNA circuit. The first amplifier branch comprises an output terminal for supplying an output current of the first amplifier branch and a common source or common emitter main amplifier. The main amplifier has an input transistor having a first terminal, which is a gate or base terminal, operatively connected to the input terminal of the first amplifier branch, a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor, and an output capacitor operatively connected between the second terminal of the input transistor and the output terminal of the first amplifier branch.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 9, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Sven Mattisson, Stefan Andersson
  • Patent number: 9413336
    Abstract: To provide a multiband-support radio-frequency module in which the occurrence of a harmonic signal in an amplifier circuit is suppressed and the output of a radio-frequency signal containing unwanted harmonic components is prevented. A first signal path SL1 and a second signal path SL2 are provided such that they intersect each other at least once in a multilayer substrate 2, as viewed from above. With this configuration, high-output radio-frequency signals output from a first amplifier circuit 31 and a second amplifier circuit 32 can be prevented from interfering with other elements disposed in the multilayer substrate 2. It is thus possible to provide a multiband-support radio-frequency module 1 exhibiting excellent RF characteristics by suppressing the occurrence of harmonic signals in each of the first and second amplifier circuits 31 and 32 and by preventing the output of radio-frequency signals containing unwanted harmonic components.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 9, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yuji Takematsu
  • Patent number: 9407221
    Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki
  • Patent number: 9401342
    Abstract: A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: July 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shun Meen Kuo, Margaret Szymanowski, Paul Hart
  • Patent number: 9397616
    Abstract: An amplifier including a main amplifier circuit and at least one peaking amplifier circuit. The peaking amplifier circuit is selectively operable to operate in combination with the main amplifier circuit. The main amplifier circuit and the peaking amplifier circuit each include an active device operation as an inverse Class-F amplifier element. The main amplifier circuit and the peaking amplifier circuit also each include a combined matching and resonator network coupled with an output of the respective active device so the active device operates as an inverse Class-F device, and a combined matching and resonator network coupled with an input of the respective active device.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 19, 2016
    Assignee: CommScope Technologies LLC
    Inventors: Marcello Donati, Fortunato Facchinetti
  • Patent number: 9391572
    Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: July 12, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Joseph Staudinger
  • Patent number: 9385668
    Abstract: A cableless high power RF or microwave amplifier may amplifies an RF or microwave signal. The amplifier may include: an input signal divider (DIV) that has a DIV input connector that receives the RF or microwave signal and that divides this input signal into multiple sub-input signals, each of which is delivered to a DIV output connector; multiple power amplifier units (PAUs), each of which has a PAU input connector that receives an RF or microwave signal and a PAU output connector that delivers an amplified version of the received RF or microwave signal; and an output signal switching combiner unit (SCU) that has multiple SCU input connectors and that coherently sums the signals at the multiple SCU input connectors and delivers this to an SCU output connector. Each of the PAU output connectors may be electrically connected to a different one of the SCU input connectors without connecting cables.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 5, 2016
    Assignee: DAICO INDUSTRIES, INC.
    Inventors: Eddie Blair, Ruben X. Mao, Scott Honma
  • Patent number: 9379680
    Abstract: Systems, methods, and apparatus are disclosed for wideband power amplification in a platform, such as an airplane. An amplifier module may include a first amplification stage. The first amplification stage may comprise a first plurality of amplification circuits. The amplifier module may also include a first plurality of couplers configured to couple an input port to each amplification circuit of the first amplification stage. The amplifier module may include a second amplification stage comprising a second plurality of amplification circuits. The amplifier module may also include a second plurality of couplers configured to couple the first amplification stage to the second amplification stage. The amplifier module may include a third plurality of couplers configured to combine an output of each amplification circuit of the second plurality of amplification circuits into an output signal. The third plurality of couplers may comprise one or more Lange couplers.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 28, 2016
    Assignee: The Boeing Company
    Inventors: Alexandros D. Margomenos, Miroslav Micovic, Ara K. Kurdoghlian, Ross L. Bowen
  • Patent number: 9337183
    Abstract: An RF power transistor package includes an input lead, an output lead, and an RF power transistor having a gate, a drain and a defined gain over an RF frequency range for which the RF power transistor is configured to operate. The RF power transistor package further includes a transformer electrically isolating and inductively coupling the gate of the RF power transistor to the input lead. The transformer is configured to block signals below the RF frequency range of the RF power transistor and pass signals within the RF frequency range of the RF power transistor. The RF power transistor package also includes a DC feed terminal for providing DC bias to the gate of the RF power transistor.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Marvin Marbell, EJ Hashimoto
  • Patent number: 9325280
    Abstract: An electronic circuit has a multi-way Doherty amplifier. The multi-way Doherty amplifier comprises a two-way Doherty amplifier with a main stage and a first peak stage that are integrated in a semiconductor device; and at least one further peak stage implemented with a discrete power transistor.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: April 26, 2016
    Assignee: Ampleon Netherlands B.V.
    Inventors: Igor Blednov, Josephus H. B. Van Der Zanden
  • Patent number: 9306515
    Abstract: A power amplifier is provided. The power amplifier comprises a plurality of power amplifier units and a bias unit. The power amplifier units are connected in parallel with each other to receive a differential input signal. The power amplifier units perform a power amplifying so as to output a differential output signal. The bias unit is coupled to the power amplifier units and supplies a plurality of bias signals to the power amplifier units respectively. At least two of the power amplifier units are enable to operate in different class regions in according with the corresponding bias signals.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: April 5, 2016
    Assignee: Shenzhen South Silicon Valley Microelectronics Co. Ltd
    Inventors: Hua-Yu Liao, Cheng-Yu Wang, Ying-Tang Chang
  • Patent number: 9276536
    Abstract: An outphasing amplification apparatus includes: a signal decomposition unit for decomposing an input signal into a first signal and a second signal having predetermined amplitude values, respectively; a first amplification element for amplifying the first signal, and output a first amplification signal; a second amplification element for amplifying the second signal, and output a second amplification signal; and a combiner for combining the first amplified signal and the second amplified signal, wherein the combiner includes a first input transmission line having an impedance converter, a second input transmission line not having an impedance converter, and a combination unit configured to combine a signal produced by the first amplification signal passing through the first input transmission line to have been subjected to impedance conversion by the impedance converter, and a signal produced by the second amplification signal passing through the second input transmission line not having been subjected to imp
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: March 1, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Patent number: 9252067
    Abstract: An integrated microwave transistor amplifier includes a AlGaN/GaN active transistor arrangement on a thinned Si 1-mil heat spreader. Elongated, plated-through vias extend from the source portions of the transistor arrangement through the spreader to a thick gold supporting layer. A matching circuit is defined on a four-mil GaAs substrate, also with a thick gold support layer. A stepped heat sink supports the matching circuit and the active transistor with surfaces coplanar. Bond wires interconnect the matching circuit with the gate or drain connections of the transistor.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: February 2, 2016
    Assignee: Lockheed Martin Corporation
    Inventor: Mahesh Kumar
  • Patent number: 9252715
    Abstract: A variable-bias power amplifier is provided, comprising: a first variable voltage source generating first bias voltages based on bias control signals; a first amplifier circuit amplifying an output RF signal to generate a first amplified signal based on the first bias voltages; a second variable voltage source generating second bias voltages based on the bias control signals; a second amplifier circuit amplifying the output RF signal to generate a second amplified signal based on the second bias voltages; and a DC isolation circuit between the first amplifier circuit and the second amplifier circuit, electrically isolating DC currents at the first amplifier from DC currents at the second amplifier, wherein the first variable voltage source can be controlled independently from the second variable voltage source, and the first amplifier circuit, the second amplifier circuit, and the DC isolation circuit are all formed on a single die.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 2, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jeffrey K. Jones, Paul R. Hart, Michael E. Watts
  • Patent number: 9214901
    Abstract: A radio frequency system includes a first power splitter, a first push-pull power amplifier and a second push-pull power amplifier. The first power splitter is configured to receive a first radio frequency signal and generate a first output signal and a second output signal. The first push-pull power amplifier is configured to amplify the first output signal. The first push-pull power amplifier comprises a first set of transistors including at least two radio frequency power transistors and a first output transformer. The second push-pull power amplifier is configured to amplify the second output signal. The second push-pull power amplifier includes a second set of transistors including at least two radio frequency power transistors and a second output transformer. An output of the first transformer is galvanically and directly connected to an output of the second output transformer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 15, 2015
    Assignee: MKS Instruments, Inc.
    Inventor: Christopher Michael Owen
  • Patent number: 9209754
    Abstract: A device includes a Doherty amplifier having a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a variable impedance coupled to an output of the Doherty amplifier, and a controller configured to set the variable impedance to a first impedance when an output power level of the Doherty amplifier is less than a threshold and to a second impedance when the output power level of the Doherty amplifier is above the threshold.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 8, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramanujam Srinidhi Embar, Joseph Staudinger, Geoffrey G. Tucker
  • Patent number: 9209116
    Abstract: A semiconductor device package includes a solid metal base with a top surface and an electrically conductive chip mounting area on the top surface. First and second pairs of conductive leads are attached to the base and extend away from one another in opposite directions. First and second amplifiers are attached to the top surface and are electrically connected to the first and second pairs of leads. The first pair is separated from the second pair by a horizontal gap between inner edge sides of the leads. A reference line in the horizontal gap that extends perpendicular to edges of the base divides the chip mounting area into first and second chip mounting sections. An area of the first chip mounting section is smaller than an area of the second chip mounting section. The first and second leads have a smaller width than the third and fourth leads.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Alexander Komposch, Soon Ing Chew, Herman Hugo, Simon Ward
  • Patent number: 9190970
    Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: November 17, 2015
    Assignee: NXP B.V.
    Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9184703
    Abstract: A power amplifier using N-way Doherty structure with adaptive bias supply power tracking for extending the efficiency region over the high peak-to-average power:ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 10, 2015
    Assignee: Dali Systems Co. Ltd.
    Inventors: Kyoung Joon Cho, Wan Jong Kim, Shawn Patrick Stapleton
  • Patent number: 9172338
    Abstract: Various embodiments include a power amplifier having power amplifier cells located in a die, conductive contacts overlying a surface of the die and coupled to the amplifier cells, and conductive lines overlying a surface of the die between the conductive contacts and coupled to the power amplifier cells. Additional apparatus are described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Hongtao Xu, Georgios Palaskas
  • Patent number: 9160285
    Abstract: A signal amplifier having an inverted topology may include: a first common source-type amplifying unit connected to a power supply terminal and amplifying a first band signal among input signals; a second common source-type amplifying unit connected to a ground terminal and amplifying a second band signal among input signals; and an output matching unit performing impedance matching with respect to a first band between the first common source-type amplifying unit and an output terminal and performing impedance matching with respect to a second band between the second common source-type amplifying unit and the output terminal. The first common source-type amplifying unit, the output matching unit, and the second common source-type amplifying unit may form a single current path between the power supply terminal and the ground terminal.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 13, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Nack Gyun Seong
  • Patent number: 9141832
    Abstract: A power combining and outphasing system and related techniques for simultaneously providing both wide-bandwidth linear amplification and high average efficiency is described. Providing linear amplification encompasses the ability to dynamically control an RF output power level over a wide range while still operating over a wide frequency bandwidth. The system and techniques described herein also operate to maintain high efficiency across a wide range of output power levels, such that a high average efficiency can be achieved for highly modulated output waveforms.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: David J. Perreault, Alexander Sergeev Jurkov, Taylor W. Barton
  • Patent number: 9130504
    Abstract: An HF resonator has a cylindrical cavity made of a dielectric material. The cavity includes a first cylindrical portion, a second cylindrical portion, and a dielectric ring that connects the first portion and the second portion. The inner face of the first cylindrical portion has an electrically conductive first inner coating. An inner face of the second cylindrical portion has an electrically conductive second inner coating. An electrically conductive first enclosed coating is arranged between the first cylindrical portion and the dielectric ring. An electrically conductive second enclosed coating is arranged between the second cylindrical portion and the dielectric ring. The first enclosed coating is conductively connected to the first inner coating. The second enclosed coating is conductively connected to the second inner coating. The HF resonator includes a device that is provided for applying a high-frequency electric voltage between the first enclosed coating and the second enclosed coating.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 8, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Back, Oliver Heid, Michael Kleemann
  • Patent number: 9118288
    Abstract: A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: August 25, 2015
    Assignee: MEDIATEK INC.
    Inventors: Jie-Wei Lai, Meng-Hsiung Hung, Robert Bogdan Staszewski
  • Patent number: 9112458
    Abstract: Embodiments of a low-complexity and potentially physically small wideband impedance transformer that can be used in a combining network of a wideband Doherty amplifier are disclosed. In one embodiment, a wideband Doherty amplifier includes Doherty amplifier circuitry and a wideband combining network. The wideband combining network includes a wideband quarter-wave impedance transformer that includes a quarter-wave impedance transformer and compensation circuitry connected in parallel with the quarter-wave impedance transformer at a low-impedance end of the quarter-wave impedance transformer. The compensation circuitry is configured to reduce a total quality factor of the wideband quarter-wave impedance transformer as compared to a quality factor of the quarter-wave impedance transformer, which in turn increases a bandwidth of the wideband quarter-wave impedance transformer, and thus a bandwidth of the wideband Doherty amplifier.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: August 18, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Sashieka Seneviratne, Igor Spokoinyi
  • Patent number: 9112451
    Abstract: An electronic radio system for power amplification of a radiofrequency signal having an electronic circuit having at least one in-service amplifier component, a detector measuring at least one electrical parameter of the in-service amplifier component, having at least the intensity of the electric current supplying the in-service amplifier component, a power attenuator adjusting the output power of the electronic circuit, and a programmable circuit receiving and transmitting commands to control the modules of the radio electronic system. The programmable circuit furthermore includes means for obtaining at least one measurement value relating to the intensity of the electric current supplying said in-service amplifier component of said detector and means for controlling said power attenuator in the case where at least one measurement value obtained exceeds a predetermined threshold value corresponding thereto. The invention also relates to an associated electronic circuit protection method.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: August 18, 2015
    Assignee: THALES
    Inventors: Pierre Bertram, Yannick Menard, Christophe Desevedavy, Eric Souchard
  • Patent number: 9106459
    Abstract: A communication circuit apparatus includes: multiple level shift circuits, each of which receives an input signal corresponding to a respective communication bus; an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold; multiple input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts the input signal to a voltage signal, and outputs the voltage signal as an identification signal; and an identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits. The one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 11, 2015
    Assignee: DENSO CORPORATION
    Inventor: Takahisa Koyasu
  • Patent number: 9086464
    Abstract: An magnetic resonance imaging (MRI) device includes at least one amplifier, a control module which controls an operating module of the at least one amplifier, a back-up control module, a determination unit for determining whether the control module is operating normally, and a switching module for performing a switching operation to switch operations of the control module to the at least one back-up control module in the event of abnormal operation of the control module.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Lee, Seung-je Choi, Hyug-rae Cho
  • Patent number: 9088248
    Abstract: An amplifier includes a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted. Furthermore, the amplifier includes a first upper active sub cell and a second upper active sub cell, each including a biasing terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output. The amplifier includes a bias controller configured to provide a first biasing signal to the first upper active sub cell and a second biasing signal to the second upper active sub cell based on an output power of the output signal.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 21, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Amr Zohny, Stephan Leuschner, Jan-Erik Mueller
  • Patent number: 9077285
    Abstract: An embodiment of an electrical device includes a device package and a plurality of amplifier paths physically contained by the device package. Each amplifier path includes an amplifier stage electrically coupled between an input and an output to the amplifier stage, and the amplifier stages of the plurality of amplifier paths are symmetrical. In a further embodiment, the amplifier paths have translational symmetry within the device package. In another further embodiment, transistors comprising the amplifier stages of the plurality of amplifier paths are substantially identical in size. The electrical device may be incorporated into an amplifier system that further includes an external input network and an external output network. For example, the amplifier system may be configured in a Doherty amplifier topology.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Damon G. Holmes
  • Patent number: 9071198
    Abstract: An integrated Doherty amplifier circuit comprising a main input terminal, a peak input terminal and an output terminal, a main input conductor and a peak input conductor that are offset from one another in a first direction, the main and peak input conductors extend in a second direction that is perpendicular to the first direction, and wherein an input end of the main input conductor is coupled to the main input terminal and an input end of the peak input conductor is coupled to the peak input terminal, an output conductor that extends in the second direction, an output end of the output conductor is coupled to the output terminal, a main amplifier stage extends in the second direction and has a main stage input and a main stage output, a peak amplifier stage extends in the second direction and has a peak stage input and a peak stage output.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: June 30, 2015
    Assignee: NXP, B.V.
    Inventor: Iordan Konstantinov Svechtarov
  • Patent number: 9059664
    Abstract: An amplifier includes a signal processing circuit configured to generate an orthogonal signal orthogonal to an input signal; a first D/A converter configured to convert the orthogonal signal into a first analog signal; a second D/A converter configured to convert the input signal into a second analog signal; and an analog computing circuit configured to generate a constant envelope signal based on the first analog signal from the first D/A converter and the second analog signal from the second D/A converter.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toru Maniwa, Shigekazu Kimura
  • Publication number: 20150145601
    Abstract: The invention relates to a Doherty amplifier for amplifying an input signal at an operating frequency, comprising: a main amplifier; a first peak amplifier; a second peak amplifier, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal, a plurality of peak amplifiers, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal; a first input phase shifter; a second input phase shifter; a first capacitor coupled between the source and drain of the first peak amplifier; a first output phase shifter and a second output phase shifter.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 28, 2015
    Inventors: Xavier Moronval, Gerard Jean-Louis Bouisse, Jean-Jacques Bouny
  • Publication number: 20150145602
    Abstract: An apparatus includes a main amplifier core and auxiliary amplifier core(s), an input signal splitter connected to inputs of the main amplifier core and the auxiliary amplifier core(s), and an output combiner connected to outputs of the main amplifier core and an the auxiliary amplifier core(s). The input signal splitter is configured to split an input signal into a first signal for the main amplifier core and at second signal(s) for the auxiliary amplifier core(s) according to frequency dependent nonlinear input drive functions. The output combiner is configured to combine output signals of the main amplifier core and the auxiliary amplifier core(s), and to provide a continuum of optimum termination impedances of the main amplifier core for the fundamental frequency and at least one harmonic frequency over a predetermined bandwidth of operation, in a low power region. The low power region is defined by the auxiliary amplifier core(s) being inactive.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Tilman FELGENTREFF, Christian MUSOLFF, Georg FISCHER
  • Publication number: 20150145600
    Abstract: The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main and peaking amplifier receive dynamic power supply voltages to operate an RF power amplifier in a high efficiency range for a particular output voltage. The power supply voltages may be changed based on an output voltage so that the power amplifier operates within a high efficiency plateau. In one embodiment, different discrete power supply voltage levels are used for different output voltage ranges. In another embodiment, a continuous time varying power supply voltage is provided as the power supply voltage. A dynamic supply voltage may be generated having a lower frequency than a signal path of the power amplifier.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Joonhoi Hur, Paul J. Draxler