Abstract: A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.

Abstract: Embodiments described herein relate to a Doherty amplifier. The Doherty amplifier may include a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output. The Doherty amplifier may also include a combining network configured for combining signals emerging at outputs of the amplifiers. The signals are combined at a combining node. The combining network includes a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier. The combining network also includes a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier. The combining network also includes a first 180 degrees phase shifter and a second 180 degrees phase shifter. Additionally, the combining network includes a third impedance inverter.

Abstract: Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Abstract: Embodiments of the disclosure relate to a multi-mode power management system supporting fifth-generation new radio (5G-NR). The multi-mode power management system includes first tracker circuitry and second tracker circuitry each capable of supplying an envelope tracking (ET) modulated or an average power tracking (APT) modulated voltage. In examples discussed herein, the first tracker circuitry and the second tracker circuitry have been configured to support third-generation (3G) and fourth-generation (4G) power amplifier circuits in various 3G/4G operation modes. The multi-mode power management system is adapted to further support a 5G-NR power amplifier circuit(s) in various 5G-NR operation modes based on the existing first tracker circuitry and/or the existing second tracker circuitry.

Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Abstract: An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

Abstract: A Doherty amplifier is able to enhance efficiency in low-power and high-power RF communication states by enabling carrier and peaking amplifiers as required, and controlling bias modulation, depending on traffic loading levels in each of a set of consecutive communications timeslots. For example, if, in a low-power state, traffic loading levels do not exceed a relatively lower threshold in a communications timeslot, carrier amplifiers are selectively enabled as needed, peaking amplifiers are not enabled, and carrier amplifier bias levels are kept substantially constant. If, in an intermediate-power state, the lower threshold is exceeded but a relatively higher threshold is not exceeded, all carrier amplifiers are enabled, peaking amplifiers are selectively enabled, and bias levels are kept substantially constant. If, in a high-power state, the higher threshold is exceeded, all carrier and peaking amplifiers can be enabled, and the peaking amplifier bias tracks the RF envelope of the received RF signal.

Abstract: An RF power amplifier circuit includes a power divider, multiple power amplification circuits and a power combiner that cooperatively perform power amplification on an RF input signal so as to output an RF output signal, and an impedance conversion circuit that has a circuit terminal coupled to one of the power divider and the power combiner which has a microstrip structure, and that is configured such that a conversion impedance, which is an impedance seen into the impedance conversion circuit from the circuit terminal, matches an impedance seen into the power divider or the power combiner from the circuit terminal. The microstrip structure has a physical length associated with the conversion impedance.

Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.

Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.

Abstract: RF circuitry, which includes RF RX circuitry, an RF PA, RF TDD switching circuitry, and RF TX switching circuitry, is disclosed. The RF TX switching circuitry is coupled between the RF PA and the RF TDD switching circuitry. The RF PA receives and amplifies an RF input signal to provide an RF TX signal. During a first CA FDD-TDD operating mode, the RF TX signal has a first FDD TX carrier frequency, the RF TDD switching circuitry forwards a first filtered RF TDD RX signal to the RF RX circuitry, and the RF TX switching circuitry provides isolation between the RF PA and the RF TDD switching circuitry. During a first TDD TX operating mode, the RF TX signal has a first TDD TX carrier frequency and the RF TX switching circuitry forwards the RF TX signal to the RF TDD switching circuitry.

Abstract: Generating a playlist may include designating a seed track in an audio library; identifying audio tracks in the audio library having constructs that are within a range of a corresponding construct of the seed track, where the constructs for the audio tracks are derived from frequency representations of the audio tracks, and the corresponding construct for the seed track is derived from a frequency representation of the seed track; and generating the playlist using at least some of the audio tracks that were identified.

Abstract: Disclosed are an adaptive power controllable WIFI adjusting method and device, wherein the method includes the following steps that are suitable for a WIFI mobile terminal to execute: determining a WIFI adjustment object as well as an adjustment target value by detecting a current WIFI application environment and/or communication status; obtaining a current value of the WIFI adjustment object by detecting the WIFI adjustment object; comparing the adjustment target value with the current value, and coupling back a comparison result; performing an initial adjustment and a fine adjustment on the WIFI adjustment object according to the coupled-back comparison result, and making a value of the adjustment object obtained after the adjustments consistent with the adjustment target value through precise adjustment, calibration, and correction.

Abstract: A chopper stabilized amplifier that utilizes a multi-frequency chopping signal to reduce chopping artifacts. By utilizing a multi-frequency chopping signal, the amplifier DC offset and flicker noise are translated to the higher chopping frequencies but are also smeared, or spread out in frequency and consequently lowered in amplitude. This lower amplitude signal allows for less stringent filtering requirements.

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Abstract: A Doherty power amplifier includes a main device in a main amplifier circuit and an auxiliary device in an auxiliary amplifier circuit arranged in parallel with the main amplifier circuit. The Doherty power amplifier further includes a load modulation network including a first open-circuited transmission line connected to an output of the main device; a second open-circuited transmission line connected to an output of the auxiliary device; and an impedance transformation and phase compensation network connected with the output of the main device and the output of the auxiliary device for providing a combined output power. The first and second open-circuited transmission lines are arranged directly adjacent one another to form, during operation, a mutual coupling therebetween.

Abstract: A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Abstract: A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device may include a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power

Abstract: Approaches, techniques, and mechanisms are disclosed for allowing multiple distinct and diverse wireless services (e.g., Wi-Fi, Bluetooth, Radio Frequency for Consumer Electronics (RF4CE), ZigBee, etc.) to share common frequencies while utilizing a single set of antennas. Among other potential benefits, the techniques may permit the sharing of common frequencies amongst multiple services with reduced (or no) interference amongst the services relative to conventional designs, which, depending on the embodiment, may increase performance, improving manufacturability, save design and material cost, and so forth. According to one embodiment, a multi-input directional coupler printed circuit may be implemented for multiple wireless services. This device may include a single directional coupler with reduced or no loss, placed in series with two combiners that provide high isolation for wireless signals.

Abstract: An antenna device includes: antennas; magnetic oscillation element units converting electrical energy to high-frequency power; and a modulator outputting electrical energy input from outside to at least two magnetic oscillation element units, with a time difference to differentiate phases of high-frequency power converted from electrical energy by at least two magnetic oscillation element units. The magnetic oscillation element units respectively include a pair of electrodes, and further include, between the pair of electrodes, a PIN layer, a free layer, and an intermediate layer. A resistance value of an element configured by the PIN, free and intermediate layers changes according to the angle between the magnetization direction of the PIN layer and the magnetization direction of the free layer. The antennas transmit electromagnetic waves to open space outside the magnetic oscillation element units with the supply of high-frequency power.

Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a buffer that is implemented inside the device package. Specifically, the amplifiers can be implemented with a gate bias modulation buffer inside the device package, where the gate bias modulation buffer is configured to provide a modulated bias signal to a transistor gate of the amplifier.

Abstract: According to an embodiment, a circuit package includes a programmable switch component having a plurality of input terminals arranged on the programmable switch component, a plurality of output terminals arranged on the programmable switch component and configured to be coupled to a plurality of amplifiers, and a plurality of switches. Each switch of the plurality of switches is coupled between an input terminal of the plurality of input terminals and an output terminal of the plurality of output terminals. Each switch of the plurality of switches includes a radio frequency (RF) switch and is configured to pass an RF signal when closed. Each input terminal of the plurality of input terminals is coupled to two switches of the plurality of switches.

Abstract: A Doherty power amplifier includes a carrier amplifier, a peaking amplifier, and a peaking amplifier bias circuit coupled to the peaking amplifier and configured to provide a peaking amplifier bias signal to the peaking amplifier based on a saturation level of the carrier amplifier.

Abstract: Certain aspects of the present disclosure relate to methods and apparatus for power amplifier control. A power amplifier network includes a first path comprising a first power amplifier. The power amplifier network further includes a second path comprising a second power amplifier. The power amplifier network further includes a common input path to both the first path and the second path. The power amplifier network further includes a first power control network for controlling a first signal applied to the first power amplifier. The power amplifier network further includes a second power control network for controlling a second signal applied to the second power amplifier, wherein the first power control network is different from the second power control network.

Abstract: A power amplifier includes an outphasing amplifier. The outphasing amplifier includes a first amplifier and a second amplifier, and is configured to provide a first amplified RF signal and a second amplified RF signal that is phase shifted from the first amplified RF signal. The power amplifier further includes an output circuit that is configured to combine RF power of the first and second amplified RF signals at a summing node. The output circuit includes a first branch connected between the first amplifier and a summing node and a second branch connected between the second amplifier and the summing node. The first and second branches are each configured to match an output impedance of the first and second amplifiers and to phase shift the first and second amplified RF signals for an outphasing operation using common reactive components for the match of the output impedance and the outphasing operation.

Abstract: A Doherty power amplifier includes a main power amplification circuit, an auxiliary power amplification circuit, a connection circuit, and an impedance conversion circuit. An output end of the main power amplification circuit and an output end of the auxiliary power amplification circuit are connected to two ends of the connection circuit separately by using bonding wires. The output end of the auxiliary power amplification circuit is further connected to one end of the impedance conversion circuit by using a bonding wire, and the other end of the impedance conversion circuit is connected to an output load.

Abstract: Various embodiments of switched amplifiers are disclosed herein. In some embodiments, a switched amplifier may include a first amplifier; a second amplifier; an input matching network common to both the first and second amplifiers; and at least one switch to couple an input of the switched amplifier, via the input matching network, to one of the first amplifier or the second amplifier. In some embodiments, a switched amplifier may include a first amplifier; a second amplifier; an input matching network common to both the first and second amplifiers or an output matching network common to both the first and second amplifiers; and a bias generation circuit to selectively (1) provide a first bias current to the first amplifier or (2) provide a second bias current to the second amplifier, wherein the second bias current is less than the first bias current.

Abstract: In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to gate pads of the plurality of amplifying elements are equalized, and signal path lengths from drain pads of the plurality of amplifying elements to an output-side combiner are equalized.

Abstract: The present invention addresses apparatuses, methods and computer program product for providing improved distance to fault measurement for voltage standing wave ratio (VSWR) on antenna line in networks. An embodiment of the present invention comprises the steps of transmitting a signal to a line to be tested, capturing a forward signal of the signal, capturing a reverse signal of the signal, separating the reflection of the signal in time domain via cross correlation of the forward signal and the reverse signal, and detecting a distance to fault in the line by searching and processing maximum peak position of the captured and separated signals.

Abstract: A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier.

Abstract: A multistage linear power amplifier receiving an input signal. The multistage linear power amplifier comprises a plurality of Class-AB amplifiers connected in a cascade configuration. The plurality of Class-AB amplifiers amplifies the input signal to generate an amplified input signal. At least one of the plurality of Class-AB amplifiers is biased such that the multistage linear power amplifier emulates a Class-C amplifier.

Abstract: A power amplifying radiator is disclosed that includes an electric field receiver or radio frequency (RF) energy coupling and impedance matching element, a capacitive coupler, a cavity combiner including a coaxial-cavity section providing electromagnetic communication with the capacitive coupler, and a phased-array antenna/one or more phased-array antennas. The RF energy coupling and impedance matching element is in electromagnetic communication with the one or more phased-array antennas via the cavity combiner. The cavity combiner includes a center conductor configured and disposed to project from the coaxal-cavity section such that the cavity combiner defines a co-axial cross-sectional configuration. The power amplifying radiator may be included within a high power microwave system.

Abstract: Certain embodiments provide a high frequency semiconductor device including a plurality of unit FETs, an input dividing/matching circuit, an output combining/matching circuit, and a low-frequency-oscillation-suppressing-circuit. The input dividing/matching circuit has an input end and a plurality of divided output ends connected to the unit FETs, and is symmetrical about a center axis of the input end. The output combining/matching circuit has an output end and a plurality of divided input ends connected to the unit FETs, and is symmetrical about a center axis of the output end. The low-frequency-oscillation-suppressing-circuit is connected to at least one of the input end of the input dividing/matching circuit and the output end of the output combining/matching circuit.

Abstract: In dividing units, signals propagating between input ports- and output ports and between input ports and output ports have phases shifted by 90° from phases of signals propagating between the input ports and the output port and between the input ports and the output ports. Amplifiers output amplified signals that are in phase to the dividing units. A combining and dividing unit outputs a combined signal obtained by combining signals from the output ports of the dividing units to an input port of a combining unit. A combining and dividing unit outputs a combined signal obtained by combining signals from the output ports of the dividing units to an input port of a combining unit.

Abstract: A semiconductor device includes a package, an input terminal fixed to the package, an input pre-matched substrate provided in the package, a semiconductor element provided in the package and formed on a substrate different from the input pre-matched substrate, a matching circuit including a circuit element formed on the input pre-matched substrate, a first wire for connecting the input terminal and the circuit element, and a second wire for connecting the circuit element and the semiconductor element, a first MIM capacitor formed as part of the circuit element, and a first stabilization circuit formed as part of the circuit element to reduce oscillation, wherein a lower electrode of the first MIM capacitor is connected to the package through a via provided in the input pre-matched substrate.

Abstract: An amplifier (1) is provided, in particular, wideband amplifier with an input (4) and an output (5) comprising a first amplifier stage (2) and a second amplifier stage (3), wherein the first amplifier stage (2) has an active power splitter with at least one injection point, wherein this injection point corresponds to the input (4) of the amplifier, and at least two discharge points (9a, 9b), wherein this active power splitter is formed according to a traveling wave amplifier principle and the second amplifier stage (3) has at least two injection points (11a, 11b) and at least one discharge point, wherein this discharge point corresponds to the output (5) of the amplifier and is formed as a power coupler. It is essential that the second amplifier stage (3) is formed as a power coupler, wherein this power coupler is formed according to the principle of a reactively matched amplifier.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: Apparatus and methods for multi-mode low noise amplifiers (LNAs) are provided herein. In certain configurations, a radio frequency (RF) system includes a multi-mode LNA including at least a first amplification stage and a second amplification stage electrically connected in a cascade. The RF system further includes a mode control circuit, which receives a mode selection signal and controls the biasing of the first and second amplification stages based on the mode selection signal. The mode control circuit operates the multi-mode LNA in one of a plurality of modes including both a first mode in which the LNA operates with higher gain and better noise figure and a second mode in which the LNA operates with lower gain and higher linearity. Controlling the mode of the multi-mode LNA using the mode selection signal allows the multi-mode LNA to advantageously achieve both the benefits of low noise figure and high linearity.

Abstract: An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A voltage regulator is described. It includes an amplification stage to control a voltage level of a first gain node and of a second gain node in response to an input voltage, to activate a first and a second output stage, respectively. It further includes the first output stage to source a current at an output node of the voltage regulator from a first potential. The voltage regulator includes the second output stage to sink a current at the output node to a second potential. The voltage regulator includes a first operating point control circuit to set the voltage level of the first gain node such that a first maintenance current is sourced by the first output stage; and/or a second operating point control circuit to set the voltage level of the second gain node such that a second maintenance current is sunk by the second output stage.

Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.

Abstract: A first amplifier is coupled to an output node via a first line having first and second portions. A second amplifier is coupled to the output node via a second line having first and second portions. An auxiliary amplifier is coupled via an auxiliary line network to a first intersection between the first and second portions of the first line, and to a second intersection between the first and second portions of the second line. For each of the first and second lines, the first and second portions have a higher-impedance portion and a lower-impedance portion whose combined length is a half wavelength. Lengths of the respective first portions of the first and second lines sum to half a wavelength, and the lengths of the respective second portions of the first and second lines sum to half a wavelength.

Abstract: An apparatus includes a cascode amplifier. The cascode amplifier includes a first transistor and a second transistor. The cascode amplifier is configured to receive a first bias voltage, a second bias voltage, and a signal. The cascode amplifier is also configured to amplify the signal based at least on the first bias voltage and the second bias voltage. The apparatus also includes a first feedback module and a second feedback module. The first feedback module is configured to adjust the first bias voltage based at least on the amplified signal. The second feedback module is configured to adjust the second bias voltage based at least on a voltage distribution across the first transistor and the second transistor. A system and method for maintaining cascode amplifier performance are also provided.

Abstract: The disclosure relates to an enhanced Doherty amplifier that provides significant performance improvements over conventional Doherty amplifiers. The enhanced Doherty amplifier includes a power splitter, combining node, a carrier path, and a peaking path. The power splitter is configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output. The carrier path includes carrier power amplifier circuitry, a carrier input network coupled between the carrier splitter output and the carrier power amplifier circuitry, and a carrier output network coupled between the carrier power amplifier circuitry and the Doherty combining node.

Abstract: Methods and systems for split voltage domain receiver circuits are disclosed and may comprise amplifying received electrical signals in a plurality of partial voltage domains, and combining the amplified received signals, utilizing a stacked cascode amplifier for each partial voltage domain, into a single differential signal in a single voltage domain. The stacked cascode amplifiers may comprise a feedback loop having a comparator which controls a current source in each domain. The signals may be received from a photodiode, which may be integrated in the integrated circuit. The amplified signals may be combined via stacked common source or common emitter amplifiers. The received signals via may be amplified by stacked inverters. The amplified received signals may be AC or DC coupled prior to the combining. The received electrical signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked and may be controlled by feedback loops.

Abstract: Techniques for simultaneously receiving multiple transmitted signals with independent gain control are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a low noise amplifier (LNA) and first and second receive circuits. The LNA amplifies a receiver input signal and provides (i) a first amplified signal for a first set of at least one transmitted signal being received and (ii) a second amplified signal for a second set of at least one transmitted signal being received. The first receive circuit scales the first amplified signal based on a first adjustable gain selected for the first set of transmitted signal(s). The second receive circuit scales the second amplified signal based on a second adjustable gain selected for the second set of transmitted signal(s). The first and second adjustable gains may be independently selected, e.g., based on the received powers of the transmitted signals.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.

Abstract: One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.

Abstract: There is provided a high-frequency amplifier including a divider, a plurality of amplifiers for amplifying a high-frequency signal distributed by the divider and outputting the amplified high-frequency signal, a combiner for combining amplified high-frequency signals, a base substrate, a conductor pattern that is connected to a ground end of each of the amplifiers, and a ground electrode. Each of the conductor patterns has a first conductive portion. A slot is disposed between the two conductor patterns connected to the corresponding adjacent amplifiers. Between the adjacent amplifiers, two vias are formed so that the slot is sandwiched between the vias. One of the two conductor patterns is connected to the ground electrode via one of the two vias, and the other one of the conductor patterns is connected to the ground electrode via the other one of the two vias.