Abstract: A circuit for linearizing the input/output characteristics of a differential amplifier core circuit is described. The differential amplifier core circuit comprises an input stage, a buffer stage, and an output stage. The input stage includes input transistors connected in a common emitter configuration, where the bases of the input transistors are coupled to input terminals. The input stage further includes load circuits coupled between the input transistors and a power supply terminal. The output stage includes output transistors connected in a common emitter configuration, where the output terminals are coupled to the collectors of the output transistors. First and second resistors are coupled between the collectors of the respective output transistors and the power supply terminal. The buffer stage includes a buffer circuit that is coupled between the input and output stages.

Abstract: A high-frequency power amplifier comprises a transistor for high-frequency power which operates and whose current-voltage characteristics greatly change when positive voltage is supplied on its input terminal, an input bias circuit, an output bias circuit, an input impedance matching circuit, an output impedance matching circuit, and a positive voltage generation circuit. The positive voltage generation circuit comprises a detection circuit which detects part of the high-frequency power which is entered to or outputted from the transistor for high-frequency power, a rectification circuit which rectifies the part of the high-frequency power outputted from the detection circuit and outputs pulsating positive voltage, and a smoothing circuit which smoothes the pulsating positive voltage outputted from the rectification circuit and outputs positive voltage.

Abstract: A preamplifier system (10) is provided which amplifies and conditions an input electromagnetic signal for insertion into a high power amplifier. The preamplifier system (10) includes a plurality of cascaded amplifying stages (100a-100d) for incrementally amplifying the input electromagnetic signal, as well as bias control circuitry coupled to the amplifying stages (100a-100d) to electrically bias at least one of those stages into a Class A operational mode and an adjustable phase shift unit (300) coupled to at least one of the amplifying stages (100a-100d) for reversibly shifting the phase of the input electromagnetic signal in accordance with the given high power amplifier's configuration. Each amplifying stage (100a-100d) includes at least one transistor assembly device (110a-110d) having integrally formed therein a plurality of silicon carbide cells coupled one to the other.

Abstract: A low-noise amplifier is disclosed that is capable of amplifying a signal with high gain (e.g., >60 dB) and low noise (e.g., <2 nV/Hz.sup.-1/2) over a large frequency bandwidth (e.g., from 1 Hz to 1 MHz) and with a high input impedance (e.g., >10.sup.6 .OMEGA.), high common mode rejection and high immunity to external noise sources.

Abstract: A circuit for clipping a dynamic focus voltage waveform during a horizontal retrace time is provided so as to prevent an unnecessary voltage from occurring during the retrace time. A high gain amplifier for amplifying horizontal and vertical parabolic waves is provided with an output circuit used as an emitter follower, a D.C. feedback circuit and a boot strap circuit composed of a capacitor. As a result, a display can be provided which is capable of performing a large amplitude operation without increasing power losses, realizing a satisfactory frequency response simultaneously with the amplitude operation and providing excellent focus properties over the entire screen thereof.

Abstract: A microwave power amplifier is comprised of a plurality of series connected amplifier stages. Each stage is provided with a local negative feedback. The addition of the local voltage feedback distribution networks provide correct voltage distribution and equal current distribution for all transistors, such that the peak-to-peak voltage and current swings of each transistor can be set simultaneously to the values required for efficient amplifier operation. The method applies to both FETs and bipolar transistors. The series connected microwave power amplifier is thus characterized as a stack with local voltage feedback networks which provide an equal distribution of voltage across the transistors in the stack. The amplifier stages can be biased and tuned to collectively operate either as a class A or B amplifier.

Abstract: A RF power amplifier with the advantages of high output efficiency and a wide range of gain control is disclosed. By appropriately biasing the power transistor of the power-stage amplifier in the RF power amplifier, the power-stage amplifier functions as a class C amplifier. By varying the bias source of the driving-stage amplifier and keeping the bias sources of the input-stage and power-stage amplifiers at a fixed level, the driving-stage can output a driving signal with a wide range of variable gain. Consequently, the driving signal can be used to drive the power-stage amplifier to obtain highly efficient output and of a wide range of output power gain control.

Abstract: A three-stage amplifier including first, second, and third sequentially coupled stages is compensated without use of compensation capacitors, by applying an input signal to an input of the first stage and a first input of a first feed-forward stage, coupling an output signal of the first feed-forward stage to an output of the second stage, the second stage having an input coupled to an output of the first stage, coupling an output signal of the first stage to an input of a second feed-forward stage, coupling an output of the second feed-forward stage to an output of the third stage, coupling the input signal to an input of a third feed-forward stage, and coupling an output of the third feed-forward stage to the output of the third stage.

Abstract: A broad-band amplifier circuit is furnished with a plurality of amplifiers with a coupling capacitor being interposed between every two adjacent amplifiers. Each coupling capacitor has a capacity large enough to prevent adverse effect of external noise. Accordingly, not only the passing of a signal having a low frequency is allowed, but also an element operable in a high frequency, such as a Schottky transistor, can be provided in each amplifier as a transistor. At least the transistor of the amplifier in the last stage is connected to a diode, so that the charges accumulated between its collector and base while the amplifier stays on are fed back and eliminated. Accordingly, the broad-band amplifier circuit can carry out a flat amplifying operation over a wide range from low to high frequency bands, and therefore, can be used for all the ASK method, IrDA1.0 method, and IrDA1.1 method. Consequently, not only the manufacturing cost, but also the size of the broad-band amplifier circuit can be reduced.

Abstract: A multistage amplifier circuit comprises a current constant mode variable amplifying circuit for amplifying an input signal and current variable mode variable amplifying circuits and for further amplifying the signal amplified by the first variable amplifying circuit. An AGC voltage VAGC is commonly applied between the bases and emitters of an amplification degree control transistor of the current constant mode variable amplifying circuit and amplification degree control transistors of the current variable mode amplifying circuits. Collector currents of the transistors change exponentially with respect to the linearly-varied AGC voltage VAGC. Further, currents each proportional to the collector current of the transistor flow in the transistors. Thus, the gain PG ?dB! of the current constant mode variable amplifying circuit changes linearly with the AGC voltage VAGC.

Abstract: A microwave power amplifier having n stages (n is an integer of at least two), which uses bipolar transistors as amplifying elements. Grounded electrodes, bias applying methods, and bias values of the bipolar transistors of the respective stages are set so that phase rotations of output powers of bipolar transistors of m stages (m is an integer of 1.ltoreq.m.ltoreq.n-1) among the n stages are canceled by phase rotation of at least one of the other bipolar transistors of the (n-m) stages. Therefore, the total phase rotation of the power amplifier can be neutralized, resulting in a microwave power amplifier having excellent distortion characteristics.

Abstract: A DC feed-back circuit for causing a DC voltage of an external transistor in which an output bias current of a record amplifier flows to be equal to a DC voltage of an output terminal is provided so as to decrease power consumption. Thus, a plurality of record amplifying circuits can be incorporated into one IC chip. In particular, in home-use Hi-Fi VCRs, a Hi-Fi record amplifying circuit and video record amplifying circuits can be incorporated into one chip.

Abstract: In a multistage source follower amplifier having input and output terminals, an output source follower amplifier has an output drive transistor of a surface channel type and a load which is connected to the output drive transistor. An input source follower amplifier has an input drive transistor and a load which is connected to the input drive transistor. A middle source follower amplifier unit is located between the input and the output source follower amplifiers and comprises a middle drive transistor of a buried channel type and a middle load which is connected to the middle drive transistor. The input source follower amplifier, the middle source follower amplifier unit, and the output source follower amplifier are connected in cascade to one another between the input and the output terminals.

Abstract: The receiver includes a ceramic filter which is connected to the output side of a mixer circuit for limiting a band, an intermediate frequency amplifying circuit cascade connected to the output side of the ceramic filter in a plurality of intermediate frequency amplifying stages, and a plurality of passive band-pass filters connected between the respective intermediate frequency amplifying stages of the intermediate frequency amplifying circuit. Thereby, the receiver is able to reduce the size and costs thereof.

Abstract: Circuits and methods to minimize total harmonic distortion in an integrated circuit feedback amplifier. Complementary transistors in the signal path are selected so that their base-to-collector capacitances are matched. Additionally, the DC operating currents of such transistors are matched, thereby cancelling non-linearities due to base-to-collector capacitances.

Abstract: An amplifier circuit in a display device for a monitor unit in a computer system or the like, includes first active element whose control electrode is supplied with a signal from an input terminal; a second active element cascade-connected to the first active element; a third active element so connected to the second active element that a junction thereof is connected to an output terminal; an impedance element disposed between the input terminal and the third active element and capable of changing the impedance in accordance with the frequency of the input signal; a first resistance element connected between the junction of the second and third active elements and the control electrode of the first active element; and a second resistance element connected between the input terminal and the control electrode of the first active element and serving to determine the signal amplification factor in cooperation with the first resistance element.

Abstract: A method and apparatus for biasing a differential cascade circuit are provided. The differential cascode circuit includes a first cascade circuit having a first transistor coupled to a second transistor at a first node, and a second cascade circuit having a third transistor coupled to a fourth transistor at a second node. A sensing circuit senses a first differential voltage between the first and second nodes. In response to the sensing of the first differential voltage, a voltage adjusting circuit coupled to the sensing circuit applies a second differential voltage between the gate terminals of the second and fourth transistors such that the first differential voltage is minimized.

Abstract: The invention relates to a semiconductor device including an amplifier, and a mobile telecommunication terminal comprising this semiconductor device. The amplifier has a very high frequency a.c. signal and comprises a last stage but one of depletion-layer MESFET transistors (T3) and a last transistor stage (T4) of the same type, coupled by a d.c. isolation capacitor (C4). This capacitor (C4) forms with the intrinsic diode (.increment.4) of the transistor (T4) of the last stage a series-arranged rectifier circuit. The latter imposes a shift of the mean level of the a.c. signal on the terminals of said isolation capacitor once the amplitude of the positive part of this a.c. signal has exceeded the conduction threshold of the intrinsic diode (.increment.4). This shift of the mean level (-1.5 volts) is used as a negative voltage (-VG) for biasing the coupled gates of all the stages of the amplifier circuit.

Abstract: An analog/digital dual-mode power amplifier which provides a good linearity and a high efficiency comprises a first and a second power field effect transistors, and an input stage, a middle stage and an output stage. An input stage receives the input signal through an input terminal. A middle stage applies a second gate bias voltage appropriately controlled in response to an analog operating mode or a digital operating mode to a second power FET. An output stage provides matching at center frequency and has the impedance of less than 2.OMEGA. for a second harmonic and a third harmonic. Accordingly, a good linearity and high efficiency circuit can be obtained.

Abstract: A circuit for clock recovery from an input signal, particularly an alternating input signal formed from a data signal, the invention calling for a filter/amplifier unit made up of several series-connected resonance ampliers to be formed in a regenerative frequency filter. Unlike series-connected resonance amplifiers without feedback, the filter/amplifier unit has an overall Q-factor in the feedback loop which increases essentially linearly with the number of resonance amplifiers and their Q-factor. This enables the required high overall Q-factor to be obtained for the clock-recovery circuit with a relatively low number of resonance amplifiers with a Q-factor which is low compared with the overall Q-factor. A slope detector, a frequency mixer and the resonance amplifiers have similar assemblies so that the circuit can be designed more simply as a solid-state integrated circuit.

Abstract: A DC feed-back circuit for causing a DC voltage of an external transistor in which an output bias current of a record amplifier flows to be equal to a DC voltage of an output terminal is provided so as to decrease power consumption. Thus, a plurality of record amplifying circuits can be incorporated into one IC chip. In particular, in home-use Hi-Fi VCRs, a Hi-Fi record amplifying circuit and video record amplifying circuits can be incorporated into one chip.

Abstract: A high efficiency multiple power level amplifier circuit for reducing power consumption during low power operations. A plurality of power amplifier stages are cascaded to provide multiple levels of amplification. At least one power amplification stage includes a signal switching network to allow one or any combination of power amplifiers to be switched out when lower power operations are desired. The switched out power amplifiers are biased such that substantially no current is drawn from the power source.

Abstract: A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.

Abstract: A preamplifier for use with high impedance audio frequency transducers, having two capacitance coupled stages each including a field effect transistor connected in follower mode. The two stages provide an impedance converter. The first field effect transistor is of substantially smaller geometry than the second, providing a low noise, low input capacitance. The second stage further reduces output impedance while maintaining low power supply feedthrough. A capacitor connected in shunt between the stages is employed for frequency shaping.

Abstract: A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.

Abstract: An active biasing circuit to provide linear operation of an RF power amplifier. A current generator circuit provides a current to the stages of the RF power amplifier. In the final power amplifier stage the current is applied to a bias control amplifier that includes a transistor connected as a diode. The transistor diode is connected through a resistor to the emitter of a bias control transistor, which is in turn connected to and controls the gate of a transistor power amplifier in the final power amplifier stage of the RF power amplifier with a bias current that is the highest current level needed for highest RF power. The transistor diode and the current generator circuit are also connected to bias control transistors in the other stages of the RF power amplifier such that the other stages are likewise controlled with the current from the current generator.

Abstract: A method of high frequency current signal amplification utilizing Metal-Oxide-Silicon Field Effect Transistors (MOSFETS) allows the use of MOSFETS for current signal amplification in the radio frequency (RF) range of the electromagnetic spectrum and minimizes the effects of parasitic capacitance. A current signal is applied to pluralities of MOSFETS arranged in amplification stages such that the amplification of the input current signal is determined by the ratio of the channel widths of the MOSFETS employed. Alternating amplification stages comprised of N-conductivity type and P-conductivity type devices are employed. The amplification of the signal can be precisely controlled by both the width of the channels within the MOSFETS and the number of current signal amplification stages employed. The output signal can also be converted to a voltage signal by coupling to a source of resistance or reactance.

Abstract: A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The respective width-to-length ratios of the channels of the transistors are unequal, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair.

Abstract: A logarithmic detector having a first input line linked to the base of the first transistor, a second line linked to the base of the second transistor, a third input line linked to the bases of third and fourth transistors, a fourth input line linked to the bases of fifth and sixth transistors, a first output line linked to the collectors of the third and sixth transistors a second output line linked to the collectors of the fourth and fifth transistors and emitters of the third and fifth transistors being linked through the first and second impedances respectively to connect to the first transistor, the emitters of the fourth and sixth transistors being linked through third and fourth impedances to the collector of the second transistor and the emitters of the first and second transistors being linked through 5th and 6th impedances respectively to a current source connected to earth.

Abstract: A fully differential, wide-band transconductance-transimpedence amplifier with a tuneable gain is disclosed. The amplifier includes a transconductance stage for generating a current signal from an inputted voltage signal. The amplifier also has a current gain stage for amplifying the current signal generated by the transconductance stage. Additionally, the amplifier includes as transimpedance stage for generating an output voltage signal from the amplified current signal generated in the current gain stage.

Abstract: An electronic device, for example a signal receiver mounted on a vehicle for opening and closing the doors of the vehicle in response to telecontrol signals from a remote source, includes an intermediate frequency amplifier. The intermediate frequency amplifier comprises two amplifier stages arranged in cascade with respect to the input signal, with the biasing terminals of the two stages being connected in series across the supply. The arrangement gives much reduced current consumption.

Abstract: A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.

Abstract: In a differential amplifier having a pair of emitter follower outputs, power saving is obtained by switching the pull-down currents so that the emitter followers have to provide current to drive the load only in the on direction. The preceding stage is a cascode stage, so that the switching signals for switching the pull-down currents may be derived from the emitter circuits of the cascode stage output transistors.

Abstract: A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.

Abstract: An op-amp comprising a single gain stage amplifier cascaded with a buffer and an output stage. The buffer comprises an amplifier which isolates the gain stage from the output stage to prevent loading of the gain stage and create a more linear op-amp. For frequency compensation, the op-amp utilizes MOSFETs connected in a reversed biased configuration as load compensation capacitors. This technique reduces the non-linear effects of MOSFET gate capacitors utilized in conventional Miller compensation schemes and allows for digital fabrication technology of low distortion, low power supply operational amplifier design.

Abstract: A power amplifier is provided which operates in a quasi-microwave band between 0.8 GHz and 2 GHz with a high output, a small size and low power consumption. Junction type GaAs FETs are connected in a multi-stage manner to form an amplification circuit. An impedance matching/phase adjusting circuit is provided between the respective stages. An input impedance matching circuit, an output impedance matching circuit and bypass capacitors for a power source terminal are provided. Further, a gain control terminal and gate bias terminals for setting operating points of the JFETs are provided, thereby forming an entire arrangement as a semiconductor integrated circuit.

Abstract: An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets.

Abstract: A semiconductor device comprises a two-stage differential amplifier, the amplifier comprising a first differential transistor pair whose transistors are coupled by their source electrodes and each receive an input signal, and a second differential transistor pair whose transistors are coupled by their source electrodes, each of these transistors receive the output of one of the branches of the first differential pair, and each supply an output. In the amplifier each branch of the second differential pair is arranged in series with a branch of the first differential pair so as to form two sub-circuits each including a transistor of the first pair with its load and a transistor of the second pair with its load in a manner such that the two transistors of each sub-circuit share the same current.

Abstract: A differential input circuit has two halves, each half includes a differential input voltage terminal with a first emitter follower having its base terminal connected to the input terminal, having a collector terminal connected to a first voltage terminal, an emitter terminal connected to a first terminal of an emitter resistor. A second emitter follower is provided having has its base terminal connected to the first differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal. A diode-connected transistor is provided having an emitter terminal connected to the emitter terminal of the second emitter follower, having its base and collector terminals connected together. A current source is provided having an output terminal connected to the base and collector terminals of the first diode-connected transistor, and having an input terminal connected to a second voltage terminal.

Abstract: A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.

Abstract: A power amplifier is provided, wherein the output of a first transistor supplied with an input signal at the base thereof is supplied to the base of a second transistor, a current proportional to a collector current of the second transistor is supplied to the emitter of the first transistor by a current mirror circuit, a third transistor is provided for outputting an emitter current in accordance with a base-to-emitter voltage of the second transistor, and emitter currents of the second and third transistors, in accordance with an emitter potential level of the first transistor, is used as an output current. This configuration allows non-linear portions in the transistor characteristics to be cancelled by each other, thereby providing a power amplifier which presents a good linearity.

Abstract: A sequential amplifier having at least two amplifier stages separated by a delay device such that switching means may energize either or both amplifier stages at any given time to obtain maximum gain of the input signal so long as no oscillations occur between stages, thus allowing a signal to be amplified by adjacent amplifier stages without the adverse effects of feedback associated therewith.

Abstract: A sequential amplifier having at least two amplifier stages separated by a delay device such that a clock may control both stages to energize one while the other is de-energized, thus allowing a signal to be amplified by adjacent amplifier stages without the adverse effects of feedback associated therewith.

Abstract: An amplifier circuit having an emitter-grounded amplifying stage formed of a transistor Q1 and a load resistor R.sub.L and having an output stage including an emitter follower formed of transistors Q2 and Q3. The base of the transistor Q1 of the amplifying stage and the base of the transistor Q3 of the output stage are connected with each other for receiving input signals and biased by a bias circuitry 5. The input signals thus given to the base of transistor Q3 for the emitter follower of the output stage cause the transistors Q2 and Q3 to alternately turn on and off to provide a higher output driving power to the load connected to the output terminal than prior art amplifier circuits having conventional emitter followers and resistor feedback amplification networks.

Abstract: A voltage-follower circuit has an input biasing stage that generates an input stage bias current and a tracking bias current. An input stage generates an intermediate voltage signal and sources an input current in response to an input voltage signal and the input stage bias current. An output biasing stage generates an output bias current. An output biasing stage generates an output voltage signal and sinks a portion of the input bias current in response to the intermediate voltage signal and the output bias current. A cancellation stage sinks substantially all of the input current in response to the tracking bias current. A cascode stage isolates the input biasing stage from the input stage and the cancellation stage. A compensation stage sinks a portion of the tracking bias current which is substantially equivalent to the portion of the input bias current sunk by the output stage.

Abstract: A method for providing a positive transmitter power switch-on in a dual-mode mobile phone is disclosed. According to the invention the transmitter is switched on in two or more phases, controlled by the mobile phone microprocessor program. Preferably the power amplifier sections are switched on in a sequence, so that the output power amplifier sections (3 and 4) are first switched on by enabling the transmit enable signal (TXE). Then the input power amplifier sections (1 and 2) are switched on by enabling ramp-up signal (RAMP-UP) Transmission is thereafter enabled by the transmit power control signal (TXC) being switched on, the amplifiers then output the amplified radio frequency input signal (RFIN) to the duplex circuit (10) transmit terminal (TX).

Abstract: A limiter amplifier includes amplifiers connected in cascade each having differential outputs and differential inputs, and a lowpass filter connected between adjacent amplifiers. The filter includes resistors having different values connected between the differential outputs and the differential inputs of adjacent amplifiers, and a capacitor connected between the differential inputs of one of the adjacent amplifiers, the filter thereby limiting a high frequency characteristic of the limiter amplifier.

Abstract: An n-stage amplifier circuit includes n+1 directional couplers connected in series between the circuit input, the amplifier stages, and the circuit output. Each coupler includes first and third ports forming an inverting interface, and second and fourth ports forming a non-inverting interface, the ports being coupled through suitable windings. Feedback lines are connected between adjacent successive couplers. The interfaces of the couplers are connected such that feedback loops covering one or more contiguous successive amplifier stages provide negative feedback for the amplifier circuit.

Abstract: A circuit constituting a system or a subsystem is composed of a cascade connection of a plurality of analog circuit cells. At least one of said analog circuit cells has either the current-sink input terminal and a current-source output terminal or a current-source input terminal and current-sink output terminal and operates in the current mode.