Abstract: A gain-controlled transimpedance amplifier circuit that comprises a first gain unit including an input for receiving a first current and an output, a current source for providing a second current, a second gain unit including an input and an output, a first impedance unit of a first impedance coupled in parallel with the second gain unit, and a comparator including an output, a first input coupled to the output of the first gain unit, and a second input coupled to the output of the second gain unit.

Abstract: Methods of and apparatus for distributing power and biasing RF PAs. A power distribution network includes a pre-final amplifier stage power distribution network and a final amplifier stage power distribution network. The pre-final amplifier stage power distribution network includes one or more pre-final amplifier stage power distribution branches, which may be configured to distribute power from one or more pre-final amplifier power supplies to one or more pre-final amplifier stages. Each pre-final amplifier stage power distribution branch comprises a ? C-R-C network coupled to an inductive load. A final amplifier stage power distribution network is configured to distribute power from a final amplifier stage power supply to a final stage of the amplifier circuit.

Abstract: The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N2), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N3), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Abstract: An object of the present invention is to provide a radio frequency power amplifier of multi stage amplifying method that is designed to reduce instability of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby operate stably. Another object of the present invention is to provide a radio frequency power amplifier that is designed to reduce distortion of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby provide high efficiency.

Abstract: A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.

Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

Abstract: A multiple-stage operational amplifier including a gain stage for amplifying an input signal and implementing a dominant pole producing a frequency response having a gain roll-off with frequency and a unity gain frequency. An intermediate stage is coupled to an output of the gain stage and has a high input impedance and a low output impedance. A high gain amplifier configured as a low gain output stage using resistive feedback and coupled to an output of the intermediate stage drives an output of the operational amplifier and implements a dominant pole at a frequency substantially higher than the unity gain frequency implemented by the dominant pole implemented the gain stage.

Abstract: A dual gate cascade amplifier includes a first transistor and a second transistor electrically connected in series, the second transistor including a first parallel transistor and a second parallel transistor, the first parallel transistor and the second parallel transistor being electrically connected in parallel, a first channel electrically connecting a first end channel region of the first transistor and a second end channel region, wherein one of the first or second end channel regions is a source and the other of the first or second end channel regions is a drain, the second end channel region being a common end channel region shared by the first and second parallel transistors, and a second channel electrically connected to the second end channel region and extending away from the first transistor.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A converter includes an input circuit to receive a single-ended input signal to generate a number of control signals. The control signals have a delay different from one another relative to the single-ended input signal. The converter also includes a first output circuit and a second output circuit. The first output circuit responds to the control signals to generate a first output signal. The second output circuit responds to the control signals to generate a second output signal. The first and second output signals are non-overlapping and form a complimentary signal pair.

Abstract: An integrated power amplifier arrangement with multistage construction is provided, in which a matching filter with integrated capacitance and inductance for impedance transformation is provided between an input transistor and an output transistor. In one example, the inductance of the matching filter is formed as a microstrip conductor, resulting in a significantly higher quality factor of the inductance and hence an improved linearity and an improved efficiency of the integrated power amplifier. The invention can advantageously be employed in particular in integrated transmitting arrangements.

Abstract: An integrated circuit includes a high-frequency power amplifier and a matching circuit. The high-frequency power amplifier has at least one stage of an amplifier element. The matching circuit has a MOSFET and a detector diode. The source of the MOSFET is connected to an input of a first stage amplifier element, the drain is connected to a ground, and the gate is also connected to the ground. A capacitor is connected between the gate of the MOSFET and the ground. The detector diode is connected in parallel between the drain and the gate of the MOSFET. Turning on the MOSFET reduces the effective gain of the first stage amplifier element, thereby allowing mode change.

Abstract: A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.

Abstract: There is provided a high frequency power amplifier circuit capable of enhancing detection accuracy of an output level, necessary for feedback control of the high frequency power amplifier circuit, and capable of executing output power control with higher precision, With the high frequency power amplifier circuit, the detection of the output level, necessary for feedback control of the high frequency power amplifier circuit is executed by use of a current detection method, and in an electronic device comprising a differential amplifier for comparing an output power detection signal with an output level designation signal and for generating a signal for controlling a gain of the high frequency power amplifier circuit according to a potential difference between the two signals, a power source voltage with variation less than that for the power source voltage of the high frequency power amplifier circuit is used as the operational power source voltage of the output power detection circuit.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A circuit for providing a base operating voltage for a bipolar transistor includes a UBE multiplier providing, in response to a working-point control current, a working voltage fed to a circuit for reducing the working voltage in order to generate a base operating voltage smaller than a base-emitter voltage drop of a bipolar power transistor. With this, the bipolar power transistor may be maintained in the class C operation in a flexible and robust manner, so that an amplifier with high efficiency is obtained.

Abstract: Apparatus, methods and articles of manufacture for multiband transmitter power amplification are provided wherein one or more amplifying devices, of which at least one may be one or more current sources, have impedances matched for different input and output frequencies by way of various impedance matching circuits.

Abstract: Provided is a series type Doherty amplifier which includes a first power amplifier and a second power amplifier using a plurality of transformers. The first power amplifier and the second power amplifier are connected in series. The second power amplifier and a first transformer are connected in series. A first path is branched from a junction between the first power amplifier and the second power amplifier and a phase delay device and a second transformer are connected in series. An output port of the second transformer is connected to a junction of a second path of an output port of the second power amplifier. An efficiency of each power amplifier is determined by a ratio of 1:M in size of a final stage of each of the first and second power amplifiers.

Abstract: A power amplifier includes an input network, output stages, coupled in parallel and configured to output power optimally in corresponding power-ranges, the output stages coupled to the input network, an output impedance matching network, coupled to the output stages and not containing a switching element, and a bias-control network, coupled between the output impedance matching network, the input network, and the output stages. In some amplifiers the output impedance matching network does not contain a switching element corresponding to the output stage configured to output power in the highest range. In other amplifiers the bias-control network is configured to isolate output stages by providing a hard shut-off to transistors of the isolated output stages.

Abstract: The invention provides a method for reducing power dissipation in a power amplifier used in wireless communication systems, said power amplifier having transistors showing a quiescent current, wherein the quiescent current of the power amplifier is adaptively changed according to the average output power of the power amplifier. A power amplifier for use in wireless communication systems is provided, said power amplifier having transistors showing a quiescent current, comprises adaptive biasing means changing the quiescent current of the power amplifier in accordance with the average output power of the power amplifier for reducing power dissipation in the power amplifier. A UMTS hand set comprises a power amplifier as specified above.

Abstract: A radio-frequency amplifier is provided. The radio-frequency amplifier includes a transistor having an input terminal, an output terminal, a control terminal, and a transconductance gm. A series-connected feed-through resistance Rf and feed-through capacitance Cf is connected in parallel with the input terminal and the output terminal of the transistor. A load resistance RL is connected to the output terminal. The control terminal of the transistor is biased at a fixed voltage. Part of the transistor noise follows the looped path through the feed-through resistor instead of passing on to the load, which reduces the noise figure of the amplifier. The value of gm, Rf and RL are chosen in a way to keep the input impedance of the amplifier matched to a well-defined signal source impedance.

Abstract: A circuit having an input amplifier and a second amplifier that provides the circuit with a unity gain crossover frequency that is higher than a unity gain crossover frequency of the input amplifier is provided. The circuit has a control input coupled to a control input of the input amplifier and also has a first current connection and a second current connection. The circuit further includes an additional amplifier that is connected in series with the second amplifier and is controlled by the input amplifier.

Abstract: An embodiment of the present invention provides an amplifier system, comprising at least one variable impedance matching network, the output of which provides the input to at least one amplifier stage or provides an output of the power amplifier itself, and a bias network associated with the at least one amplifier stage. The amplifier system may further comprise a controller enabling impedance control to the at least one variable impedance matching network and a supply voltage provided to the at least one variable impedance network and/or the at least one amplifier stage and wherein the at least one variable impedance network and the at least one amplifier stage may be a plurality of impedance networks connected to a plurality of amplifier stages. The at least one variable impedance network may include at least one variable capacitor and the at least one variable capacitor may be a voltage tunable dielectric capacitor which may include Parascan® voltage tunable dielectric material.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: An object of the present invention is to provide a radio frequency power amplifier of multi stage amplifying method that is designed to reduce instability of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby operate stably. Another object of the present invention is to provide a radio frequency power amplifier that is designed to reduce distortion of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby provide high efficiency.

Abstract: A two-stage amplifier that includes a first stage and a second stage and a first component and a second component coupled in series between the first and second stages. The first component is selected to provide AC decoupling of the first and second stages and the second component is selected to provide for the stability of the amplifier while avoiding excessive power dissipation and/or negative impact on overall gain.

Abstract: The output of a differential amplifier circuit group (PA) that amplifies signals inputted to input PINs is connected to a final-stage differential amplifier circuit (PAn). The output of the differential amplifier circuit (PAn) is connected to a detection (DET) circuit. A detect signal sent from the DET circuit is outputted to the (?) side input of a comparator. A bias signal (BP) outputted from a bias circuit is inputted to the base of a PMOS transistor of a source follower circuit. An output signal (SFOUT) outputted from a source terminal thereof is inputted to the (+) side input of the comparator. A result of comparison between the bias signal (BP) and the output signal (SFOUT) is outputted from the comparator as an output signal (COMPOUT).

Abstract: There is provided a high frequency power amplifier circuit capable of enhancing detection accuracy of an output level, necessary for feedback control of the high frequency power amplifier circuit, and capable of executing output power control with higher precision, With the high frequency power amplifier circuit, the detection of the output level, necessary for feedback control of the high frequency power amplifier circuit is executed by use of a current detection method, and in an electronic device comprising a differential amplifier for comparing an output power detection signal with an output level designation signal and for generating a signal for controlling a gain of the high frequency power amplifier circuit according to a potential difference between the two signals, a power source voltage with variation less than that for the power source voltage of the high frequency power amplifier circuit is used as the operational power source voltage of the output power detection circuit.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

Abstract: A single ended highly linear power amplifier includes a component, a 1st transistor pair, and a 2nd transistor pair. The 1st and 2nd transistor pairs are coupled in series with the component, which may be a resistor, inductor and/or linearly loaded transistor, where the node coupling the component to the 1st and 2nd transistor pairs provides the output of the single-ended highly linear power amplifier. The 1st transistors of the 1st and 2nd transistor pairs are coupled to receive an input signal. The 2nd transistors of the 1st and 2nd transistor pairs are each coupled to receive a separate enable signal. The transistor pairs are enabled via their corresponding enable signal to change the gain of the power amplifier with negligible effects on the linearity of the power amplifier. A differential power amplifier includes the single ended power amplifier and a complimentary mirror image of the single ended power amplifier.

Abstract: A ground layer is provided between a first and a second wiring layer. A first transistor provided at the first wiring layer amplifies a supplied high-frequency signal. A second transistor provided at the first wiring layer amplifies the output signal of the first transistor. A first power supply line, which supplies power to the first transistor, is provided at the first wiring layer. A second power supply line, which supplies power to the second transistor, is provided at the second wiring layer.

Abstract: A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Abstract: Variable gain amplifiers offering high frequency response with improved linearity and reduced power dissipation are provided. An amplifier is disclosed that is constructed from a one-stage topology with multiple signal paths and compensation networks for improved linearity and stable operation. In this amplifier, improved performance is obtained by replacing single transistor components with enhanced active devices which incorporate local negative feedback. One embodiment of the invention is a transconductance enhancement circuit that improves transconductance and input impedance relative to the prior art. A further development is an enhanced active cascode circuit that provides improved linearity. A high frequency bipolar transistor switch is also disclosed that incorporates lateral PNP transistors as high frequency switches with improved OFF-state to ON-state impedance ratio to realize a variable gain function.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A single-power-supply Idss-bias RF amplifier is disclosed, which is composed by the first and second stages Amplifiers. The two stages have the same circuit topology except matching circuits. The source terminal of amplifier is grounded directly to reduce a parasitic effect from a bias circuit. It will increase the stability of the RF amplifier and avoid an oscillation. The lossy matching circuits and eliminating resonator circuit are designed to make the RF amplifier unconditional stable. A variable resister is put into to adjust a D.C. voltage on the drain terminal. The current of amplifier could be controlled in a reasonable range. High gain and quit low noise have been obtained.

Abstract: A multi-stage amplifier including a first amplifier stage including a first transistor, the first transistor selected to provide an optimum noise characteristic, and a second amplifier stage including a second transistor, the second transistor selected to provide an optimum gain characteristic.

Abstract: An analog to digital converter and/or related systems which in some aspects may contain but are not limited to: at least one cascade of N gain elements operably couplable with analog circuitry, and a gain element of the at least one cascade having a gain larger than one by an amount such that a noise factor of said at least one cascade operating on a predetermined operable signal at an input of said at least one cascade is substantially minimized.

Abstract: An FET band amplifier for providing a high gain. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages and a BPF 16 inserted halfway in their connection. Each of the amplifiers 11 to 15 acts as a differential amplifier comprising a p-channel FET as an amplification element. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing the low-band component of a signal amplified by the amplifiers 11 to 13 at three stages and thermal noise by removing the high-band component. Thus, each of the amplifiers 14, 15 connected to the rear stage of the BPF 16 is not saturated by a noise component.

Abstract: An analog to digital converter and related systems.

Abstract: An amplifier is disclosed, having an input stage connected to an output stage. The input stage is connected between a positive supply rail and a ground rail and has an input terminal arranged to receive an input signal. The output stage is connected between a positive supply rail and a negative supply rail and has an output terminal. The output stage is adapted to generate an output signal, which is dependent on a received input signal, at the output, and is further adapted such that, in use, a quiescent voltage at the output terminal is at a selected value between a voltage on the positive supply rail and a voltage on the negative supply rail. For driving a grounded load, the quiescent output voltage is preferably zero volts. In preferred embodiments, the input and output stages are formed on a common substrate using CMOS technology, the output stage including one or more NMOS devices having a triple-well structure. A corresponding method of driving a grounded load is also disclosed.

Abstract: A circuit arrangement in which cascaded first and second operating transistors have gate terminals connected to an input signal and a control voltage, respectively. A control path from the control voltage source to the gate terminal of the second operating transistor includes a voltage divider. First and second circuit units are also provided in the control path to selectively enable and disable the voltage divider according to a voltage level of the applied control voltage, thereby causing the circuit to have desirable control characteristics.

Abstract: An operational amplifier with selectable performance characteristics is provided. The operational amplifier provides a sleep mode (e.g., fully disabled) in addition to providing a number of different levels of awake operation (e.g., different performance characteristics). As such, the op-amp can allow a system to use only the power needed to obtain a required level of performance at any point in time. For example, the op-amp may be operated at a minimum power mode, an awake at mid-level power mode, or an awake at maximum power mode.

Abstract: A method and an apparatus for analyzing performance of a multi-stage radio frequency amplifier are described. The method simplifies the multi-stage radio frequency amplifier into equivalent input parts, output parts and mid-stage parts. The mid-stage parts are temporarily unset. Therefore, the equivalent input parts and output parts will be adjusted to make best gain performance and the mid-stage parts will be the next targets for analysis. Repeating the above-mentioned methods for decomposing the circuit can systemize the method for analyzing circuits and problems in each part of the circuit may be found more quickly.