Abstract: In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays.

Abstract: A switching circuit, a charge sense amplifier, and a photon counting device are provided. The switching circuit configured to close and open a connection between a first terminal and a second terminal of a predetermined circuit element, includes: a first transistor comprising a source connected to the first terminal, a drain connected to the second terminal, and a gate; a second transistor comprising a drain, a source, and a gate connected to the drain of the second transistor; a current source configured to supply a current flowing through the drain and the source of the second transistor, to generate a gate voltage of the gate of the second transistor; and a multiplexer configured to receive the gate voltage, a reference voltage, and a control signal, and selectively apply the gate voltage or the reference voltage to the gate of the first transistor based on the control signal.

Abstract: A fast settling reference voltage buffer and method are disclosed. In one of embodiments, An apparatus comprising: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal coupled to a circuit node shunt to ground by a shunt capacitor via a current sensor; a tunable resistor, controlled by a control signal, coupling the circuit node to the feedback node; a load circuit coupled to the feedback node via a switch controlled by a logical signal; and a control circuit for receiving an output of the current sensor and outputting the control signal, wherein the control signal is adapted in accordance with the output of the current sensor.

Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.

Abstract: To obtain an amplifier circuit capable of realizing low power consumption and high-precision output. A controlling unit controls each switch of an offset correction circuit to select one capacitor associated with a voltage level of an input signal selected by an input signal selection unit, have an offset voltage of an operational amplifier generated according to the voltage level of the input signal stored by the selected capacitor, and correct an output of the operational amplifier by using the offset voltage held by the selected capacitor.

Abstract: Techniques are disclosed for canceling an offset component (e.g., dc component or dc offset) in an amplifier circuit. For example, an apparatus comprises an amplifier circuit with an amplifier element and a feedback resistor network coupled between an output of the amplifier element and an input of the amplifier element. The apparatus also comprises a current source coupled to the feedback resistor network, the current source generating a current signal that generates a voltage in a first portion of the feedback resistor network that cancels an offset component present in an input signal received by the amplifier circuit. A second portion of the feedback resistor network may be adjustable so that a gain applied to the input signal is adjustable while the offset component is canceled from the input signal. One or more resistors in the feedback resistor network may be composed of the same or substantially similar material as one or more resistors associated with the current source.

Abstract: A switch-modulator for a radio-frequency power amplifier, arranged to modulate the I-signal and the Q-signal of the complex components (I+j·Q) separately in an I-signal part and a Q-signal part in order to create a modulated I-signal pulse sequence and a modulated Q-signal pulse sequence, wherein the modulation comprises a time-shift of the pulse positions within a sample interval.

Abstract: A chopper comprises a differential difference amplifier, a first switch, and a second switch. The differential difference amplifier comprises a first input stage and a second input stage. The first input stage comprises a non-inverting input terminal and an inverting input terminal. The second input stage comprises a non-inverting input terminal and an inverting input terminal. The first switch is operable to receive a first input voltage and a second input voltage and selectively transfer the first input voltage to one of the non-inverting input terminal of the first input stage and the non-inverting input terminal of the second input stage. The second switch is operable to receive a third input voltage and a fourth input voltage and selectively transfer the third input voltage to one of the inverting input terminal of the first input stage and the inverting input terminal of the second input stage.

Abstract: An amplifier may include a low noise auto-zero circuit with auto-zero capacitors and switch-controlled auxiliary capacitors that function as switched-capacitor low-pass filters. In an acquisition phase of the auto-zero operation, the inputs of an amplifier may be shorted to a common voltage, and a representation of the offset voltage may be acquired by the auto-zero capacitors. In a hold phase of the auto-zero operation, the auto-zero capacitors may be connected to the auxiliary capacitors, and the resulting voltages may be applied to the circuit such that the original offset voltage is cancelled. Moreover, the switched-capacitor filters may reduce the effective sampling noise while maintaining high acquisition bandwidth.

Abstract: The present invention discloses a circuit with three-stage of power-on sequence used for suppressing the pop noise in audio system. It mainly comprises a first resistor (R1); a capacitor (Cout); a first switch (SW1); a second switch (SW2); a soft start device; a first feedback amplifier; and a second feedback amplifier. By using the three-stage of power-on sequence, the present invention can effectively suppress the pop noise when the audio driver is power on.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: A chopper comprises a differential difference amplifier, a first switch, and a second switch. The differential difference amplifier comprises a first input stage and a second input stage. The first input stage comprises a non-inverting input terminal and an inverting input terminal. The second input stage comprises a non-inverting input terminal and an inverting input terminal. The first switch is operable to receive a first input voltage and a second input voltage and selectively transfer the first input voltage to one of the non-inverting input terminal of the first input stage and the non-inverting input terminal of the second input stage. The second switch is operable to receive a third input voltage and a fourth input voltage and selectively transfer the third input voltage to one of the inverting input terminal of the first input stage and the inverting input terminal of the second input stage.

Abstract: An audio device and an audio input/output method are described, which is coupled to an audio port, and includes a capacitor, a load, an output amplifying module, and an input amplifying module. The capacitor and the load are coupled to the audio port. The output amplifying module is operated at a first working voltage, for outputting a first audio signal to the audio port. A direct current (DC) level of the first audio signal is substantially zero volts. The input amplifying module is operated at a second working voltage, in order to receive a second audio signal from the audio port. When the audio port is in an output state, the output amplifying module is enabled and the input amplifying module is disabled, and when the audio port is in an input state, the input amplifying module is enabled and the output amplifying module is disabled.

Abstract: In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.

Abstract: A method of canceling an offset of display device includes coinciding offset directions of amplifiers with one another and canceling offsets of the amplifiers through a chopping operation.

Abstract: A voltage sensing circuit includes a voltage to current converter, an integrator, a sample and hold amplifier, and a modulator. The voltage to current converter produces a modulated current corresponding to an input voltage. The integrator demodulates the modulated current and produces a voltage sum of the demodulated current. The sample and hold amplifier samples the voltage sum and provides an output voltage corresponding to the voltage sum. The modulator modulates the output voltage and provides the modulated voltage to the voltage to current converter as a feedback voltage.

Abstract: The present invention provides a sensor circuit. The sensor circuit comprises a first amplifier which receives a measurement signal via an input end thereof, amplifies the received signal, and outputs the amplified signal via a first output end thereof; a first current source which supplies current (Ir) flowing toward the input resistance (Ri) of the first amplifier; a second current source which supplies current (Ic) flowing toward the input capacitance (Ci) of the first amplifier; and a bias current source which reduces the direct current offset voltage in the output of the first amplifier.

Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract: The present invention relates to a parallel light emitting diode (“LED”) drive circuit and provides a drive circuit configured to drive a parallel array of LEDs. The drive circuit comprises: a switching control signal generator, a plurality of switches, a plurality of sampling resistors, and a plurality of chopper amplifiers. Each switch is coupled to a respective LED in the LED array. Each chopper operational amplifier configured to receive a reference voltage and a switching control signal generated by the switching control signal generator and generate an input offset voltage. Each chopper operational amplifier includes a differential amplifier including an input transistor pair and a current mirror transistor pair, of which the electrical positions can be reserved when the switching control signal is switched between a first state and a second state, wherein the offset voltage, which causes the lightness mismatching in a parallel LED circuit, can be cancelled.

Abstract: An apparatus comprises: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal shunt to a ground node via a shunt capacitor; a resistor coupling the output terminal of the OTA to the feedback node; and a load circuit coupled to the feedback node via a switch controlled by a logical signal, wherein: an impedance of the shunt capacitor is substantially smaller than an input impedance of the load circuit. In an embodiment, the load circuit is a switch capacitor circuit. A corresponding method using an OTA is also provided.

Abstract: In a class AB amplifier circuit, an input stage circuit includes a first differential pair configured to receive a differential signal and a first current mirror circuit connected with the first differential pair through a first node. A middle stage circuit includes a floating constant current source connected with the first node, a first transistor whose gate is applied with a bias voltage, and a first constant current source connected with the first node through the first transistor. A last stage circuit includes a first output stage transistor whose gate is connected with the first node and which controls a voltage of an output terminal. A first phase compensation capacitance has one end connected with a first connection node between the first constant current source and the first transistor and the other end connected with the output terminal.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract: Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.

Abstract: Direct current (DC) offset in and audio driver can cause a constant drain on power even when there is no sound. Furthermore it can cause an audible pop when the audio driver is enabled. A scaled replica output stage can be employed to perform DC offset cancellation offline during a sampling phase. Once DC offset cancellation is achieved, the audio driver uses a full scale output stage during the operation phase.

Abstract: In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory.

Abstract: A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second comparators generate respective select signals to turn on only one of the first or the second differential input stage in each amplifier circuit depending on a value of the respective part of the differential input signal. In operation, the first and second complementary differential input stages of each amplifier circuit not being turned on at the same time.

Abstract: An offset cancellation circuit can include an amplifier having a negative input, a positive input, and a single-ended output, wherein the positive input is configured to receive a reference voltage. The circuit also can include a capacitor having a first terminal and a second terminal. The first terminal can be coupled to the negative input of the amplifier. The capacitor can be configured to sample the offset voltage of the amplifier. The second terminal of the capacitor can be selectively coupled to the output of the amplifier.

Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.

Abstract: A programmable device includes an operational amplifier and circuitry. The operational amplifier is configured to generate an output voltage based on input voltages at input terminals thereof. The circuitry is configured to provide the input voltages to the operational amplifier. The configuration of the circuitry allows the programmable device to implement discrete-time or continuous-time functions. The circuitry includes a resistor network and a capacitor network configured to be selectively coupled to the operational amplifier.

Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.

Abstract: A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

Abstract: A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two switched signals such that each of the switched signals is associated with one of the processing circuits leaving at least one unassociated processing circuit. A controller circuit is configured to switch one of the switched signals to be associated with one of the unassociated processing circuit(s) upon at least one specified interval such as, for example, at a transition of the switched signal. The circuit may be incorporated into an audio amplifier configured to provide information carried on the switched signals to one or more speakers that provide an audio output. A one-processor circuit approach includes switching frames of a switched signal between positive and negative inputs of a processor circuit to average out errors introduced by the processor circuit.

Abstract: An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed.

Abstract: Provided is a switched capacitor amplifier capable of outputting a stable output voltage. The switched capacitor amplifier is capable of operating so as to eliminate a charge/discharge time difference between an input capacitor (18) and an output capacitor (19). Accordingly, in a shift from a hold state to a sample state, for example, even if one terminal voltage (V2) of the output capacitor (19) abruptly increases to an output voltage (VOUT), another terminal voltage (Vs) of the output capacitor (19) does not increase abruptly. In other words, an input voltage to an internal amplifier (11) does not increase abruptly. Therefore, an output voltage of the internal amplifier (11) becomes stable and accordingly the output voltage (VOUT) becomes stable as well.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device. The amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications.

Abstract: Embodiments provide a configurable low noise amplifier circuit including a gain stage coupled to the input of the low noise amplifier circuit, the low noise amplifier circuit being configurable between one of a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes an impedance matching stage coupled to an input of the configurable low noise amplifier circuit, the output of the impedance matching stage providing an input bias voltage for the impedance matching stage, and a feedback stage coupled to an output of the impedance matching stage and a voltage source, the feedback stage providing a compensated operating voltage for the impedance matching stage.

Abstract: A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.

Abstract: A chopper-stabilized amplifier (20A) includes an amplifier (3), an input chopper (2A) having a first input (4) receiving an input signal (VIN+), an output (5) coupled to a first input of the amplifier, and a feedback resistor (9) coupled to an output (6) of the amplifier to couple a feedback signal (VFB+) to a second input of the amplifier (3). The input chopper operates in response to a chopping clock (CHOP_CLK). If the amplifier (3) is unacceptably close to a saturation condition, the chopping clock (CHOP_CLK) is disabled to reduce input leakage current (ILEAKAGE) of the chopper-stabilized amplifier.

Abstract: An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN?), a positive differential output (VOUT+), and a negative differential output (VOUT?). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT?. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT? when VIN+ and VIN? are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT?, respectively.

Abstract: A high-gain differential amplifier that is capable of high speed operation, outputs a signal representing a difference between signals respectively inputted to first and second input terminals and a phase-inverted signal thereof via first and second output terminals respectively. A first switching element making a short-circuit between the first input terminal and the second output terminal when turned on, a second switching element making a short-circuit between the second input terminal and the first output terminal when turned on, and a third switching element making a short-circuit between the first output terminal and the second output terminal when turned on are provided. The third switching element is turned on for a predetermined period while the first and second switching elements are turned off. Subsequently, the third switching element is switched off, and the first and second switching elements are switched on.

Abstract: A chopper stabilized amplifier may include a modulation circuit that performs a digital conversion on an input signal so as to convert the input signal into a first modulated signal by using a modulation signal, the modulation signal being a rectangular wave having a predetermined frequency, an operational amplifier circuit that amplifies the first modulated signal so as to convert the first modulated signal into a second modulated signal, and a demodulation circuit that performs analog conversion on the second modulated signal so as to convert the second modulated signal into an output signal by using a demodulation signal, the demodulation signal having a waveform that corresponds to the differences between frequency components of the first modulated signal and the second modulated signal.

Abstract: A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal.

Abstract: A chopper-stabilized amplifier (20A) includes an amplifier (3), an input chopper (2A) having a first input (4) receiving an input signal (VIN+), an output (5) coupled to a first input of the amplifier, and a feedback resistor (9) coupled to an output (6) of the amplifier to couple a feedback signal (VFB+) to a second input of the amplifier (3). The input chopper operates in response to a chopping clock (CHOP_CLK). If the amplifier (3) is unacceptably close to a saturation condition, the chopping clock (CHOP_CLK) is disabled to reduce input leakage current (ILEAKAGE) of the chopper-stabilized amplifier.

Abstract: A voltage output device which is capable of preventing an increase in circuit scale and includes an offset compensation function that is suitably applicable in particular to a drive circuit for display devices such as liquid crystal display panels. The voltage output device includes an operational amplifier which has an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.