Abstract: Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device.

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

Abstract: Current-feedback instrumentation amplifiers that include dynamic element matching for the input transconductance amplifiers by periodically swapping the transconductance amplifiers between the instrumentation amplifier input and the feedback input. The instrumentation amplifiers may include a gain error reduction loop, which loop corrects differences in the gains of the input transconductance amplifiers and eliminates the ripple in the instrumentation amplifier output caused by the dynamic element matching. If chopper stabilization is used, the amplifiers may also include an offset reduction loop. Various embodiments are disclosed.

Abstract: In a signal monitoring system, a circuit includes an input terminal and an output terminal. In addition, a processor coupled to the circuit is operable for calculating a parameter indicative of an error factor of the circuit by setting a level difference between an input signal at the input terminal and an output signal at the output terminal to a predetermined level.

Abstract: When controlling the audio signal to the mute mode from an unmute mode, first, the muting circuit switches from the non-attenuating state to the attenuating state to cause the muting circuit to attenuate the audio signal by the predetermined amount of attenuation, and then, the amount of attenuation by the volume control section is set to the maximum amount of attenuation to cause the volume control section to attenuate the audio signal by the maximum amount of attenuation.

Abstract: An amplifier includes an input stage, a comparator coupled to an output of the differential input stage, and a trimming controller coupled to an output of the comparator. The input stage includes a plurality of trim devices coupled in parallel with a first input device. The trimming controller is adapted to configure the trim devices based on an output of the comparator. The trim devices may selectively control a total effective device area of the first input device. Each of the trim devices, when enabled, may add a specified area to the total effective device area of the first input device. The input stage may also include a second plurality of trim devices coupled in parallel with a second input device.

Abstract: An offset cancellation circuit for canceling an offset voltage in an amplifier is provided herein. The offset cancellation circuit includes a current source configured to provide an offset current, a switching stage comprising first and second switches, and a cascode stage. The cascode stage comprises a first cascode device configured to receive the offset current from the first switch and inject the offset current into a first differential end of the amplifier, and a second cascode device configured to receive the offset current from the second switch and inject the offset current into a second differential end of the amplifier. Offset voltages are common to many differential circuits as a result of mismatch. The injection of current by the offset cancellation circuit can reduce or eliminate an offset voltage, while the cascode stage can prevent parasitic capacitance associated with the offset cancellation circuit from creating further mismatch.

Abstract: Provided are high-resolution parametric signal restoration systems, and applications thereof. Such systems include a multi-output module and a parametric compensator. The multi-output module provides a reference gain output signal and one or more higher gain output signals based on a single input signal. The parametric compensator independently responds to functional parameters of the one or more higher gain output signals to provide a compensation error signal. The single input signal is modified based on the compensation error signal.

Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.

Abstract: In an offset canceling arrangement, an offset of an operational amplifier may be canceled even in case capacitive or resistive element is connected outside of the operational amplifier per se, and a signal may be output even during the offset canceling operation. IC chips include respective sets of plural output circuits. Each of the IC chips is provided with an offset canceling function, for which the respective sets of output circuits are grouped into plural groups. A reference signal for offset canceling is generated from a reference output circuit. One of the groups, each constituting one IC chip, is selected, and the reference signal for offset canceling generated by the group is used as a reference signal for offset canceling for the remaining group(s).

Abstract: A circuit and method for signal amplification is provided. The circuit includes an amplifier including an input amplifier that is arranged to receive an input analog signal, and to provide an input amplifier output signal by amplifying the input analog signal. The amplifier further includes a DC offset correction circuit that is arranged to determine a DC offset correction for the input amplifier each time the amplifier is powered up. The DC offset correction is performed by iteratively adjusting a DC offset of the input amplifier until the input amplifier output DC offset is zero when the input analog AC signal is zero, within a predetermined tolerance. The DC offset correction circuit is further arranged to provide the determined DC offset correction to the input amplifier during operation of the amplifier.

Abstract: An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.

Abstract: Ripple reduction loop for chopper amplifiers and chopper-stabilized amplifiers. The ripple reduction loop includes a first chopper, a first amplifier having an input coupled to an output of the first chopper, a second chopper having an input coupled to an output of the first amplifier, a second amplifier having an input coupled to an output of the second chopper, a third chopper, an output of the second amplifier having its output capacitively coupled to an input of the third chopper as the only input to the third chopper, a third amplifier coupled as an integrator having an input coupled to an output of the third chopper, an output of the integrator being coupled to combine with the output of the first amplifier as the input of the second chopper, and at least one Miller capacitor coupled between an output of the second amplifier and the input of the second amplifier. Various embodiments are disclosed.

Abstract: Provided is an operational amplifier capable of correcting an offset voltage of an element to be connected to an input terminal. The operational amplifier includes a main amplifier and an offset correction amplifier, which include input terminals connected in common. The main amplifier includes: a first transconductance amplifier for measurement; a second transconductance amplifier for offset correction; and a first capacitor connected to an input terminal of the second transconductance amplifier. The offset correction amplifier includes: a third transconductance amplifier for measurement; a fourth transconductance amplifier for offset correction; and a second capacitor connected to one input terminal of the fourth transconductance amplifier. An offset voltage adjustment circuit is provided to another input terminal of the fourth transconductance amplifier included in the offset correction amplifier.

Abstract: Various apparatuses and methods for amplifying an FM signal in a segmented linear power amplifier are disclosed herein. For example, some embodiments provide an apparatus including a signal input, a signal output, and an output driver connected between the signal input and the signal output. The output driver includes a number of driver segments connected in parallel, each having an input connected to the signal input and each having an output. The output driver also includes a number of series capacitors, each associated with one of the driver segments. The series capacitors are each connected between the output of its associated driver segment and the signal output. The output driver also includes a number of shunt capacitors, each associated with one of the driver segments having an associated series capacitor. The shunt capacitors are each connected between the output of their associated driver segment and a ground.

Abstract: A programmable system includes a programmable analog device including an operational amplifier to generate an output voltage based on input voltages at terminals of the operational amplifier. The programmable system also includes a system controller to direct the programmable analog device to reconfigure analog circuitry providing the input voltages to the operational amplifier. The reconfiguration of the analog circuitry allows the programmable analog device to implement discrete-time or continuous-time functions.

Abstract: A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.

Abstract: A multi-path amplifier can include a high frequency path, a low frequency path, and a summing node to sum an output from the high frequency path with an output from the low frequency path. The low frequency path can include a flicker noise reduction mechanism including an image band rejection mechanism. The low frequency path can include an in-phase path and a quadrature path.

Abstract: A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A power amplifier based on EER technology or ET technology extracts an amplitude-modulated component from a modulated signal as an input signal which includes the amplitude-modulated component and a phase-modulated component, and decomposes the amplitude-modulated component into two control signals whose product is proportional to the amplitude-modulated component. One of the control signals is amplified by a highly efficient amplifier, and thereafter is used to amplitude-modulate an output from an RF amplifier. The other control signal is converted by a pulse modulator into a rectangular-wave signal, which is then mixed with the phase-modulated component or the modulated signal and input to the RF amplifier.

Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Abstract: A signal processing circuit comprising a chopper amplifier in combination with a circuit or device having an acquisition period, and wherein a clock controlling the chopper amplifier is controlled such that a predetermined or known number of clock transitions occur during the acquisition period.

Abstract: A differential amplifier includes a main differential amplifier circuit that receives a pair of input signals and supplies a pair of output signals based on a difference between the input signals; and a bias control differential amplifier circuit that receives the pair of output signals, controls a control terminal of a current-limiting transistor making up the main differential amplifying circuit based on an offset voltage included in the output signals, and reduces the offset voltage.

Abstract: Calibration of gain and/or offset of an instrumentation amplifier (INA) is accomplished by coupling an appropriate number of current sources, and/or current sinks, respectively, to first and/or second transconductance stage(s) of the INA. Gain and/or offset calibration of the INA may occur when requested by a user and/or the occurrence of an event(s). A voltage reference may be used in combination with a successive approximation register analog-to-digital converter in determining which ones of the current sources and sinks are coupled to the first and/or second transconductance stage(s) of the INA for gain and/or offset calibration thereof. After the gain and/or offset calibration of the INA is completed, the selection of the constant current sources and sinks used therefore may be stored in volatile or nonvolatile memory. Parity checking of the memory may be incorporated and if a parity error is detected, an auto-calibration of the INA may be initiated.

Abstract: A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.

Abstract: A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.

Abstract: A system comprises a switched capacitor amplifier including an operational amplifier (opamp). A switching circuit comprises a first switch connected across inputs of the opamp. A second switch is connected across outputs of the opamp. An overdrive detect circuit communicates with the first and second switches and selectively shorts the inputs and the outputs of the opamp when the input voltage is greater than a first predetermined overdrive voltage or when the input voltage is less than a second predetermined overdrive voltage.

Abstract: An operational amplifier capable of suppressing power consumption and noise generation includes an offset modifier including a differential amplification circuit, and an offset memory for storing an offset voltage using a latch circuit. The differential amplification circuit includes first and second NMOS transistors connected to an input terminal, first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors, a third NMOS transistor connected to sources of the first and second NMOS transistors, a third PMOS transistor connected to a source of the second PMOS transistor, a fourth NMOS transistor connected to the third PMOS transistor, to form an output to be applied to the offset memory, and left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel.

Abstract: A semiconductor integrated circuit includes a first input terminal configured to input a first input voltage, a second input terminal configured to input a second input voltage, a differential amplifier configured to generate a differential output voltage by amplifying a differential input voltage obtained from a difference between the first input voltage input by the first input terminal and the second input voltage input by the second input terminal, a switch configured to electrically connect or cut off the first input terminal and the second input terminal, and a sample hold unit connected to a power supply which generates a reference voltage and configured to generate an offset correction voltage of the differential amplifier based on the differential output voltage and the reference voltage when the first input terminal and the second input terminal are electrically connected by the switch.

Abstract: Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths.

Abstract: A circuit and an adjusting method with a differential amplifier and with a control circuit, wherein the differential amplifier has a first amplifier transistor which for amplifying an input signal of the differential amplifier is connected in a first branch of the differential amplifier, wherein the differential amplifier has a second amplifier transistor which for amplifying the input signal of the differential amplifier is connected in a second branch of the differential amplifier, wherein the differential amplifier has at least one first series connection with a first transistor and a first semiconductor switch, the amplifier being connected parallel to the first amplifier transistor, wherein the differential amplifier has at least one second series connection with a second transistor and a second semiconductor switch, the amplifier being connected in parallel to the second amplifier transistor, and wherein the control circuit is connected to the switch inputs of the semiconductor switches to control the s

Abstract: Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers and amplifiers using the same are disclosed. The amplifiers disclosed use different combinations of chopping and auto-zero techniques. Also disclosed are amplifiers using on-off switches to affect the chopping and auto-zeroing, with unique circuits for driving the switches on the differential input to provide boot-strapped switch controls. Other features are disclosed.

Abstract: Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (ACAL) input to the mixed-signal integrated circuit. An external voltage calibration (VCAL) input may be used for auto-calibration of the mixed-signal integrated circuit to a user-supplied common-mode voltage reference. Auto-calibration of the mixed-signal integrated circuit may also be initiated upon the occurrence of any one or more of the following events: 1) detection of auto-calibration data corruption, e.g., parity checking of auto-calibration data values digitally stored in the mixed-signal integrated circuit; 2) an internal timer that causes a calibration request after a programmable timeout period, 3) change in the internal integrated circuit die temperature as determined by a temperature sensor, and 4) a change in the power supply and/or internal supply voltage(s).

Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.

Abstract: Conventional multistage amplifiers oftentimes employ trim circuits or highly matched components to combat noise and offset contributions. Having trim circuitry or highly matched components increases the overall size, cost, and power consumption, so it is desirable to have a circuit that reduces any need for better matching components or trim circuitry. Here, a multistage amplifier system is provided that generally accounts for some noise and offset contributions, reducing the need for better matching components and/or trim circuitry.

Abstract: Disclosed herein are embodiments of an auto ranging system and method for an analog signal. A microprocessor is configured to digitally control the programmable gains of an operational amplifier based on the digital output of an A/D converter which may reside on or packaged along with the microprocessor. The amplifier receives a raw analog signal from a sensor and provides an amplified analog signal to the A/D converter. The gain of the amplifier generally corresponds to some range of the sensor signal. The A/D converter outputs a number of bits representative of the input signal. A microprocessor which is configured to digitally control the programmable gains of the amplifier receives and examines the output from the A/D converter and automatically adjusts the gain of the amplifier accordingly and as needed to keep or maintain the output from the A/D converter in a predetermined range.

Abstract: In one embodiment, a circuit having a chopper stabilized amplifier and a network coupled in feedback with the chopper stabilized amplifier is disclosed. The circuit also has a plurality of switches coupled to an output of the chopper stabilized amplifier, and a summing network coupled to the plurality of switches. Ones of the plurality of switches are coupled to ones of a plurality of the summing network inputs.

Abstract: An amplifier circuit, includes: a first amplifier; a second amplifier; a first capacitor connected to the first amplifier; a second capacitor having one terminal connected to the first amplifier, another terminal connected to the second input terminal; and a first switch circuit switching a connection of the output terminal, the another terminal of the first capacitor, the first input terminal and the second input terminal, and switching supplying a reference potential supply, the first switch circuit including: a first state connecting the first input terminal to the second input terminal, connecting the output terminal to the another terminal of the first capacitor, and supplying the second input terminal with the reference potential, a second state connecting the first input terminal to the another terminal of the first capacitor and providing the output terminal and the second input terminal in an open state.

Abstract: A DC offset calibration circuit has a first resistor, a first switch, a second resistor, and a second switch. The first resistor is coupled to a first supply voltage. The first switch is coupled to the first resistor, to a first input of an amplifier, and to a first input resistor. A second end of the first input resistor is not coupled to the first supply voltage. The second resistor is coupled to a second supply voltage. The second switch is coupled to the second resistor, to a second input of the amplifier, and to a first end of a second input resistor. A second end of the second input resistor is not coupled to the second supply voltage.

Abstract: A differential amplifier that has a current supply and a differential current to voltage converter with a positive current input node, a negative current input node and a voltage output node, has offset voltage trimming. The voltage output node provides an output voltage that is proportional to the difference in current values flowing into the positive current input node and a negative current input node. A trimming circuit has a plurality of trimming control inputs, an inverting trimming output, a non-inverting trimming output and trimming inputs coupled to the current supply. Trimming resistances couple the inverting trimming output to the non-inverting trimming output. Trimming selectors, controllable by a trim code provided to the trimming control inputs, provide for selectively connecting the current supply directly to the non-inverting trimming output while selectively connecting the current supply to the inverting trimming output through a first selected group of the trimming resistances.

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: An SC amplifier arrangement and a method for measuring an input voltage are described.

Abstract: Provided are high-resolution parametric signal restoration systems, and applications thereof. Such systems include a multi-output module and a parametric compensator. The multi-output module provides a reference gain output signal and one or more higher gain output signals based on a single input signal. The parametric compensator independently responds to functional parameters of the one or more higher gain output signals to provide a compensation error signal. The single input signal is modified based on the compensation error signal.

Abstract: An audio amplifier and a method of operating such an amplifier are disclosed. The audio amplifier includes a switch disabling controller and/or an output set-point controller. The switch disabling controller is configured to disable switching of an output switch circuit or other switch circuit while an input signal represents at least relative silence. The output set-point controller is configured to bring and/or hold first and second switch nodes toward and/or at a set-point voltage while the input signal represents at least relative silence.

Abstract: A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.