Abstract: A digital phase-lock-loop circuit includes a generator that produces a horizontal rate output signal at a controlled frequency and a phase detector responsive to the output signal and to an incoming synchronizing signal. The phase detector is coupled to the generator control port via a loop filter. When the phase between the output signal and the synchronizing signal that synchronizes the phase-lock-loop circuit changes as a result of, for example, head switching in a two-head VTR that supplies the synchronizing signal, a signal representative of such phase change is produced. The phase change representative signal is fed forward to the generator, by bypassing the loop filter of the phase-lock-loop circuit. The phase change representative signal produces an immediate phase shift of the output signal such that the loop filter is not affected by the head switching.

Abstract: A phase-locked loop for generating an output signal whose phase is locked onto that of a reference signal and whose frequency is offset in respect to an integral multiple of the reference signal frequency comprises a variable-frequency oscillator the output frequency of which is adapted to be varied according to an error signal output from a phase comparator. A frequency divider divides the output frequency from the variable-frequency oscillator by a predetermined dividing ratio, and a phase modulator is supplied with the output of the frequency divider and controlled so that its phase shift amount is increased with time. The output of the phase modulator is compared, in the phase comparator, with the reference signal, the dividing ratio of the frequency divider is changed at intervals related to the offset frequency, and the phase shift amount of the phase modulator is reset at the same time.

Abstract: A digital phase shifter uses a heterodyne concept to mix a continuous wave (cw) signal with a local oscillator which is an integer multiple of the difference frequency. The difference frequency is phase-locked, and the local oscillator frequency is divided into N increments by a counter. The count of the counter is compared to a microprocessor generated phase shift value which is added to the difference frequency. The phase shifted difference frequency is then converted up to produce the phase shifted continuous wave signal.

Abstract: In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock

Abstract: A phase-lock loop circuit of a television apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive, during vertical trace, to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. During vertical trace, the control voltage varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. During vertical retrace, the frequency-to-voltage converter is responsive to the oscillator output signal for generating the control signal that maintains the free running frequency of the oscillator substantially unchanged during vertical retrace.

Abstract: A frequency controlled oscillator arranged to be fabricated in integrated circuit form including a primary frequency controlled oscillator and a secondary frequency controlled oscillator with a counter arranged to periodically count pulses of the oscillation frequency of the secondary frequency controlled oscillator and to produce a first output signal if the count is less than a predetermined value and to produce a second output signal if the count is greater than a predetermined value, and control means providing a bias control signal in dependence on the output signals of the counter for tuning the oscillation frequency of both the secondary frequency controlled oscillator and the primary frequency controlled oscillator.

Abstract: A phase locked signal generator comprises an asynchronous oscillator for producing a square wave signal, delay circuits supplied with the output square wave signal of the asynchronous oscillator, which delay circuits are provided in a plurality of stages and the output square wave signal of the asynchronous oscillator is supplied to a delay circuit provided in an initial stage, a latch circuit supplied with the output square wave signal of the asynchronous oscillator and outputs of the delay circuits, which latch circuit simultaneously latches the outputs of the delay circuits responsive to a reference signal applied to the latch circuit, and a gate circuit for producing an input or an output of one or a plurality of delay circuits each having an input and an output of mutually opposite polarities at a time when the reference signal is applied to the latch circuit, as an output square wave signal of the phase locked signal generator.

Abstract: Apparatus for controlling the frequency of a voltage controlled oscillator in response to a horizontal synchronizing signal of a video signal comprises a frequency divider for dividing the frequency of the output of the oscillator and a control for phase-comparing the output of the frequency divider with the horizontal synchronizing signal and controlling the frequency of the oscillator in response to the result of the phase comparison. The control comprises a circuit for forming a control signal by using a first pulse signal having a first signal level and a second pulse signal having a second signal level in response to the phase difference between the horizontal synchronizing signal and the output of the oscillator. A correcting signal is added to the control signal when the phase of the horizontal synchronizing signal is beyond a predetermined range.

Abstract: A signal generator circuit for a television receiver employed in a videotex or CAPTAIN system comprises a reference signal oscillator for producing a reference signal and a synchronizing signal generator for generating a horizontal synchronization signal synchronized with the reference signal. A frequency divider is responsive to the reference signal for producing a color sub-carrier signal. A phase-locked loop is responsive to the sub-carrier signal and includes a voltage-controlled oscillator. The voltage-controlled oscillator produces an output signal synchronized with the sub-carrier signal and having a series of rising edges. A rising edge of the sub-carrier signal periodically coincides with a rising edge of the signal from the voltage-controlled oscillator.

Abstract: A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nf.sub.H (n is an integer), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nf.sub.H, a difference between the pulse widths of the clocks resulting from counting down the first and second clocks to 1/M and the frequency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchronized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.

Abstract: A video display apparatus having automatic frequency control circuitry for adjusting the frequency of a horizontal oscillator to provide oscillator synchronization with incoming horizontal synchronizing pulses incorporates an interface circuit for controlling the horizontal oscillator frequency response to frequency control output voltage. The interface circuit incorporates a two-transistor switch which provides a current path for charging the horizontal oscillator timing capacitor during a portion of the horizontal interval and a current path for bypassing the horizontal oscillator timing capacitor during another portion of the horizontal interval. The amplitude of the frequency control output voltage will determine the relative length of time that each of the transistors is conducting in order to provide a net increase or decrease rate in the charging of the oscillator capacitor, which in turn adjusts the oscillator operating frequency.

Abstract: Phase shifting means are provided for altering the phase relationship between a vertical sync signal the resulting vertical retrace and video information in a video display environment. The video display is adjustably repositioned both up and down on the display raster by means of phase adjustment circuitry. A single loop having first and second delay circuits provides phase shifting. The output vertical sync signal lags or leads in phase the originally received vertical sync signal by the difference between the first delay and second delay values. The first delay is interposed between the incoming vertical sync signal and the phase locked loop system. The second delay circuit is interposed in the loop between the output vertical sync signal and the phase detector for locking the output vertical sync signal in phase with the delayed original sync signal.

Abstract: Non-inverting amplifier, with bandpass filter in regenerative feedback path, forms color reference oscillator in a color TV receiver. Phase shift circuit, responsive to an oscillator output, supplies signals to a first phase shifted signal amplifier, which shares a load with the non-inverting amplifier, and is subject to control by complementary outputs of a phase comparator functioning to compare the phase of an oscillator output with the phase of incoming color synchronizing bursts. A voltage comparator, responsive to the respective phase comparator outputs, is periodically enabled by field rate keying pulses. The voltage comparator output controls the charging or discharging of a capacitor during the keying intervals.

Abstract: A synchronization circuit for a free-running oscillator, in which a multi-tapped delay line provides delayed outputs incrementally spaced throughout the period and at the same frequency as the oscillator. That delayed signal closest in time to a reference signal is selected as the output signal, synchronized to the reference signal.

Abstract: A voltage controlled oscillator comprises a tank circuit for determining an oscillation frequency, a first circuit for delaying the signal having the oscillation frequency, a second circuit for advancing the signal having the oscillation frequency, the first and second circuit being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit of the series connection, a first gain controlled amplifier amplifying the output from the first circuit, a second gain controlled amplifier amplifying the output from the second circuit, an adder for adding outputs from the first and second gain controlled amplifiers, a control circuit controlling the gains of the first and second gain controlled amplifiers, and a feed-back circuit for feeding the output of the adder to the tank circuit.

Abstract: A color subcarrier generator for PAL uses a one-quarter horizontal frequency signal from a sync generator to sample the subcarrier signal. The sampled signal is phase and frequency compared with a 25 Hz (one-half vertical frequency) signal from the same sync generator to control the frequency of the subcarrier signal. Thus the required 25 Hz PAL offset is obtained. The one-quarter horizontal frequency sampling signal can also be used in NTSC and SECAM subcarrier generators.

Abstract: A line synchronizing circuit for a picture display device comprising a control loop for controlling a line oscillator. An incoming line synchronizing signal and also a reference signal generated by the oscillator are applied to a phase discriminator circuit. The output signal of the phase discriminator circuit is smoothed to obtain the control voltage for the oscillator. Pull-in of the control loop is established by means of a coincidence detector. Prior to that, an edge of the reference signal is compared with the center instant of a line synchronizing pulse. When the control loop is in the pulled-in state, it is changed by the coincidence detector to compare the leading edge of a line synchronizing pulse to the center instant between the said edge of the reference signal and its first preceding edge.

Abstract: A line synchronizing circuit for a picture display device comprising a voltage-controlled oscillator for generating a signal whose frequency is higher than the line frequency, a frequency dividing circuit for dividing the frequency of the oscillator signals and a phase comparison stage for generating a control voltage in dependence on the phase deviation between the signals applied thereto, more specifically a received line synchronizing signal and a locally generated reference signal. The elements of the line phase control loop, are part of an integrated circuit which functions as a frequency synthesizing circuit. The reference-frequency dividing circuit incorporated in the integrated circuit is programmed to operate with a constant divisor.

Abstract: To adjust the free running frequency of a voltage controlled oscillator so that it is close enough to a target frequency for a phase locked loop to lock the frequency, a reference signal is derived from a stable external source. A derived signal is generated from the oscillator. The derived signal and the reference signal are applied to a comparison circuit which examines the relationship of a specific edge of the reference signal at times determined by the signal derived from the oscillator. If the oscillator is within its proper frequency range, the edge of the reference signal will have a certain relationship to the times determined by the derived signal. If this relationship is found to be improper, correction signals are applied to the oscillator. In the preferred embodiment, this occurs in a television receiver where the reference signal is based on a 3.58 megahertz signal. The examination which is made takes an output from a counter which divides by 455, specifically, the 160 count.

Abstract: The output of a phase comparator in the PLL of the data reproduction unit is filtered to remove low frequency components which may be due to record eccentricity. The filtered output is then rectified and integrated, with the level of the integrated signal determining whether the PLL should be operated in a broad or narrow band state.

Abstract: A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals.

Abstract: A genlock circuit has a reference signal that is frequency divided to provide an internal vertical sync signal. When an external sync signal is present, the division ratio is temporarily changed to provide a slow locking of the internal sync signal to the external sync signal. This avoids picture disturbances. The circuit can be used in a camera control unit and camera heads.

Abstract: A decoder includes an oscillator supplying a decoding signal to the control input of an RF modulator for decoding a sine wave encoded television signal. The decoding signal developed by the oscillator is randomly phase locked in either of two states with the output of a horizontal sync separator operated in response to the detected output of the RF modulator. In the first phase locked state, the decoding signal is in antiphase relationship with the encoding modulation resulting in a properly decoded baseband video signal. In the second phase locked state, the decoding signal is in phase alignment with the encoding modulation so as to constructively combine therewith. The second phase locked state is detected and broken each time it is assumed allowing the decoder to eventually assume the first phase locked state wherein a properly decoded video signal is produced.

Abstract: A phase sychronizing circuit for a device which reproduces digital data has a phase locked loop including a first phase comparison circuit, a voltage controlled oscillator (VCO) producing an output the frequency of which is controlled by the first phase comparison circuit, and a first frequency divider to divide the output frequency of the VCO. The phase synchronizing circuit further includes second frequency divider for dividing the output frequency of the VCO, a second phase comparison circuit for comparing the phase of a first clock signal from the first frequency divider, with that of a second clock signal from the second frequency divider and a circuit for controlling the frequency dividing ratio of the first frequency dividing circuit according to the phase difference between the first and second clock signals in such a way that the frequency dividing ratio becomes one of 1/N, 1/(N+1) and 1/{(N+(N+1))/2} wherein N is a positive integer.

Abstract: Color reference oscillator in a color television receiver comprises a non-inverting amplifier, with positive feedback from its output conveyed via a crystal filter to its input. A quadrature phase shift network, coupled to the filter output, develops phase shifted signals which are matrixed with signals derived directly from the non-inverting amplifier to form resultant signals with a phase intermediate the phases of the matrix inputs. Control voltage outputs of a phase comparator, responsive to oscillator signals and to received synchronizing bursts, determine the magnitude and polarity of the output of a controlled amplifier which has at its input the resultant signals produced by said matrixing. The controlled amplifier output, and the output of an inverting amplifier also responsive to said resultant signals, share the load resistor of the non-inverting amplifier.

Abstract: Color reference oscillator comprises a non-inverting amplifier, with positive feedback via a crystal filter linking its output and input. A quadrature phase shift network, coupled to the filter output, delivers phase shifted signals to a pair of independently controlled amplifiers. One of the controlled amplifiers is responsive to control voltage outputs of a burst-responsive phase detector so as to inject phase shifted signals into the oscillator loop, as and when required, to effect synchronization of oscillator with burst component of incoming color television signal. The second of the controlled amplifiers is responsive to a reference DC voltage and to a manually adjustable DC control voltage, and develops a phase shifted signal output, of a magnitude and polarity dependent upon the magnitude and sense of the difference, if any, between the respective DC voltages, for combination with the non-inverting amplifier's output.

Abstract: A sampling PLL circuit features a frequency sweep caused by an offset voltage applied to an integrator to avoid false lock ups. At one end of the frequency range the polarity of the offset signal can be reversed. The error voltage can be sampled during a television vertical or horizontal blanking period. Once proper lock up is achieved, the offset signal can be removed.

Abstract: The present invention allows code signals from a video signal to be read even though the signal is being reproduced at non-standard speed, a reference oscillator and programmable frequency divider are utilized with a time width detector and the frequency dividing ratio of the programmable frequency divider is controlled so as to assure that the video code signal can be detected even at non-standard speeds.

Abstract: A multiburst test signal generator and a method for using the generator's test signal to determine the frequency response characteristics of television video circuits with a high degree of accuracy is described. One of the burst frequencies is continuously enabled and made variable and the other burst frequencies are disabled. The resulting continuous sine wave is applied to the circuit being tested, its frequency is varied, and the output of the circuit being tested is monitored with a conventional frequency counter.

Abstract: A horizontal deflection turn-on circuit operates in the absence of trigger pulse normally derived by an AFPC loop. Under normal operation, the AFPC loop generates the trigger pulses based on a synchronized phase relationship with sampled flyback pulses. During receiver start-up, the flyback pulses are not present and no trigger pulses are generated. The turn on circuit provides auxiliary pulses which occur later in time than the normal occurrence of the trigger pulses. Means are provided for applying the auxiliary pulses to the horizontal deflection circuit only in the absence of normal trigger pulses.

Abstract: An automatic frequency control (AFC) circuit is disclosed which comprises an oscillating circuit for generating repetitive pulses, a generator for generating comparison signals having a slope portion in response to the repetitive pulses, and a phase comparison circuit which compares the comparison signals, and synchronous (sync) signals and based on the comparison supplies control signals to the oscillating circuit. The AF circuit further comprises a limiting circuit connected between the comparison signal generator and the phase comparison circuit which limits the maximum and minimum levels of the comparison signals to predetermined levels, and thereby predeterminedly limits the control range of the AFC circuit.

Abstract: A chrominance subcarrier regeneration network having high stability, the network being adapted for use in a video tape recorder and including a phase detector for comparing the phase of a gated subcarrier burst of a video signal with that of a subcarrier regenerated signal to develop an error signal; a voltage controlled oscillator driven by the error signal to develop a corrected signal at a frequency substantially below that of the subcarrier burst; and a crystal oscillator, mixer and filter for translating the frequency and filtering the corrected signal to develop the regenerated signal.

Abstract: A VCO control circuit features a first exclusive-OR gate to the inputs of which are applied signals derived from the VCO to provide an output signal that has a 90.degree. phase shift with respect to a reference signal. A second exclusive-OR gate serves as a phase detector for the output and reference signals and provides, after filtering, a frequency control voltage for the VCO. The control voltage has about the same amplitude regardless of the presence or absence of the reference signal.

Abstract: A television horizontal deflection synchronizing system uses two phase-lock loops. A horizontal oscillator operating at a frequency greater than the horizontal frequency is counted and a bilevel signal near the horizontal frequency is generated. A first phase-lock loop having a relatively long time constant controls the oscillator to maintain the bilevel signal in frequency and phase synchronism with horizontal synchronizing signals. In order to compensate for load-dependent variations in the delay of the horizontal deflection stage, a second phase-lock loop is used. The second phase-lock loop includes a phase detector, one input of which is coupled to an output of the first phase-lock loop and a second input of which is coupled to the deflection circuit for responding to the retrace pulse for enabling the phase detector to produce a current of a first polarity when the bilevel signal has a first value and a current of a second polarity when the bilevel signal has a second value.

Abstract: A variable-frequency oscillator includes an oscillator portion coupled to a phase shifter and a controllable gain device for controlling the amount of phase-shifted signal reintroduced to the oscillator. The oscillator includes first and second transistors coupled at their emitters to a current source. The emitters of third and fourth transistors are coupled to bases of the first and second transistors, respectively. The base of the third transistor is coupled to a voltage source, and the base of the fourth transistor couples to the collector of the first to form a regenerative loop capable of oscillation. A parallel-resonant circuit is coupled between the collector of the first transistor and the voltage source for establishing a frequency-sensitive phase characteristic in the loop by which the quiescent frequency is determined. The phase shifter is coupled to a point on the regenerative loop.

Abstract: A sample and hold detector arrangement suitable for construction in integrated circuit form as an automatic chroma gain control detector, or a color oscillator AFPC detector, or the like. A wide bandwidth analog multiplier circuit is supplied with an intermittent reference signal and a second signal, the phase or amplitude of which is to be sampled. In a preferred embodiment, the reference signal corresponds to the burst component of a composite color television signal and the second signal corresponds to a locally generated color subcarrier signal. The multiplier provides oppositely phased output signals which are coupled to first and second sample and hold circuits. Each sample and hold circuit is keyed to concurrently sample the respective multiplier outputs for the same sampling interval, and each provides substantially symmetrical bidirectional conduction to associated filter capacitors during the sampling interval and a high holding impedance during the remainder of each cycle.

Abstract: A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.

Abstract: A television horizontal AFPC loop includes a filter, the time constant of which can be switched at the vertical rate for improved operation from standard broadcast signals and from video tape recorders. A transistor switch introduces a voltage offset which perturbs the AFPC filtered oscillator control voltage. The perturbation is reduced by introducing a second offset voltage for reducing the perturbation and improving the synchronization of the oscillator with the synchronizing signals.

Abstract: A clock pulse generator which has the frequency of its output automatically controlled by comparison of the generated clock pulses with an external reference signal comprises an input for receiving the reference signal, a voltage controlled oscillator for generating the clock pulses, a counter for frequency-dividing the clock pulses to obtain a comparing signal having substantially the same frequency as the external reference signal, a phase comparator for comparing the phase of the comparing signal with the phase of the external reference signal and providing the control voltage for the oscillator in response to a detected phase difference therebetween, and an inhibiting circuit for inhibiting the control voltage whenever the phase of the external reference signal is outside a predetermined range with respect to the comparing signal.

Abstract: A television video vertical sync detector which produces a vertical sync pulse. This detector includes a separating circuit for the production of horizontal sync pulses, equalizing pulses and vertical sync pulses, and a phase control oscillator. The phase control oscillator includes a phase comparator low pass filter, a voltage control oscillator for generating clock pulses, a division circuit and a delay circuit. A sampling circuit is used to generate the final vertical sync pulse.

Abstract: An automatic frequency control circuit comprising two switching transistors with the emitter-collector paths thereof connected in series with each other between a power source and a reference voltage source, a horizontal synchronizing signal being commonly coupled to the bases of the switching transistors, an integrating circuit having an input terminal receiving a horizontal pulse signal and an output terminal connected to the emitter-collector juncture between said two switching transistors, a smoothing circuit to convert the output voltage of said integrating circuit into a d-c voltage, and a voltage controlled oscillator to produce a frequency output in accordance with the d-c output voltage of the smoothing circuit, the output of said oscillator being fed back to the input terminal of said integrating circuit.

Abstract: A horizontal oscillator phase-lock loop arrangement compares synchronizing pulses with recurrent ramp signals derived from the horizontal retrace pulses to control the deflection frequency. The ramp signals are generated by a capacitor charged during the retrace interval through a diode from a reference voltage established by a clamp.

Abstract: A television synchronizing signal generator includes a synchronizing signal separator circuit for separating a synchronizing signal from a video signal, an oscillator the oscillatory frequency of which is controllable, a phase discriminator for discriminating outputs of the synchronizing signal separator circuit and the oscillator, a memory circuit for memorizing an output of the phase discriminator, a switching circuit for applying alternatively the output of the phase discriminator and the output of the memory as a control signal to the oscillator to control the oscillatory frequency thereof, and an input state detector for detecting the input amplitude and noise state of the video signal such that the switching action of the switching circuit is controlled in accordance with the output of the input state detector. With such a generator, a stable picture can be obtained in a television receiver, even although the received video signal is temporarily abnormal.

Abstract: A method and apparatus is disclosed for sampling an analog information signal having an associated carrier signal at precise phase positions with respect to said carrier, which involves sampling the information signal at predetermined phase positions relative to the carrier signal using a phase locked loop to maintain the sampling positions reasonably close to the predetermined phase positions and thereafter examining the discrete samples and generating an error signal that indicates any phase deviation and adjusting the sampling so that the error signal approaches zero and the samples are taken at said precise phase positions.

Abstract: A horizontal AFC circuit comprising a phase detector circuit supplied with a horizontal synchronizing signal separated from a television video signal and with a comparison signal and carrying out phase comparison, a filter circuit for filtering the output of the phase detector circuit, a horizontal oscillator circuit supplied with the output of the filter circuit and oscillating with an oscillation frequency controlled thereby, a horizontal deflection circuit for forming the output signal of the horizontal oscillator circuit into a horizontal deflection pulse, a wave shaping circuit operating upon being supplied with the output pulse of the horizontal deflection circuit to wave shape this output pulse and to supply the resulting output signal thereof as said comparison signal to the phase detector circuit, means for supplying a control pulse of a pulse width corresponding to a vertical blanking period of the television video signal, and loop gain control means supplied with the control pulse and operating to

Abstract: A method and apparatus for synchronization of a digital divider chain with a low frequency reference pulse train is embodied in the form of all digital circuit apparatus suitable for fabrication by state of the art high density packaging techniques such as Large Scale Integration (LSI) or Multi-chip Hybrid Packaging (MHP). Each individual substage of the divider chain is reset to its ZERO condition by a circuit including first and second flip-flops which receives inputs from the master oscillator clock driving the divider chain and from the source of the low frequency reference pulse train.

Abstract: A frequency scanning automatic phase control includes a phase detector, a local oscillator and an APC filter. A coincidence detector includes an AND gate responsive to the horizontal retrace and reference synchronizing pulses. A lock detector also responsive to the retrace and reference sync pulses produces an output signal when a predetermined interval of non-coincidence has existed. An AND gate responsive to both the lock detector and coincidence detector gates a current sink which unbalances the phase detector producing a ramp-like error voltage across the APC filter. A threshold detector coupled to the APC filter activates a discharge circuit also coupled to the filter when the filter voltage exceeds the threshold. The oscillator responds to the variations of error voltage and changes frequency accordingly. Once coincidence occurs frequency variation ceases and is resumed only if non-coincidence returns.

Abstract: Synchronizing circuit arrangement, for example for line synchronization in a television receiver, including digital means, the frequency of the oscillator being twice that of the signal to be synchronized. A frequency divider circuit, for example a master-slave flipflop, produces two output signals one of which serves as a reference signal for the phase discriminator whilest the other is applied together with the input signal of the circuit to a coincidence stage.

Abstract: Switching the time constant of a filter in the APC-loop of a color television receiver is done by a keyed transistor switch so that the circuit is suitable to be formed as an integrated circuit.

Abstract: A vertical deflection circuit used in television receivers, comprising a free-running oscillator capable of synchronous oscillation triggered by a vertical synchronizing signal separated from a composite synchronizing signal is disclosed. The vertical deflection circuit has a switch means which operates under synchronous control by the vertical synchronizing pulse and prevents the application of a vertical trigger signal to the free-running oscillator at least for the period from the time at which the free-running oscillator has been triggered to the time corresponding to the end of the vertical synchronizing pulse period of the composite synchronizing signal.