Abstract: Disclosed in the present application are a method for reducing SGLTE coupling de-sense and a mobile terminal, the method including: filtering out an LTE network frequency band in a signal transmitted by a signal transmission end of a GSM; and filtering out a network frequency band in a signal of a signal reception end accessing the GSM other than a GSM network frequency band. Employing the present application may eliminate mutual interference between a GSM signal and an LTE signal due to the GSM network frequency band and the LTE network frequency band getting too close to each other, which greatly alleviates SGLTE mobile terminal coupling de-sense situation.

Abstract: In 5G and 6G, each message element of a message is transmitted with a constant amplitude level. Disclosed herein is a more resource-efficient modulation scheme in which each message element is modulated to two of the amplitude levels, with a first amplitude level in the first half of a message element, and a second amplitude level in the second half. The information density of the message is thereby doubled, saving time and resources. The transition between the first and second amplitude levels can be abrupt, as in a square wave, or ramped, as in a linear ramp function. The changing amplitude may cause a frequency shift; however the transmitter can calculate that shift and apply a frequency correction to each message element to compensate. The changing amplitude can also deposit energy in adjacent subcarriers; however the receiver can calculate that energy and subtract it from the adjacent subcarriers before demodulating.

Abstract: The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.

Abstract: Example systems and processes control transition of an electric motor from open-loop operation to closed-loop operation by detecting zero-crossing (ZC) locations of the back-electromotive force (BEMF). The rotor angle of the electric motor is changed, e.g., by changing acceleration of the electric motor to correct a phase difference based on the detected ZC locations and an open-loop profile of the electric motor. Detected ZC locations may be used to identify ZC-detected-based commutation points, and each detected ZC location may be used to update a next commutation point. During the control process the open-loop profile is updated. Transition may occur when a set number of ZC-detection-based commutation points are sufficiently aligned with corresponding updated commutation points, or such alignment is maintained for at least one electrical cycle.

Abstract: To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.

Abstract: An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.

Abstract: System and methods implemented in a coherent receiver having a pair of Avalanche Photodiodes (APD) include adjusting one or more of a reverse bias voltage (VAPD) on a P-path (VAPDP) and on an N-path (VAPDN) responsive to an output (PIN,CM) that indicates electrical power of an AC common-mode input signal; adjusting a Transimpedance Amplifier (TIA) common-mode AC response, AdjCM_AC_Response, responsive to an output (POUT,CM) that indicates electrical power of an AC common-mode output signal; and/or adjusting one or more of VAPDP and VAPDN responsive to received signal Signal-to-Noise Ratio (SNR).

Abstract: A half rate bang—bang phase detector for high-speed Analog Clock and Data Recovery (CDR) is disclosed. In some embodiments, the half rate bang—bang phase detector includes a first set of flip flops. Each of the first set of flip flops is configured to receive an input data sampled at each of a four phases of a Voltage Controlled Oscillator (VCO) clock. The half rate bang—bang phase detector includes a first set of logic gates configured to generate a set of four exclusive—OR (XOR) outputs. The half rate bang—bang phase detector includes a second set of flip flops configured to generate a set of clean XOR outputs. The half rate bang—bang phase detector includes a second set of logic gates configured to generate a set of final outputs based on the set of clean XOR outputs.

Abstract: A memory system includes a plurality of memory devices coupled to each other through a channel and each including a test clock input pad suitable for receiving an external test clock, a clock generation circuit suitable for generating an input clock and an output clock based on a reference clock and the external test clock in response to a reset signal, a test data processing circuit suitable for parallelizing test data so as to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock, and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock.

Abstract: A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

Abstract: A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

Abstract: A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: A frequency synthesiser arrangement is arranged to receive a clock input signal and provide an output signal. The frequency synthesiser arrangement comprises: a frequency divider arranged to divide the output signal by a variable number N and output a feedback signal; a phase detector arranged to detect a phase difference between the feedback signal and the clock input signal; a phase alignment circuit portion arranged to determine an overlap of the clock input signal and the feedback signal; and a voltage controlled oscillator which is arranged to receive either a first input derived from the phase detector or a second input from an external reference voltage and to provide the output signal. The phase alignment circuit portion is arranged to provide a control output which determines whether the voltage controlled oscillator receives the first or second input.

Abstract: A magnetic field sensor includes a phase-locked loop to receive a measured magnetic field signal formed from sensing element output signals of a plurality of magnetic field sensing elements in response to a magnetic field. The phase-locked loop is configured to generate an angle signal having a value indicative of the angle of the magnetic field. Associated methods are also described.

Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Abstract: A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

Abstract: Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

Abstract: A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

Abstract: A method is provided for operating an electrical device (14) which has an operating mode and a sleep mode, in which method an oscillator apparatus (20) provides a first analog signal (f(t)) with a first frequency and second analog signal (f?(t)) with a second frequency, wherein the second analog signal (f?(t)) is different from the first analog signal (f(t)), a comparator apparatus (28) compares the first analog signal (f(t)) and/or second analog signal (f?(t)) with at least one reference value (Uref) or a reference value range, and an interrupt signal for transferring from the sleep mode into the operating mode is produced if a certain comparison result is detected.

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

Abstract: A tunable voltage oscillator expands a voltage oscillator's tuning range and compensate for any frequency spread present in the voltage oscillator. The tunable voltage oscillator multiplies a frequency of a periodic signal generated by the voltage oscillator by a fractional number. This fractional number is determined by a desired frequency range and an actual frequency range of the voltage oscillator. As such, the frequency range of the output periodic signal is tuned into the desired range. The voltage oscillator can include a programmable inductor of which the inductance can be adjusted thereby to expand the frequency range by increasing the quality factor in the low frequency range.

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may report a phase-noise compensation reference signal (PCRS) configuration to a base station to enable per-UE PCRS signaling. For example, a UE may operate in a wireless communications system using carrier frequencies greater than 6 GHz, which may be affected by phase noise. The UE may accordingly determine a PCRS configuration based on a capability to receive signals. The PCRS configuration may include a resource mapping for one or more PCRS, a number of PCRS ports used for PCRS, a multiplexing scheme for one or more PCRS ports, or the UE's phase noise estimation capability. The UE may then transmit a reporting message including the PCRS configuration to a base station. The base station may use the PCRS configuration for PCRS transmissions to the UE.

Abstract: An integrated circuit. The integrated circuit comprises an analog transmit chain, an analog receive chain, a processor coupled to the analog transmit and receive chains, and a non-transitory storage coupled to the processor and storing executable code. When executed by the processor, the executable code causes the processor to cause a portion of a radio frequency (RF) signal to be transmitted by the analog transmit chain, to determine a first direct current (DC) voltage of a baseband signal provided by the analog receive chain, to cause a DC voltage offset to be input into the analog transmit chain, to determine a second DC voltage of another baseband signal provided by the analog receive chain, to determine a DC voltage offset compensation based on the first and second DC voltages and the DC voltage offset, and to cause the DC voltage offset compensation to be used to transmit signals.

Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

Abstract: A method for determining the functionality of a switchable reception amplifier of a radar system with a transmitting unit, a receiving unit and a voltage-controlled oscillator, wherein, before the radar system is started up, calibration is carried out in order to compensate for a frequency deviation of the frequency emitted by the oscillator. The invention provides for at least one calibration cycle to be run with at least one first signal at a first frequency and one second signal at a second frequency during calibration of the oscillator, wherein the first signal and the second signal are transmitted by the transmitting unit and are received by the receiving unit, wherein the reception amplifier is switched with a switching sequence, which results in amplitude modulation of the first and second signals, and the amplitude modulation is used to determine the functionality of the reception amplifier.

Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

Abstract: A frequency modulation receiver includes a frequency modulation demodulation circuit that generates a first signal, and a phase locked loop (PLL) circuit coupled to the frequency modulation demodulation circuit to receive the first signal. The PLL circuit includes: a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal; a phase detector, coupled to the VCO, generating a phase signal according to the oscillation output signal and the first signal; and a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO.

Abstract: A clock calibration method of a navigation system is provided. The clock calibration method includes: entering a calibration mode; sequentially issuing, by a host, a count start signal and a count end signal separated by a time interval; counting a local oscillation frequency of a local oscillator when a navigation device receives the count start signal from the host; disabling the counting when the navigation device receives the count end signal from the host and generating a current count; generating a calibration signal according to the current count and a predetermined count corresponding to the time interval; and calibrating the local oscillation frequency of the local oscillator according to the calibration signal.

Abstract: Methods and systems are described for communication of data over a communications bus at high speed and high pin efficiency, with good resilience to common mode and other noise. Pin efficiencies of 100% may be achieved even for bus widths of four or fewer wires. Information to be transmitted is encoded as words of a vector signaling code, each word comprising multiple values transmitted as a group over the communications bus. Subsets of the vector signaling code have distinct group characteristics, which are discernable on transmission and are used to facilitate decoding on reception.

Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

Abstract: There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

Abstract: A method includes modulating a laser that is coupled to a fiber; modulating the laser with a member selected from the group consisting of low frequency thermal modulation or bias modulation to broaden a laser linewidth, increase an SBS threshold and reduce an IIN; and modulating the laser with a predistorting modulation selected from the group consisting of phase modulation or amplitude modulation, the predistorting modulation being of equal magnitude but opposite phase as that produced in at least one member selected from the group consisting of the laser or the fiber as a result of the low frequency thermal modulation or bias modulation.

Abstract: A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal.

Abstract: Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.

Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

Abstract: A power switch control circuit is provided for power management in one-wire application. The circuit comprises a controllable switch coupled between an input node and an internal power node. A comparator is utilized for power loss sensing to close the switch when necessary to minimize the power loss while the input is low or floating. A watchdog circuit is incorporated within the control circuit to pull down the input node periodically to detect small leakage current when the input node is floating.

Abstract: A power generating device (2, 3) for supplying power to a power system (37). The power generating device includes a first component (87) for generating a first signal representing a frequency of a voltage on the power system, a power converter (90) for generating an output voltage, a second component (82) responsive to the first signal and to a second signal representing the output voltage, the second component producing an error signal representing a phase angle difference between the first and second signals, and the error signal being an input to the power converter for controlling the power converter to maintain the phase angle difference between the output voltage and the first signal.

Abstract: Circuitry for providing an oscillating output signal. This circuitry includes a transconductance circuit having a first input, a second input, an output. The transconductance also includes a first transistor, a second transistor, and chopping circuitry. The chopping circuitry is for alternatively connecting, in a first clock cycle phase, a first node to a first terminal of the first transistor and a second node to a first terminal of the second transistor and, in a second clock cycle phase, following the first clock cycle phase, the first node to the first terminal of the second transistor and the second node to a first terminal of the first transistor. An oscillator circuit is also included and coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit.

Abstract: A clamping circuit clamps a serial data signal between a first high voltage level and a first low voltage level to yield a clamped serial data signal. A first comparator circuit compares the clamped serial data signal to a second high voltage level less than the first high voltage level to yield a high output equal to one just when a voltage of the clamped serial data signal is greater than the second high voltage level. A second comparator circuit compares the clamped serial data signal to second low voltage level greater than the first low voltage level to yield a low output equal to one just when the voltage of the clamped serial data signal is greater than the second low voltage level. An edge circuit detects an edge of the serial data signal from the high output and the low output.

Abstract: Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit is coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement.