Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.

Abstract: Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.

Abstract: A method for compensating for noise in a secondary radar system is described. The method includes, using a first transceiver, transmitting, in temporally overlapping manner, a first transmission signal containing a first interfering component and a second transmission signal containing a second interfering component, and compensating for at least one of phase shifts or frequency shifts resulting from the first and second interfering components by evaluation of the first and second transmission signals.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: An embodiment circuit comprises first and second output nodes with an inductor arranged therebetween, and first and second switches coupled to opposed ends of the inductor. The switches are switchable between non-conductive and conductive states to control current flow through the inductor and produce first and second output voltages. The current intensity through the inductor is compared with at least one reference value. Switching control circuitry is coupled with the first and second switches, the first and second output nodes, and current sensing circuitry, which is configured to control the switching frequency of the first and second switches as a function of the output voltages and a comparison at the current sensing circuitry. The switching control circuitry is configured to apply FLL-FFWD processing to produce the reference values as a function of a timing signal, targeting maintaining a constant target value for the converter switching frequency.

Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

Abstract: An injection control device includes: a boost controller performing a boost switching control of a boost switch to charge a boost capacitor and supplying a boost power from a battery power supply; a boost voltage monitor monitoring the boost voltage; and a boost monitor timing controller setting a section from a predetermined time after an on-edge of the boost switch to an off-edge timing in a section monitor mode as a boost monitor section. The boost controller stops boosting by stopping the boost switching control when the boost voltage is equal to or higher than a boost stop threshold value in the boost monitor section.

Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: Phase noise compensation can be performed in a primary radar system, such as in transceiver hardware. A first reflected reception signal can be received, corresponding to a reflection of a first transmission signal from an object, and a first measurement signal can be generated using mixing or correlation of the first reflected reception signal and the first transmission signal. A second measurement signal can be similarly generated from a second transmission signal and a second reflected reception signal. The first and second measurement signals include respective components including complex conjugate representations of each other. The components correspond to interfering components associated with phase noise, and such respective components can cancel each other to suppress phase noise.

Abstract: A PLL circuit includes: a charge pump; a voltage-controlled oscillator including an oscillation portion; and a voltage-converting circuit configured to convert a voltage from the charge pump and apply the converted voltage to the voltage-controlled oscillator. The power supply range supplied to the voltage-converting circuit is larger than the power supply range supplied to the oscillation portion of the voltage-controlled oscillator.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: Methods and apparatus for quickly changing line rates in PCIe analyzers without resetting the receivers. One example circuit for multi-rate reception generally includes: a receiver having a data input, a data output, and a clock input configured to receive a clock signal from a clock generator, the receiver being configured to switch between receiving data at a first data rate and at least one second data rate and to sample data according to the first data rate, wherein the first data rate is higher than the at least one second data rate; a phase detector having an input coupled to the data output of the receiver; and a filter having an input coupled to an output of the phase detector and having an output configured to effectively control a phase of the sampling by the receiver when the data is at the at least one second data rate.

Abstract: A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.

Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

Abstract: A system for driving a microelectromechanical system (MEMS) oscillating structure includes a phase error detector configured to generate a phase error signal based on measured event times and expected event times of the MEMS oscillating structure oscillating about a rotation axis; a disturbance event detector configured to detect a disturbance event based on the phase error signal and a disturbance threshold value; and a phase frequency detector (PFD) and correction circuit configured to, in response to the detected disturbance event, monitor for a plurality of measured crossing events of the MEMS oscillating structure oscillating about the rotation axis, generate a first compensation signal based on at least a first measured crossing event and a second measured crossing event to correct a frequency of the MEMS oscillating structure, and generate a second compensation signal based on a third measured crossing event to correct a phase of the MEMS oscillating structure.

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

Abstract: A method and apparatus for modulating/demodulating an FSK signal capable of overcoming a trade-off relationship between a modulation index and a spectral efficiency are disclosed. An apparatus for modulating/demodulating a frequency deviation keying (FSK) signal includes a channel selection-modulator, a phase locked loop, and an output unit. The channel selection-modulator modulates an FSK signal by setting a frequency channel to be used. The phase locked loop generates a desired output frequency ‘fout’ compared to a reference frequency ‘fREF’ by adjusting a frequency division ratio (N+n) with respect to a frequency of the modulated FSK signal. The output unit amplifies the FSK signal having the generated output frequency ‘fout’ and radiating the amplified FSK signal through an antenna. Here, each of the frequency channels is divided into two or more tones, and different frequency channels are allocated between the tones divided into two or more tones.

Abstract: Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Abstract: Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.

Abstract: An oscillation circuit is provided. The oscillation circuit includes a first inverting circuit. The first inverting circuit comprises a first transistor of a first type and a second transistor of the first type, wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and a source terminal of the first transistor is connected to a drain terminal of the second transistor.

Abstract: Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal.

Abstract: Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

Abstract: A device includes a microwave generator configured to generate a microwave having a bandwidth, an output unit, a directional coupler and a measurer. The microwave generator generates a microwave a power of which is pulse-modulated to be a High level and a Low level. A set carrier pitch is set to satisfy a preset condition. The preset condition includes a condition that a value obtained by dividing a set pulse frequency by the set carrier pitch or a value obtained by dividing the set carrier pitch by the set pulse frequency is not an integer and a condition that an ON-time of the High level is equal to or larger than 50%. The microwave generator averages a first High measurement value and a first Low measurement value in a preset moving average time longer than a sum of the ON-time of the High level at a preset sampling interval.

Abstract: A vibration actuator is capable of reducing differences in vibration phase and vibration amplitude without raising a voltage of a drive circuit when driving a contact member using a plurality of vibrators connected in series. The vibration actuator includes a vibrator device and a contact member that moves relative to the vibrator device. The vibrator device includes transformers of which primary coils are connected in series, and vibrators that are respectively connected in parallel to secondary coils of the transformers.

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Abstract: Ina power conversion system having a fixed pulse pattern modulation unit 2 that is configured to refer to tables storing therein pulse patterns that determine respective command voltage levels corresponding to phase information for each modulation ratio and to generate a gate signal g on the basis of a command modulation ratio d and a control phase ? and driving a power converter 3 on the basis of the gate signal g, the fixed pulse pattern modulation unit 2 is further configured to, when performing a pulse pattern transition, search for a proper post-transition table reference position and make a command voltage level follow a command voltage level of a post-transition pulse pattern. With this, the power conversion system that can perform the pulse pattern transition without current impulse and that can also be applied to a multi-level power converter having four levels or more can be provided.

Abstract: A power supply control system includes a power generator for providing a signal to a load. The power generator includes a power controller controlling a power amplifier. The power generator includes an adaptive controller for varying the output signal controlling the power amplifier. The adaptive controller compares an error between a measured output and a predicted output to determine adaptive values applied to the power controller. The power generator also includes a sensor that generates an output signal that is digitized and processed. The sensor signal is mixed with a constant K. The constant K is varied to vary the processing of the sensor output signal. The value K may be commutated based on the phase, frequency, or both phase and frequency, and the bandwidth of K is determined by coupled power in the sensor output signal.

Abstract: The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.

Abstract: In 5G and 6G, each message element of a message is transmitted with a constant amplitude level. Disclosed herein is a more resource-efficient modulation scheme in which each message element is modulated to two of the amplitude levels, with a first amplitude level in the first half of a message element, and a second amplitude level in the second half. The information density of the message is thereby doubled, saving time and resources. The transition between the first and second amplitude levels can be abrupt, as in a square wave, or ramped, as in a linear ramp function. The changing amplitude may cause a frequency shift; however the transmitter can calculate that shift and apply a frequency correction to each message element to compensate. The changing amplitude can also deposit energy in adjacent subcarriers; however the receiver can calculate that energy and subtract it from the adjacent subcarriers before demodulating.

Abstract: Disclosed in the present application are a method for reducing SGLTE coupling de-sense and a mobile terminal, the method including: filtering out an LTE network frequency band in a signal transmitted by a signal transmission end of a GSM; and filtering out a network frequency band in a signal of a signal reception end accessing the GSM other than a GSM network frequency band. Employing the present application may eliminate mutual interference between a GSM signal and an LTE signal due to the GSM network frequency band and the LTE network frequency band getting too close to each other, which greatly alleviates SGLTE mobile terminal coupling de-sense situation.

Abstract: Example systems and processes control transition of an electric motor from open-loop operation to closed-loop operation by detecting zero-crossing (ZC) locations of the back-electromotive force (BEMF). The rotor angle of the electric motor is changed, e.g., by changing acceleration of the electric motor to correct a phase difference based on the detected ZC locations and an open-loop profile of the electric motor. Detected ZC locations may be used to identify ZC-detected-based commutation points, and each detected ZC location may be used to update a next commutation point. During the control process the open-loop profile is updated. Transition may occur when a set number of ZC-detection-based commutation points are sufficiently aligned with corresponding updated commutation points, or such alignment is maintained for at least one electrical cycle.

Abstract: To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.

Abstract: An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.

Abstract: System and methods implemented in a coherent receiver having a pair of Avalanche Photodiodes (APD) include adjusting one or more of a reverse bias voltage (VAPD) on a P-path (VAPDP) and on an N-path (VAPDN) responsive to an output (PIN,CM) that indicates electrical power of an AC common-mode input signal; adjusting a Transimpedance Amplifier (TIA) common-mode AC response, AdjCM_AC_Response, responsive to an output (POUT,CM) that indicates electrical power of an AC common-mode output signal; and/or adjusting one or more of VAPDP and VAPDN responsive to received signal Signal-to-Noise Ratio (SNR).

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.