Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Abstract: A phase locked loop system including first and second counters connected respectively to first and second registers. The first register contains a number M and the second register contains a number N. The first counter is responsive to a reference signal Fref and the second counter is responsive to an output signal Fout. The first counter provides an output signal F1 responsive to M cycles of Fref and the second counter provides an output signal F2 responsive to N cycles of Fout. The F1, F2, Fref and Fout signals are connected to a phase detection circuit where the phases of Fref and Fout are compared under the control of the larger states of F1 and F2. The output signal of the phase detection circuit is connected to a voltage controlled oscillator that produces the output signal Fout proportional to the phase detection circuit output signal. The Fout signal is looped back to the second counter until the phase locked loop system settles when Fref/M equals Fout/N.

Abstract: A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal.

Abstract: An integrated circuit for generating an oscillator clock signal based on a reference clock signal includes a wide band digital frequency detector. The wide band digital frequency detector includes a first shift register clocked by the reference clock signal and a second shift register clocked by the oscillator clock signal. A third shift register receives as an input the output from the first shift register and is clocked by the output of the second shift register. The third shift register provides a first oscillator control output. A fourth shift register receives a phase of the reference clock signal as an input and is clocked by the oscillator clock signal to provide a second oscillator control output. In an alternate embodiment, the first oscillator control output is coupled as the up-down control input of an up-down counter and the second oscillator control output is coupled as the clock input to the up-down counter to control the oscillator clock frequency.

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop, and circuitry for accomplishing that method. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks.

Abstract: A frequency locked loop frequency synthesizer is comprised of a loop including a voltage controlled oscillator, a phase lock locked loop frequency detector, a divide by N counter and a low pass loop filter. A steering voltage is applied to the loop filter to produce a desired frequency or frequencies. The frequency lock loop frequency synthesizer drives the voltage controlled oscillator frequency to be N times the reference frequency. The frequency lock loop synthesizer inherently has 90 degrees less loop phase shift than a conventional phase lock loop. Additionally, the frequency lock loop frequency synthesizer provides a highly accurate, continuously tuneable, frequency synthesizer that includes a linear frequency detector in the frequency lock loop.

Abstract: A phase locked loop circuit may be utilized as a low jitter clock regenerator in order to generate an extremely stable low jitter signal which is to a large extent immune from input phase and frequency noise. The slaving clock generates an output at a fixed phase relationship to a reference input. The clock regenerator is advantageously implemented by a logic gate type phase detector connected to a multi-stage loop filter. The loop filter output is connected to a phase correction circuit whose output is mixed with the loop filter output to provide a control input to a voltage controlled oscillator. The voltage controlled oscillator output may be provided directly, or through a frequency divider, to a feed-back input of the phase detector.

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: A phase/frequency-locked loop (P/FLL) circuit for generating output signals synchronized with input signals in frequency and phase. The circuit includes a phase comparator which responds to the input signals and to the output signals to develop therefrom phase comparison signals in the form of positive or negative voltages corresponding to the phase differences between the input and output signals. A filtering circuit produces from the phase comparison signals a control signal for a voltage controlled oscillator (VCO) which produces in turn an oscillation signal having a frequency corresponding to the control signal. A phase controller responds to the control signal for the VCO as well as to the output oscillation signal thereof and produces the output signals in a form and wave shape which cause the control signal for the VCO to have a single voltage polarity. The P/FLL circuit of the invention reduces the time required to pull-in the frequency of the VCO and also expands the pull-in range.

Abstract: A phase-locked oscillation circuit system for dividing a clock whose frequency is an integral multiple of a signal produced by dividing the frequency of an input clock. While the input clock to the circuit is shut off, a phase comparator included in the circuit is supplied with a reference signal which is the signal being applied to the compare input of the comparator and the timing of which is modified by a small amount. The system protects the output of a voltage controlled oscillator and, therefore, the output clock of a phase-locked oscillation circuit thereof against disturbances ascribable to the shut-off and recovery of an input clock.

Abstract: A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.

Abstract: A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled osc

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: An asynchronously resettable counter/divider (25) in a phase-locked loop (PLL) for a frequency synthesizer (12) reduces the lock-up time for the PLL by resetting the resettable counter/divider when the phase difference between the output signal from a VCO (20, 21) and a low frequency reference signal (30) exceeds a predetermined value.

Abstract: A synthesizer including a voltage-controlled oscillator, a phase-frequency comparator, a variable-rank frequency divider, a command device to control the oscillation frequency of the voltage-controlled oscillator on a frequency which is a multiple of the frequency of the reference signal as a function of the rank of division of the variable-rank frequency divider. The phase-frequency comparator circuit sends a first series and a second series of pulses as a function of the phase advance or delay respectively of the signals applied to its first and second inputs, to charge or discharge an integration capacitor and provide a signal commanding the advance or delay of the frequency and phase of the oscillator as a function of the voltage developed at the terminals of the capacitor.

Abstract: A circuit for the regeneration of the clock signal within a message containing a preamble and random data. No assumption as to the message structure is required for the operation of such a circuit. The circuit operates on an autocorrelation principle which allows a voltage controlled oscillator (VCO) which is used to reconstruct the clock signal to operate free of the data format. The device is essentially formed as a phase correlator connected to a feedback loop which contains in series a filter, an amplifier and a voltage controlled oscillator. The correlator is formed by a delay line feeding a delayed data signal to two multipliers. The data is also fed to a shift register, the output of which is also fed to the multipliers. The multiplier outputs are fed to a differentiating element which outputs an error signal which acts as a clock correction signal feeding the VCO which, when necessary, adjusts the VCO output so as to match the clocking within the circuit with the clock timing of the message received.

Abstract: A circuit configuration includes a controllable oscillator issuing an output signal. A phase detector is acted upon by a reference signal and by the output signal of the oscillator. A first charge pump is controllable by the phase detector and has an input connected to the phase detector and an output. A loop filter is connected between the first charge pump and the oscillator for triggering the oscillator. A second charge pump is connected parallel to the output of the first charge pump.

Abstract: The charge pump circuit of a phase locked loop has a sensing device, latch and charge pump. When there are contemporaneous up and down signals being produced by the charge pump, a reset signal is provided from the sensing device to a latch which is coupled between the input to the circuit and the pump. Input signals are then inhibited from reaching the charge pump.

Abstract: A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Abstract: A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

Abstract: A frequency synthesizer phase locked loop includes a voltage controlled oscillator (VCO) providing a variable frequency signal, a reference frequency oscillator providing a reference frequency signal, a phase comparison circuit for comparing the phases of the variable frequency and reference frequency signals and providing an output signal to a loop filter, the output of the loop filter providing a frequency control signal to the VCO. The phase comparison circuit includes a digital phase detector providing an output signal on an output line coupled to a charge pump for providing a first output signal to the loop filter; and an analog phase detector including a sample and hold circuit, and a control circuit responsive to the variable and reference frequency signals for providing a signal for sampling to the sample and hold circuit, the sample and hold circuit providing a second output signal to the loop filter.

Abstract: A frequency synthesizer having a frequency divider and a frequency multiplier in the feedback loop is disclosed. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider, which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.

Abstract: A synchronizing circuit including an oscillator, a phase discriminator having a first input coupled to an input terminal of the circuit for receiving an incoming synchronizing signal, a second input for receiving a signal derived from the oscillator and an output for applying a control signal to a control input of the oscillator for controlling the frequency and/or the phase of the oscillator signal. To ensure that the action of the circuit is not disturbed when no signal is present at the input terminal of the circuit, the circuit includes an auxiliary circuit for reducing the difference between the signal at the output of the phase discriminator and a reference, the auxiliary circuit being active in response to a synchronizing signal detector at the output of the phase discriminator in the absence of the incoming synchronizing signal and inactive in the opposite case.

Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Abstract: A phase locked loop circuit including ramp generating circuitry for generating a dual slope ramp signal having alternating positive and negative slopes that are controlled by the level of the control signal, and sampling circuitry responsive to sample command pulses for providing a sample output representative of the level of the dual ramp signal at the time of sampling. The sample output is provided to a loop which provides the control signal for the ramp generating circuit. Also disclosed is a phase locked loop having ramp generating circuitry for generating a ramp signal, and track and hold circuitry having a plurality of track/hold capacitors that are controlled to track the ramp voltage or hold the ramp signal voltage in response to a sample command signal, such that only a capacitor that is tracking is switched to hold the ramp voltage in response to the sample command signal.

Abstract: The invention relates to automatic phase adjustment in a phase locked loop including an oscillator (Os) with a controllable frequency. The oscillator generates a timing signal which is used together with a received data signal (1) to form two pulse trains (9,10) which comprise pulses of a duration which in the first pulse train (9) is independent of, and in the second pulse train (10) is responsive to, the phase position of the timing signal relative the phase position of the data signal. The pulse trains are utilized to form a control signal to the oscillator (Os). In forming the pulse trains (9,10) there is utilized a first array of signals (6-8) which are formed by the data signal (1) being sampled in several different phase positions with the aid of mutually phase shifted clock signals (2-4). A rapid locking-in of the phase locked loop is obtained in accordance with the following.

Abstract: In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to see an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal.

Abstract: A circuit for high-efficiency tuning of video frequencies comprises a closed control loop including a voltage controlled oscillator, a frequeny divider, a phase comparator, and a low-pass filter cascade interconnected via respective inputs and outputs, with the filter output connected to the oscillator input to form the loop. The circuit further comprises a second comparator connected in parallel to the phase comparator between the frequency divider output and the low-pass filter input to compare a reference frequency to a frequency from the divider when the values of each frequencies lie far apart.

Abstract: A PLL circuit comprises a phase comparator for inputting input and output clock signals and detecting a difference in phase between these both signals and outputting a signal based on the phase difference; a proportional circuit for converting the output signal based on the phase difference from the phase comparator to a first voltage approximately proportional to the phase difference; an integral circuit for converting the output signal based on the phase difference from one of the phase comparator and the proportional circuit to a second voltage approximately proportional to an integral value of the phase difference; and a voltage-controlled oscillator for inputting the first output voltage from the proportional circuit and the second output voltage from the integral circuit, and generating an output clock signal having a frequency controlled by the first and second output voltages.

Abstract: A phase and frequency detector circuit includes both a phase comparator such as an exclusive-OR gate possessing high phase sensitivity, and a frequency-phase comparator that is sensitive to differences in frequency. The outputs of these circuits are combined to provide a single output signal offering both frequency discrimination and sharp phase discrimination.

Abstract: A voltage controlled oscillator (VCO) is controlled by a separate phase locked loop (PLL). The PLL includes a first variable delay circuit of m stages which receives a reference frequency signal and produces a delayed signal which is compared in a phase comparator with the reference frequency signal. A first control signal generating circuit in the PLL receives the output of the phase comparator and a reference voltage to produce a first control signal for controlling the delay of the first variable delay circuit. The VCO contains a ring oscillator formed of a second variable delay circuit of n stages similar to those of the first variable delay circuit. A second control signal generating circuit in the VCO receives the output of the phase comparator and a control voltage to produce a second control signal for controlling the delay of the second variable delay circuit to thereby control the output frequency of the VCO.

Abstract: An AFC circuit using counters, flip-flops and logic gates produces a first pulse signal only when the phase of a VCO output signal lags the phase of a reference signal, and produces a second pulse signal only when the phase of the VCO output signal leads the phase of the reference signal. The first and second pulse signals control a switch to connect a first or a second constant current source to charge or discharge a filter circuit, to thereby produce a control voltage for the VCO. When the VCO output signal is in phase with the reference signal, the switch remains in a neutral position to hold a constant control voltage on the filter.

Abstract: In a phase control loop of an oscillator circuit having an oscillator (1) whose frequency is dependent on a control current (81), an output signal is obtained from a phase detector (13) in the phase control loop and is applied to a switchable (23, 27) first current-source circuit (29) charging a capacitor (35) from which a control signal is obtained which is applied via a second current-source circuit (63) to a control signal input (81) of the oscillator (1). To render the operation of the circuit less dependent on the frequency of phase variations, the second current-source circuit is also switchable (69, 71) by the phase detector (13).

Abstract: A phase locking system for providing a sampling signal which is to be phase/frequency locked to an applied signal includes a controllable oscillator coupled to a sampling circuit to produce samples of the applied signal representing substantially quadrature phase related components of the applied signal. An accumulator respectively accumulates the quadrature phase components over predetermined intervals. A differencing circuit successively forms the differences of one of the components from successive intervals. The differences are used to generate a control signal to alter the signal generated by the controllable oscillator.

Abstract: A frequency synthesizer including an oscillator (1) whose frequency is controlled by a tuning signal (TS), a phase detector (4) and a phase lock loop circuit (5, 6). A tuning indicator (7) has a tolerance on the phase difference between the tuning frequency signal and the reference frequency signal. The phase detector produces a first (PS1) and a second (PS2) phase signal upon leading and lagging, respectively, of the phase between the tuning frequency signal (F.sub.T) and a reference frequency signal (F.sub.R). The tuning indicator includes delay circuits provided at the input of AND-gates in such manner as to cancel the phase signals (PS1) and (PS2) of a duration less than a predetermined duration, and a register producing a confirmed tuning indication signal (IS) only when the phase signals (PS1) and (PS2) indicate stable tuning during at least two consecutive periods of the reference frequency (F.sub.R).

Abstract: A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.

Abstract: A PLL comprising a phase comparator circuit for detecting the phase of a pulse signal based upon the input signal and the phase of a pulse signal based upon the output signal, a smoothing filter for smoothing the output of the phase comparator circuit, a loop filter for controlling the oscillation frequency on the basis of the smoothing filter, and a voltage controlled oscillator circuit for sending out the output signal having a frequency corresponding to the voltage based upon the output of the loop filter. Since the smoothing filter is separated from the loop filter, time constants of the smoothing filter and the loop filter can be set independently and with precision. If the time constant of the smoothing filter is chosen to be extremely small, for example, the time constant of the phase-locked loop is defined by the time constant of the loop filter. It is thus possible to define the time constant of the phase-locked loop by only selecting the time constant of the loop filter.

Abstract: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which utilizes gain compensation (90,110) for optimizing phase-locking speed. The sample-and-hold circuit (FIG. 6) also includes circuitry for substantially reducing perturbations at its output. The frequency synthesizer further includes control circuitry (70) and a reference frequency generator (20) for quickly reinitializing the synthesizer in response to a command to change frequency.

Abstract: In an intermittently operative phase-locked loop, in order to prevent the oscillator frequency from significantly changing at the time of turning on of an electric power source, a point in time at which a phase difference between clock signals respectively fed to a reference frequency divider and to a frequency divider for dividing the output frequency of a voltage-controlled oscillator becomes substantially zero is detected, and the two frequency dividers are initialized when the above-mentioned point in time is detected after turning on of the electric power source.

Abstract: A phase locked loop circuit including a controllable oscillator, a phase detector for detecting a phase difference between an output signal of the oscillator and an input signal, and a control signal generator for generating a control signal for controlling an oscillation frequency of the oscillator on the basis of the output of the phase detector. The phase locked loop circuit also includes a feedback circuit for controlling a level of the control signal on the basis of a DC level thereof. The feedback circuit is able to temperature compensate for changes in the oscillator output signal thereby keeping the lock range of the phase locked loop circuit constant against variations in temperature.

Abstract: A phase discriminator and data standardizer apparatus measures phase difference between a data signal obtained from a magnetic disk device and a variable-frequency reference data clock. From the measured phase difference, the apparatus develops a phase difference signal used to adjust the frequency of the reference data clock in order to reduce the phase difference. The apparatus includes a multi-state latch circuit that responds to the input data and clock signals by measuring the phase in a phase measurement transition cycle in which only one state variable changes at a time and producing the phase difference signal based upon the measurement. A gate responds to the measurement transition cycle by producing the phase difference signal. The apparatus further standardizes the input data so as to provide the data in a format that is predictably standardized in its time relationship to the reference data clock signal.

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which utilizes gain compensation (90,110) for optimizing phase-locking speed. The sample-and-hold circuit (FIG. 6) also includes circuitry for substantially reducing perturbations at its output. The frequency synthesizer further includes control circuitry (70) and a reference frequency generator (20) for quickly reinitializing the synthesizer in response to a command to change frequency.

Abstract: A phase comparing circuit can be made as a semiconductor integrated circuit for inclusion in a phase-locked loop for generating a phase-locked output signal synchronized with a pilot signal. The phase comparing circuit generates first and second reference signals with reverse polarity about their DC level from the pilot signal and first and second base signals having a DC level substantially the same as the DC level of the reference signals. First and second switching signals with reverse polarity about their DC level are generated from the phase-locked output signal. A plurality of bipolar transistors are operated by the switching signals alternately to provide first and third current paths and second and fourth current paths connecting the reference and base signals to cancel the DC components therefrom. A voltage deriving circuit provides a control signal current path that connects the first and third current paths and the second and fourth current paths.

Abstract: A digital signal detector utilizing a detected input digital signal derived from a reference square wave and a received pulse train to establish phase and frequency variations between the reference signal and the received signal. The detected signal and the reference signal are coupled to up-down counters wherein overflow counts from preset values are obtained which are representative of the frequency and phase difference between the reference and received signals. These overflow counts are utilized to establish phase and frequency error correction signals which may be coupled to control the reference oscillator to provide frequency and phase lock between the reference and received signals.

Abstract: A frequency lock system including an oscillator providing a switching output voltage that switches at a given frequency between fixed periods in each of first and second states and a reference source providing a variable reference voltage that periodically varies from and returns to a given voltage level at a predetermined frequency less than 1/2 the given frequency. A reference lock circuit provides a reference pulse of finite width in response to occurrence of the given voltage level and an oscillator lock circuit provides a control pulse of finite width a certain period after switching of the output from its first to its second state. In addition, a reset circuit resets the oscillator to initiate a new fixed period thereof at the second state in response to temporal coincidence of the reference and control pulses.

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.

Abstract: Synchronization of a local timing signal with an incoming reference timing signal is realized by employing a frequency estimator and frequency synthesizer in conjunction with a local fixed oscillator. The frequency estimator includes a first phase-locked loop including an integrator for generating a frequency estimate which is the difference between the frequency of the incoming reference timing signal and the frequency of the fixed oscillator signal. The phase value of the frequency estimate obtained by integrating the frequency estimate is supplied to a second phase-locked loop which includes a digitally controlled oscillator to generate the local timing signal. If the incoming reference timing signal is lost or if there is too large a variation in a phase error signal in the first phase-locked loop, the value of the frequency estimate is held constant. Consequently, the second phase-locked loop never free runs and the local timing signal remains in synchronization with the reference timing signal.

Abstract: Apparatus for controlling the frequency of a voltage controlled oscillator in response to a horizontal synchronizing signal of a video signal comprises a frequency divider for dividing the frequency of the output of the oscillator and a control for phase-comparing the output of the frequency divider with the horizontal synchronizing signal and controlling the frequency of the oscillator in response to the result of the phase comparison. The control comprises a circuit for forming a control signal by using a first pulse signal having a first signal level and a second pulse signal having a second signal level in response to the phase difference between the horizontal synchronizing signal and the output of the oscillator. A correcting signal is added to the control signal when the phase of the horizontal synchronizing signal is beyond a predetermined range.