Abstract: A phase comparing circuit can be made as a semiconductor integrated circuit for inclusion in a phase-locked loop for generating a phase-locked output signal synchronized with a pilot signal. The phase comparing circuit generates first and second reference signals with reverse polarity about their DC level from the pilot signal and first and second base signals having a DC level substantially the same as the DC level of the reference signals. First and second switching signals with reverse polarity about their DC level are generated from the phase-locked output signal. A plurality of bipolar transistors are operated by the switching signals alternately to provide first and third current paths and second and fourth current paths connecting the reference and base signals to cancel the DC components therefrom. A control signal generating circuit provides a control signal current path that connects the first and third current paths and the second and fourth current paths.

Abstract: In the disclosed phase-locked loop circuit, a phase detecting circuit produces a control signal for controlling the frequency of an oscillator according to the phase difference between the output of the oscillator and an input signal. The control signal controls the oscillator only during a specific period of time in which there is a phase difference. This eliminates the need for a low pass loop filter and results in a quick response, stable phase-locked loop circuit.

Abstract: A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nf.sub.H (n is an integer), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nf.sub.H, a difference between the pulse widths of the clocks resulting from counting down the first and second clocks to 1/M and the frequency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchronized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.

Abstract: A phase comparator for receiving an input signal and a signal to be compared with this input signal, comprising an auxiliary stage. The auxiliary or dynamic reducing stage includes a circuit for reducing a predetermined value of the phase difference between the two inputs of the comparator and a circuit for recovering said value at the output of the comparator via a circuit delaying the information expressing this value. The phase comparator may be used in a phase locked loop.

Abstract: A simplified clock-signal reproducing circuit for reproducing a clock signal from a repetitive pulse signal or a digital signal such as an EFM signal read from a compact disc as a data recording medium of the compact disc digital audio system is provided. A voltage-controlled oscillator generates a first repetition signal, and a second repetition signal is formed from the first repetition signal, the second repetition signal being the clock signal. The repetitive pulse signal is latched by a first latch in response to the clock signal, and a signal which is a delayed output of the first latch is latched by a second latch in response to the clock signal. A voltage representing a phase difference between a clock signal in the repetitive pulse signal and the clock signal generated by the voltage-controlled oscillator is generated in accordance with a first phase difference between the input and output signals of the first latch and a second phase difference between input and output signals of the second latch.

Abstract: A signal comparison circuit is described which is implementable by a logic gate array structure without introducing the possibility of the large, incorrect error signals possible with phase comparators implemented by logic gate array structures. The circuit has particular applicability to phase-locked-loop circuits because it compares the frequency and phase of a first input signal with the frequency and phase of a second input signal in an error-free manner. A first master flip-flop triggered by the first input signal produces negative pulses, under the control of a NAND latch. A second master flip-flop is triggered by the second input signal to produce negative pulses, under control of the same NAND latch. The NAND latch is responsive to the outputs of the first and second master flip-flops. The first and second input signals are each delayed, and the delayed input signals are respectively used to trigger first and second slave flip-flops (which are slaves to the two master flip-flops).

Abstract: A PLL frequency detector or comparator is provided having an up-down counter, responsive to beat signals produced by the input periodic waveforms of the VCO reference signals and the input data signals, to produce top and bottom output signals which enable multivibrators connected to each of the input signal lines to transmit overflow and underflow output pulses, whose sum is proportional to the difference in frequency of the input signals up to a predetermined maximum level, as control signals for the PLL loop filter. The up-down counter may include three or more states with buffer states which prevent generation of overflow or underflow output signals when the PLL is within a predetermined region of phase-lock and the sign of the beat signal oscillates.

Abstract: A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse.

Abstract: A data reproduction circuit, which can be used for reproducing audio data from an optical disc, includes a phase-locked loop which has a circuit for detecting polarity inversions of the input signal, a circuit for comparing the phases of a polarity inversion signal with a reference signal, and circuitry for generating an output clock signal which is phase-locked with the input signal, that clock being used to strobe the input signal to remove fluctuation and jitter from the input signal.

Abstract: A pulse corrector provides circuitry for responding to first and second input pulses applied to its first and second inputs to provide first and second output pulses at the first and second outputs respectively such that the first pulse edge occurring at the first output after an interruption of the first input pulses never leads the corresponding first pulse edge occurring at the second output irrespective of the phase relationship between the corresponding first pulse edges occurring at the inputs after the interruption. Circuitry is also provided to ensure that the duration of the pulse produced at the first output and starting with the aforementioned first edge is not substantially less than that of one of the first and second input pulses, thus ensuring that a phase detector connected to the outputs of the pulse corrector is placed in a predetermined neutral state by the aforementioned pulse edges such that both its outputs are activated before reference pulses are again allowed to contact its input.

Abstract: In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator whose oscillation frequency varies in accordance with a control signal, an A/D converter which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator, a decision circuit for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter, and a logic circuit responsive to the output of the decision circuit to apply a logical operation to a decision signal derived from the A/D converter and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the voltage controlled oscillator.

Abstract: A quartz crystal oscillator is controlled entirely by digital elements to phase lock with a reference square wavetrain by alternately switching the tuning circuit of the oscillator between first and second configurations. The ratio of the times during which the tuning circuit is in its respective configurations is a function of the relative phases of the oscillator output and the reference wavetrain and serves to determine the precise frequency of the oscillator so as to keep its output locked to the phase of the reference wavetrain.

Abstract: A phase lock circuit including a phase/frequency detector, a plurality of selectable filters, and a plurality of variable frequency signal generators connected in a loop to lock an output signal to an input signal. An out-of-frequency-range condition detector is provided to facilitate automatic selection of an appropriate in-range combination of filter and signal generator to cause lock to occur.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A sample and hold phase detector for a phase locked loop includes a digital detector for detecting the frequency and phase difference between the reference signal and the voltage controlled oscillator (VCO) signal. In a first mode of operation, the digital detector generates a first signal relating the difference in frequency and in a second mode of operation generates a second signal relating the difference in phase. A capacitor stores the first or second signal depending on the operational mode of the digital detector. The capacitor is selectively discharged in response to a discharge signal produced by the digital detector when either the VCO frequency is higher than the reference frequency or following each detection of a phase difference. A first amplifier is used to bypass a portion of the loop filter to effect rapid changes in VCO frequency in the first mode while a second amplifier couples the control voltage to the VCO via the loop filter to maintain proper VCO frequency in the second mode.

Abstract: A vehicle detector installation includes a loop oscillator the loop of which is laid in the roadway and which is locked in operation to a voltage controlled oscillator (VCO). Vehicle detection is effected by a phase detector monitoring the phase difference between the oscillators. The VCO is incorporated in a phase-lock loop (PLL) that is capable of locking to a multiple of a reference frequency oscillator over a range of multiples. To achieve the locking of the loop oscillator to the VCO, means are provided for disabling the normal operation of the PLL and sweeping the VCO over its range of frequency until the phase detector indicates that the loop oscillator and VCO frequencies are equal. This indication activates the PLL to its normal operation to pull the VCO and therewith the loop oscillator to an adjacent multiple of the reference frequency. The PLL is maintained by a repeated charge/discharge cycle of the VCO capacitor that is dependent on the phase of the reference oscillator and the VCO.

Abstract: An improvement in a phase locked loop comprising a VCO for generating a signal S.sub.VCO of frequency f.sub.VCO, a divider for dividing f.sub.VCO to produce a signal S.sub.N of frequency f.sub.N, a reference signal generator for generating a reference signal S.sub.R of frequency f.sub.R, and with said VCO responsive to a particular value E.sub.c of a variable control signal e.sub.c to cause f.sub.N =f.sub.R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S.sub.N and S.sub.R to cause f.sub.N =f.sub.R and comprising a three stage left/right shift register responsive to one of signals S.sub.N or S.sub.R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S.sub.N or S.sub.R to shift binary 1's into the third stage thereof in the left direction.

Abstract: A clock recovery system including a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.

Abstract: A non-linear phase detector is disclosed which compensates for gains occuring during tuning a frequency generator of a known phase locked loop circuit which incorporates a Varactor tuned resonant circuit as a VCO. The phase detector is of the sample and hold type and incorporates a Varactor rather than a hold capacator to compensate for non-linear gains which occur when tuning the frequency generator across its band spread. Additionally, bias compensation is provided for the resonant circuit Varactor to offset its contact potential.

Abstract: A circuit arrangement for generating a frequency controlled signal which is made synchronous with an input signal by an automatic phase control circuit. The circuit comprises a variable frequency oscillator for generating the frequency controlled signal and a phase comparator for generating a first control voltage based on the phase variation of the input signal, the control voltage being supplied to the variable frequency oscillator to control the frequency of the frequency controlled signal. The circuit arrangement includes a circuit for detecting a frequency difference between the frequency controlled signal and a reference signal from a reference oscillator, and a circuit for comparing the outputs from the phase comparator and the frequency difference detecting circuit to produce an additional control voltage to be mixed with the first control voltage.

Abstract: A modulator for controlling the frequency of the power applied to a gyroscope to rotate the seismic mass (wheel) of the gyro so as to compensate for movement of the gyro case about the spin axis of the gyro is disclosed. The modulator includes a slow acting phase-locked loop that includes: a high frequency (e.g., 20 MHz) crystal controlled voltage controlled oscillator (VCXO); a divider for dividing the VCXO frequency down by several orders of magnitude (e.g., six); a phase comparator for comparing the relatively low frequency output of the divider with a low frequency reference signal; a loop filter for filtering the output of the phase comparator so as to give the loop its desired dynamic response chacteristic and bandwidth; and, a summing amplifier for summing the output of the phase comparator with a rate signal having a voltage level linearly related to the rate of movement of the gyro case about its spin axis.

Abstract: A circuit for synchronizing the frequency and/or phase of an output frequency signal (f.sub.0) to a reference frequency signal (f.sub.ref) is disclosed. A digitally controlled oscillator produces an output frequency signal which varies dependent upon an input digital signal which also is varied. A comparator means is coupled to the oscillator and the reference signal for determining the presence or absence of a frequency or phase difference between the output frequency signal and the reference frequency signal and generates a digital signal to the oscillator indicating whether the output frequency signal should be increased or decreased. In one embodiment, the comparator means comprises an up/down counter and the digitally controlled oscillator comprises a digital-to-analog converter (DAC) coupled to an oscillator circuit. The output of the oscillator circuit (f.sub.0) is fed back through a divide by N counter circuit.

Abstract: An input signal is mixed with a reference frequency and with a frequency 90.degree. phase-displaced from the reference frequency, so as to produce resultant waveforms whose slopes are dependent on the respective frequency differences detected. Both waveforms are differentiated to produce respective slope signals. Two comparisons are then carried out: one comparison compares the sign of one slope signal with the sign of the waveform producing the other slope signal, and the second comparison compares the sign of the other slope signal with the sign of the waveform producing the first slope signal. The two comparisons produce nominally identical intermediate signals having values dependent on the difference between the input and reference frequencies. Control means operative in dependence on the relative magnitudes of the two waveforms then selects the intermediate signals alternately, each selected intermediate signal constituting the output signal of the circuit.

Abstract: A frequency agile phase detector includes a digital frequency detector section connected to a hold-sample-hold phase detector section. The digital frequency detector develops control signals related to frequency differences between a reference periodic signal and a variable periodic signal. The control signal determines the amplitude of a voltage signal impressed across a first hold circuit. A sample signal acts to sample and transfer the sample voltage signal from the first to a second hold circuit so as to reduce phase differences between the reference and variable periodic signals. The detector is incorporated into a phase locked loop using the VCO output as the variable periodic signal so that acquisition and lockup of the loop is obtained even when the two periodic signals are decades apart. Additionally, the hold-sample-hold section aids in reducing the reference and sampling energy required which results in a spectrally pure output signal.

Abstract: A circuit for producing a frequency dependent output signal in response to two a.c. input signals, including a converter unit connected to receive the two a.c. input signals for furnishing an output signal having a d.c. component which varies in dependence on changes in the value of a relationship between the frequencies of the two a.c. input signals, and a frequency generator connected to the converter unit for producing an a.c. output signal whose frequency is a function of the value of such d.c. component.

Abstract: A phase locked loop (10) has a phase insensitive frequency comparator (18) including an up/down counter (26) incremented one way by loop frequency pulses (on 28) and incremented the other way by reference frequency pulses (on 30) and which yields error correction signals (on 22 and 24) to adjust loop frequency when the counter overflows or underflows given limits. Timing means (32) is provided at the input (28, 30) to the counter (26) and prevents any clock pulse from being lost by ensuring a sufficient time gap between pulses. A sample and hold phase detector circuit (16) is provided at the data acquisition input to the loop (10) and enables successful acquisition and lock-on even with many zeros between the incoming data bits, and does so with a minimum number of components.

Abstract: Three sample and hold circuits (26, 30 and 34) sample a received pulse amplitude modulated signal at twice the data bit frequency or timing of the received signal. The clock to the sample and hold circuits is timed so that three consecutive samples, two mid-bit samples and a transition sample are held in the circuits (26, 30 and 34) once every two sample periods. The mid-bit samples are added together by an adder (32) and divided by two in a divider (38) to provide an average. The transition sample is subtracted from this average in a subtractor (36) to produce an error signal. The error signal is normalized in a multiplier (44) using the reciprocal of the difference in magnitude between the two mid-bit samples to produce a normalized signal. A clock signal is generated by a voltage controlled oscillator (52) in response to the normalized signal at twice the bit frequency or bit timing and in synchronism therewith.

Abstract: A second-order phase-locked loop circuit which does not require error voltage amplification is described. The output of a voltage controlled oscillator is accurately phase locked to a reference pulse. The loop phase detector is periodically enabled by a pulse generator and draws current only when enabled. Therefore very little noise may be coupled to the voltage controlled oscillator. The phase detector incorporates a current amplifier which allows very accurate establishment of the instant phase comparison takes place.

Abstract: A clock synchronization unit for controlling frequency and phase of a local clock and synchronism with an external clock signal, employs a programmable controller as a part of a phase-locked loop. The controller provides highly accurate control of the clock, including verification of the accuracy of the clock control signal before applying it to the clock oscillator as well as control of the magnitude to the clock oscillator to avoid rapid changes in frequency. In one particular embodiment, the programmable controller comprises duplicated microprocessors which perform operations in step. In a master/slave oscillator arrangement, the controller controls the slave clock oscillator as well as the master to assure tracking of the slave to the master.

Abstract: A first frequency-to-voltage converter develops a first voltage representative of a standard frequency. A variable frequency source is provided to furnish a pulse sequence with constant-duration but variable repetition pulses. A frequency-to-voltage converter receives the pulse sequence to develop a second voltage representative of a total pulse energy generated in the pulse sequence per unit time. The deviation of the second voltage from the first voltage is detected by a comparator to control the variable frequency source to derive a desired frequency.

Abstract: A digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source is in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.

Abstract: A phase locked loop circuit employing a first edge detector consisting of an exclusive OR gate and flip flop circuit feeding by way of a NAND gate, an up counter and a second edge detector of like kind feeding also by way of a NAND gate into a down counter. Both counters feed into an added which provides a signal to a decoder representing the phase difference between the input phase and the output phase signal. The phase processing system provides positive rapid pull-in over the entire frequency range capability of the VCO, which allows narrow bandwidth loops to track rapid rates of frequency change without loss of lock and with great accuracy.

Abstract: A phase-locked loop for PCM transmission systems has a phase comparator (20) which provides continuous regulation of the loop oscillator (30). When a PCM pulse signal is present, the phase comparator selectively compares the PCM and oscillator clock signal and generates an error signal which synchronizes the oscillator to the PCM frequency. During the absence of a PCM pulse, the phase comparator provides a high impedance output and oscillator synchronization is maintained by a loop filter (23). In the disclosed embodiment, the phase comparator is a dual section tristate gate (300).

Abstract: A phase locked loop circuit (100) for generating a periodic clock signal from a controlled oscillator circuit (130) in phase coincidence with a synchronous aperiodic data input signal is disclosed. A pulse of the data signal and a corresponding pulse of the clock signal are applied to a bistable circuit (FF1) having an output signal indicating which of the pulses occurs first in time. The pulses are further applied through delay circuitry (DLY1, DLY2) to another bistable circuit (FF2) having an output signal indicative of the magnitude of phase difference between the pulses. The output signals of the bistable circuits (FF1, FF2) are applied to a multilevel driver circuit (140) which generates an error correction signal pulse defining magnitude and direction of a correction signal to be applied to the oscillator circuit (130).

Abstract: A phase detector circuit is connected to a sine wave reference during a time interval of one-half cycle of the sine wave to be compared. Phase detection is provided by integrating the inputted sine wave reference during such time interval, and immediately following such accumulation of information, the latter is transferred to a holding circuit. The phase detector is applied to a phase locked loop in which the time intervals are established digitally to control FET devices for the sampling and holding functions.

Abstract: A frequency tuning arrangement for tuning a source of variable frequency to a desired frequency, comprises a phase lock loop having a reference frequency source, an adjustable divider dividing the variable frequency to produce an adjustable control frequency, a phase comparator for comparing the phases of the control and reference frequencies to produce a control signal dependent on any phase error detected, and adjusting means responsive to the control signal for adjusting the variable frequency so as to equalize the phases of the control and reference frequencies. In accordance with the invention, means responsive to the phase error imposes on the leading one of the control and reference frequencies a phase delay which is substantially equal to the phase error. This enables the system to respond very rapidly to changes in desired frequency.

Abstract: A first frequency-to-voltage converter develops a first voltage representative of a standard frequency. A variable frequency source is provided to furnish a pulse sequence with constant-duration but variable repetition pulses. A frequency-to-voltage converter receives the pulse sequence to develop a second voltage representative of a total pulse energy generated in the pulse sequence per unit time. The deviation of the second voltage from the first voltage is detected by a comparator to control the variable frequency source to derive a desired frequency.

Abstract: A circuit for extracting a clock pulse waveform from an input pulse waveform comprising a phase-locked loop including a phase comparator having a first input to which the input pulse waveform is supplied, a second input and an output which is coupled in cascade at least with a voltage controlled oscillator whose output is coupled to the second input of the phase comparator. The clock pulse waveform is provided at the output of the oscillator.

Abstract: A phase comparator for a digital phase locked loop which provides first and second order error signals for phase and frequency correction of a voltage controlled oscillator in the loop with respect to data being read for self synchronization of the data. A first order error signal is generated in a first phase detector which operates only during a VCO "unsafe" condition, i.e., when a data pulse is beyond a present limit. A finer, second order error signal is generated in a second phase detector which operates only during a VCO "safe" condition, i.e., when a data pulse is within a preset limit.

Abstract: An electronic phase locked loop circuit including a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample. A feedback circuit generates the sampling clock by coupling the output of the voltage controlled oscillator to the sampling input of the sample and hold circuit.

Abstract: A phase comparator circuit arrangement is provided for controlling an electrical member on the basis of a control signal formed in accordance with the difference detected between a first waveform which is periodic and has a constant cyclic ratio, after it has locked on to a reference signal, and a second waveform which, after this locking on for which it serves as a reference, becomes non-periodic with a variable cyclic ratio for the purposes of exerting the said control. The circuit comprises a combination of a first bistable flip-flop circuit which receives the first and second waveforms respectively and which receives enabling voltages whose evolution is complementary between one input and the other. Means to subtract the waveform emitted by the first flip-flop circuit from the first waveform are provided to form the said signal for controlling the member.

Abstract: Method and system for the constant amplitude control of an electromechanical oscillator utilizing a phase locked oscillator to generate a secondary a-c setpoint which is compared to the oscillator output to provide a difference signal which is passed as a fast-acting negative feedback signal to stabilize the amplitude.

Abstract: A phase lock loop is illustrated which includes clamp means for controlling the rate of change of the output phase to no more than a preselected value. This feature has been found to be beneficial in certain applications such as temporary restraint of the dynamics of a phase lock loop of a data alignment unit of a communications system where downstream equipment cannot tolerate more than a predetermined phase change per unit time without losing synchronization.

Abstract: In a frequency discriminator for a first and a second input signal of a first and a second frequency, a phase detector produces first and second rectangular pulse sequences. When the first input signal leads the second by 0.degree. through 180.degree., the first pulse sequence takes a predetermined peak value with an instantaneous frequency corresponding to the phase difference while the second one continuously has the peak value. When the first input signal lags behind the second by 0.degree. through 180.degree., the second pulse sequence takes the peak value with the instantaneous frequency while the first one continuously has the peak value. A low-pass filter rejects components of the first pulse sequence which are higher than the first and second frequencies.

Abstract: A phase locked loop includes a variable frequency oscillator, a phase comparator for comparing the phase between an output signal derived from the variable frequency oscillator and a reference signal and for generating a control signal in response to the phase difference between the two signals for controlling the variable frequency oscillator, an indicator for indicating the phase difference between the signals, and a control circuit for varying the frequency of the variable frequency oscillator.

Abstract: A phase locked loop includes a voltage-controlled oscillator, and a phase and frequency detector for comprising an input signal pulse wave with a pulse wave from the voltage-controlled oscillator, and for providing a frequency control voltage to the voltage-controlled oscillator. When the pulses overlap, a pulse comparison circuit in the phase and frequency detector produces a frequency "up" signal or a frequency "down" signal proportional to the correction necessary. When the pulses do not overlap, the pulse comparison circuit produces a "non-overlap" signal which effects a rapid frequency correction by causing a current pump in the phase and frequency detector to increase its output to a fixed maximum value, and by causing a loop filter to increase its bandwidth to a fixed maximum value.

Abstract: An automatic frequency control circuit comprising two switching transistors with the emitter-collector paths thereof connected in series with each other between a power source and a reference voltage source, a horizontal synchronizing signal being commonly coupled to the bases of the switching transistors, an integrating circuit having an input terminal receiving a horizontal pulse signal and an output terminal connected to the emitter-collector juncture between said two switching transistors, a smoothing circuit to convert the output voltage of said integrating circuit into a d-c voltage, and a voltage controlled oscillator to produce a frequency output in accordance with the d-c output voltage of the smoothing circuit, the output of said oscillator being fed back to the input terminal of said integrating circuit.