Abstract: A synchronizing circuit including an oscillator, a phase discriminator having a first input coupled to an input terminal of the circuit for receiving an incoming synchronizing signal, a second input for receiving a signal derived from the oscillator and an output for applying a control signal to a control input of the oscillator for controlling the frequency and/or the phase of the oscillator signal. To ensure that the action of the circuit is not disturbed when no signal is present at the input terminal of the circuit, the circuit includes an auxiliary circuit for reducing the difference between the signal at the output of the phase discriminator and a reference, the auxiliary circuit being active in response to a synchronizing signal detector at the output of the phase discriminator in the absence of the incoming synchronizing signal and inactive in the opposite case.

Abstract: A phase locked loop circuit includes a phase detector and an oscillator associated therewith, and a voltage-to-current converter for providing that lag signals sent thereto from the phase detector provide increased signal to the oscillator, and lead signals sent thereto from the phase detector provide decreased signal to the oscillator.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including a FM modulator or FM demodulator. The signal delay device will assure undistorted signals.

Abstract: A Phase Locked Loop (PLL) circuit includes a compensation circuit which corrects for non-linear sensitivity of a varactor of a voltage controlled oscillator (VCO) which is part of the circuit. The varactor is employed as a capacitance tuning element. The compensation circuit controls the sensitivity of a charging/discharging circuit (a charge pump) of the PLL circuit with a feedback signal which is derived from an input to the VCO. The sensitivity characteristic of the charge pump is made the complement of the non-linear portion of the VCO sensitivity characteristic.

Abstract: A PLL for direct modulation having a flat modulation characteristic in the audio frequency range is described. The PLL for the direct modulation comprises a voltage controlled oscillator whose oscillating frequency is controlled by an output voltage of a low pass filter and also modulated by a signal, a programmable frequency divider supplied with an output signal of the voltage controller oscillator or the output signal divided in frequency, and a phase comparator comparing an output frequency f.sub.p of the programmable frequency divider with a reference frequency f.sub.r. The phase comparator outputs signals indicating three conditions in accordance with the results of the comparison: a first transistor turned ON by the output signal of the phase comparator indicating the condition f.sub.r >f.sub.p for charging a capacitor within the low pass filter; a second transistor turned ON by the output signal of the phase comparator indicating the condition f.sub.r >f.sub.

Abstract: A phase lock loop frequency synthesizer for providing a synthesized frequency signal employing a modified adaptive loop construction having parallel feedback paths about a loop amplifier. A normal feedback path having a narrow bandwidth characteristic includes a feedback capacitor having one end connected to electrical ground via a controlled switch and a second feedback path having a wide bandwidth characteristic with a capacitor also connected across the amplifier. Upon the variation of an incoming reference signal, the controlled switch connects the normal feedback capacitor to ground permitting the wide bandwidth feedback path to rapidly settle the loop while charging the feedback capacitor of the normal feedback path. Upon opening the controlled switch, the narrow bandwidth feedback path completes the charging of the feedback capacitor of the normal feedback loop settling the loop to the steady state condition while enhancing the settling time.

Abstract: A synthesizer is provided to include a phase detector, a loop filter, a current source and two current sinks. The current source and the second current sink selectively supplies current to and from the loop filter, respectively. The first current sink selectively sinks current from the current source. Responsive to signals from the phase detector, a controller actuates the current source on prior to switching at least one of the first and second current sinks.

Abstract: A voltage controlled oscillator (VCO) is controlled by a separate phase locked loop (PLL). The PLL includes a first variable delay circuit of m stages which receives a reference frequency signal and produces a delayed signal which is compared in a phase comparator with the reference frequency signal. A first control signal generating circuit in the PLL receives the output of the phase comparator and a reference voltage to produce a first control signal for controlling the delay of the first variable delay circuit. The VCO contains a ring oscillator formed of a second variable delay circuit of n stages similar to those of the first variable delay circuit. A second control signal generating circuit in the VCO receives the output of the phase comparator and a control voltage to produce a second control signal for controlling the delay of the second variable delay circuit to thereby control the output frequency of the VCO.

Abstract: A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits.

Abstract: A voltage-controlled oscillator and a control substitution circuit that interrupts the control loop in case a source of normal control voltage such as a referenced frequency fails, and allows the voltage-controlled oscillator to continue to operate with a nominal control voltage. To allow the oscillator of such a loop to continue to operate for weeks with a practically unchanged frequency under certain circumstances, after the normal control voltage source has failed, the nominal control voltage can be selected such that the oscillator produces an oscillation of a preset frequency. Simultaneously with change-over of the oscillator to the preset frequency, its voltage-to-frequency characteristic is changed by the control substitution circuit such that a change of the control voltage leads to a smaller change in the frequency than in normal operating conditions.

Abstract: A phase detector includes a bridge of FETs which are simultaneously rendered conductive by pulses of a reference signal having a very small duty cycle. A higher frequency signal, whose phase in relation to the reference signal is to be detected, is supplied to a gate of one of the FETs. A bridge output signal is low pass filtered and differentially amplified to produce a phase detector output signal. The phase detector output signal can be used directly to control the frequency of a voltage controlled oscillator which produces the higher frequency signal.

Abstract: A phase-locked loop circuit comprises a controlled oscillator receiving a control signal for generating an oscillation signal of a frequency corresponding to the received control signal, and a frequency divider receiving the oscillation signal for generating a signal having a frequency divided by a given frequency division ratio. A phase detector receives an input signal and the frequency-divided signal. This phase detector generates a first phase difference signal starting at the input signal and terminating at one of a rising edge of the frequency-divided signal. The phase detector also generates a second phase difference signal having a constant pulse width in an interval period between each pair of adjacent first phase difference signals without substantially overlapping the first phase difference signal.

Abstract: In a multiple reference frequency generator, instead of using a quartz crystal for each of the accurate frequencies to be produced, a single quartz crystal is used together with a current controlled oscillator (ICO) and a phase loop comprising a phase comparator (PHC) and a control current generator (GC). The current generator provides a current varying as a function of a voltage and inversely proportional to a resistor value. In a first step, the phase loop causes the oscillator to oscillate at a frequency F0 and the resistor has a value R0. In a second phase, the loop is opened and the resistor is given a value R1 causing the oscillator to oscillate at a frequency F1=F0.times.R0/R1.

Abstract: A circuit comprising three stages, a differential input stage, a store and integrate stage, and a differential output stage. Both input and output stages are co-operative with enable/disable switching, which switching is controlled by timing signals provided externally to control the periods of integration and data reading. The store and integrate stage comprises a pair of transistors and individual current sources, charge being integrated by a capacitor connected between the transistors. At the end of each period of integration the capacitor may be discharged via these sources, or, parallel sources and a further switch may be added to allow separate reset and hole period provision. Such circuits may be combined and timed out in phased sequence for fastest operation. They may be incorporated in Costas phase-locked loops and used as a means of communication data recovery.

Abstract: A phase locked loop circuit using a reference signal and a response control signal with a preset transition time, comprising a voltage-controlled oscillator to produce a signal variable in phase, a detecting circuit responsive to the reference and variable-phase signals for producing a signal indicating a delay or advance in phase of the variable-phase signal with respect to the reference signal during a phase difference detect period for which the signal from the detecting circuit is indicative of a difference in phase between the reference and variable-phase signals for each period of cycle of the variable-phase signal, a voltage signal generating circuit responsive to the signal from the detecting circuit for producing a voltage signal having first and second states to advance and retard the phase of the variable-phase signal, respectively, and a third state to maintain the phase of the variable-phase signal, the signal generating circuit being responsive to this voltage signal for producing the variable-p

Abstract: A PLL comprising a phase comparator circuit for detecting the phase of a pulse signal based upon the input signal and the phase of a pulse signal based upon the output signal, a smoothing filter for smoothing the output of the phase comparator circuit, a loop filter for controlling the oscillation frequency on the basis of the smoothing filter, and a voltage controlled oscillator circuit for sending out the output signal having a frequency corresponding to the voltage based upon the output of the loop filter. Since the smoothing filter is separated from the loop filter, time constants of the smoothing filter and the loop filter can be set independently and with precision. If the time constant of the smoothing filter is chosen to be extremely small, for example, the time constant of the phase-locked loop is defined by the time constant of the loop filter. It is thus possible to define the time constant of the phase-locked loop by only selecting the time constant of the loop filter.

Abstract: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which utilizes gain compensation (90,110) for optimizing phase-locking speed. The sample-and-hold circuit (FIG. 6) also includes circuitry for substantially reducing perturbations at its output. The frequency synthesizer further includes control circuitry (70) and a reference frequency generator (20) for quickly reinitializing the synthesizer in response to a command to change frequency.

Abstract: A dynamic control system includes at least one control loop which contains a comparator, a correction device and an adjusting device with a control device wherein a controlled variable is determined and compared with a reference variable for forming a control difference, the correction and the adjusting device operating to provide a given characteristic, a controlled variable being derived by the adjusting device cooperating with a control variable derived from the control device as the output variable wherein the control loop can be coupled to at least one further control loop and/or variable of the dynamic control system, wherein the further control loop includes an adjusting device and wherein the control device contains at least two functional groups having different characteristics, of which at least one is intermittently connected in the signal path of the control difference for generating the controlled variable and a method for operating the dynamic control system.

Abstract: The method consists in using a sawtooth signal at the output from a lowpass filter of a phase lock loop, in multiplying it by a low frequency squarewave signal, in integrating the resulting multiplied signal in order to obtain a sweep signal, and in controlling a voltage controlled oscillator of the phase lock loop by means of the sweep signal. The apparatus comprises a multiplier (7) and a low frequency generator (8). It may also include, prior to the multiplier, a hysteresis comparator (5) and a highpass filter (6). The output (S7) of the multiplier (7) is connected to a loop filter (3) in said phase lock loop in order to integrate the multiplied signal.

Abstract: The frequency of a voltage controlled crystal oscillator is conventional pulled by means of a varicap diode forming the load capacitance of the oscillator crystal. In order to realize a wider range of frequency pulling, the load capacitance 44 is alternately switched on and off in a known manner. According to the invention a band-switch diode 46 is utilized as a switch element, the hole-storage time of this diode being as long as or longer than the oscillator cycle. By applying a low-frequency control voltage to the diode it is rendered self-switching within the oscillator cycle, so that proportional frequency tuning is achieved.

Abstract: A phase-locked-loop (PLL) circuit comprising a phase comparator, a current-variable charge pump, a voltage-controlled oscillator, a low-pass filter, and frequency dividers. The charge pump drive current is controlled in steps or continuously depending on the operating mode.

Abstract: There is disclosed a phase-locked loop circuit for obtaining an output in phase with an incoming signal including a phase comparator arranged to compare phases of incoming two pulse signals to detect a phase difference between them only during a predetermined time in every period of one of said incoming pulse signals and to produce an output signal corresponding said phase difference and a controlled oscillator arranged to produce an output having an output frequency varying in accordance with the output signal of said phase comparator. According to the phase-locked loop circuit as disclosed, a pulse signal having a frequency produced by frequency division of said output frequency and a constant pulse width is formed and this pulse signal is fed to said phase comparator as the other one of said incoming pulse signals, whereby the occurrence of a false locked state is prevented.

Abstract: A phase locked loop circuit including a controllable oscillator, a phase detector for detecting a phase difference between an output signal of the oscillator and an input signal, and a control signal generator for generating a control signal for controlling an oscillation frequency of the oscillator on the basis of the output of the phase detector. The phase locked loop circuit also includes a feedback circuit for controlling a level of the control signal on the basis of a DC level thereof. The feedback circuit is able to temperature compensate for changes in the oscillator output signal thereby keeping the lock range of the phase locked loop circuit constant against variations in temperature.

Abstract: A bipolar transistor circuit is disclosed, which receives input voltage signals and outputs a current of a polarity in accordance with the input signals and of a predetermined amplitude. This circuit includes a first current source producing a first reference current, an output terminal, bipolar switching transistors coupled between the first current source and the output terminal and controlled by the input voltage signals to supply to the output terminal an output current of a first polarity which has an amplitude of the first reference current minus a base current of the switching transistor or integer times of that amplitude, a current producing circuit producing a current that is substantially equal to the base current of the switching transistor, and a second current source connected to the output terminal and producing a second reference current of a second polarity which has an amplitude of the first reference current minus the amplitude of the current produced by the current producing circuit.

Abstract: An integrated circuit phase-locked loop includes a bipolar bandwidth switch for selectively coupling circuit elements of an external bandwidth filter network so as to control loop bandwidth. The bandwidth switch includes first and second switched terminal means which are coupled to the bandwidth filter network. A differential amplifier has a first control terminal coupled to the first switched terminal and a second control terminal coupled to the second switched terminal. The differential amplifier controls first and second currents as a function of a difference between potentials applied to the first and second switched terminals. A first current mirror couples the differential amplifier to the second switched terminal and controls current flow between a first supply terminal and the second switched terminal as a function of the first current.

Abstract: An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convertor (14) including two transistor current sources (19,24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as a control voltage to a voltage controlled oscillator (12).

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which utilizes gain compensation (90,110) for optimizing phase-locking speed. The sample-and-hold circuit (FIG. 6) also includes circuitry for substantially reducing perturbations at its output. The frequency synthesizer further includes control circuitry (70) and a reference frequency generator (20) for quickly reinitializing the synthesizer in response to a command to change frequency.

Abstract: The IC chip consists of electronic circuits wherein voltage control oscillator whose oscillation frequency is dependent on the product of the resistance value of a resistor element and the electrostatic capacity of a capacitor element is provided; said capacitor element consists of the first variable capacitor; said voltage control oscillator comprises said capacitor consisting of said first variable capacitor; said first variable capacitor is controlled by the output obtained by detecting the output signal of said voltage control oscillator by its phase, using the predetermined reference signal, whereby the oscillation frequency of said voltage control oscillator can be made to agree with the frequency of said reference signal.

Abstract: A phase comparing circuit can be made as a semiconductor integrated circuit for inclusion in a phase-locked loop for generating a phase-locked output signal synchronized with a pilot signal. The phase comparing circuit generates first and second reference signals with reverse polarity about their DC level from the pilot signal and first and second base signals having a DC level substantially the same as the DC level of the reference signals. First and second switching signals with reverse polarity about their DC level are generated from the phase-locked output signal. A plurality of bipolar transistors are operated by the switching signals alternately to provide first and third current paths and second and fourth current paths connecting the reference and base signals to cancel the DC components therefrom. A voltage deriving circuit provides a control signal current path that connects the first and third current paths and the second and fourth current paths.

Abstract: In accordance with the present invention, there is provided a method of substantially flattening the modulation response in a frequency synthesizer. The method includes the steps of generating a synthesized frequency in response to a filtered control signal; scaling the synthesized frequency with a scalar; generating a control signal, having a response substantially the reciprocal of the frequency generation response, and indicative of the phase relationship between a reference frequency and the scaled, synthesized frequency; and filtering the control signal, whereby the interaction of the phase relationship control signal response and the frequency generation response approximates a flat modulation response.

Abstract: An improved charge pump for use in a phase-locked loop is disclosed in which there is only one current source, and in which all switching components pass current in the same direction. The charge pump may thus be constructed entirely of NPN transistors, which makes it possible to embody it in a single integrated circuit chip. The pump up and pump down currents inherently have the same magnitude and transient characteristics, thus minimizing steady-state errors.

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.

Abstract: In the disclosed phase-locked loop circuit, a phase detecting circuit produces a control signal for controlling the frequency of an oscillator according to the phase difference between the output of the oscillator and an input signal. The control signal controls the oscillator only during a specific period of time in which there is a phase difference. This eliminates the need for a low pass loop filter and results in a quick response, stable phase-locked loop circuit.

Abstract: Non-inverting amplifier, with bandpass filter in regenerative feedback path, forms color reference oscillator in a color TV receiver. Phase shift circuit, responsive to an oscillator output, supplies signals to a first phase shifted signal amplifier, which shares a load with the non-inverting amplifier, and is subject to control by complementary outputs of a phase comparator functioning to compare the phase of an oscillator output with the phase of incoming color synchronizing bursts. A voltage comparator, responsive to the respective phase comparator outputs, is periodically enabled by field rate keying pulses. The voltage comparator output controls the charging or discharging of a capacitor during the keying intervals.

Abstract: Disclosed is a circuit providing a controllable effective resistance which comprises of transistor means that provides current at an input node responsive to an input voltage at the input node. The transistor means is coupled to a settable current source which operates to control the effective value of the controllable effective resistance. The invention also includes a filter which employs the controllable effective resistance to vary the breakpoint frequency of the filter. Also, a phase-locked loop apparatus employing the filter is disclosed.

Abstract: The present invention consists of an apparatus comprising a phase locked loop and a frequency loop having a discriminator and a disable. The disable is used to electrically disconnect the frequency loop from the phase locked loop when the phase of the output from the voltage controlled oscillator is within a preset range of the incoming signal. The disable acts to provide an adjusting voltage signal, set by the discriminator, to the phase locked loop when the output and input signal phases are out of the preset range. When they are within the preset range the disable outputs a zero voltage regardless of the input from the discriminator.

Abstract: According to a frequency comparing circuit of the present invention, there is provided a negative switched capacitor circuit having negative equivalent resistance, the value of which is determined according to the reference frequency and the frequency to be compared, and a positive switched capacitor circuit having positive equivalent resistance, the value of which is determined according to the reference frequency. A constant DC voltage is supplied in parallel to one terminal of the two switched capacitor circuits. The respective terminals of the switched capacitor circuits are commonly connected in order to produce the composite current of both output currents of the two switched capacitor circuits. The composite current is integrated by an integrator. Further, there is provided a Schmitt-type oscillating circuit. The oscillating frequency signal from the Schmitt-type oscillating circuit is supplied to the negative switched capacitor circuit.

Abstract: Phase-locked loop, comprising Hartley-type oscillator being formed with a dual-gate field effect transistor (10), whose gates (G.sub.2) and (G.sub.1) constitute the phase-comparison inputs of the loop and whose drain is coupled, optionally via a low-pass loop filter (35), to the input of the feedback circuit, this feedback circuit being connected to the tuning circuit of the oscillator.

Abstract: A voltage controlled oscillator comprises a tank circuit for determining an oscillation frequency, a first circuit for delaying the signal having the oscillation frequency, a second circuit for advancing the signal having the oscillation frequency, the first and second circuit being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit of the series connection, a first gain controlled amplifier amplifying the output from the first circuit, a second gain controlled amplifier amplifying the output from the second circuit, an adder for adding outputs from the first and second gain controlled amplifiers, a control circuit controlling the gains of the first and second gain controlled amplifiers, and a feed-back circuit for feeding the output of the adder to the tank circuit.

Abstract: A PLL circuit arrangement comprising a voltage controlled oscillator, the frequency of which is determined by the alternating charging and discharging of a capacitor, and a phase comparator, to a first input of which the output signal of the voltage controlled oscillator is supplied and to a second input of which a reference signal is supplied and from the output signal of which the signal controlling the oscillator is derived, wherein the capacitor can be charged by means of a current source circuit having a current intensity which can be switched over, the current intensity of the current source circuit can be switched over to a different value during each charging process, and wherein the moment of switching over of the current source circuit can be changed as a function of the output signal of the phase comparator.

Abstract: A phase lock loop oscillator is provided with a voltage controlled oscillator which includes a current controlled oscillator and an input controller therefor that maintains the center frequency of the current controlled oscillator substantially constant irrespective of changes in the gain of the voltage controlled oscillator.

Abstract: In a controlled signal generator or specifically a microwave frequency signal generator, which requires a quieting capacitor, improved switching speed without degrading noise performance is provided by switching out the quieting capacitor during frequency changes, precharging it to the new condition, and then reconnecting it for normal operation. Other error causing current drains are also compensated for.

Abstract: A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal.

Abstract: A phase lock circuit including a phase/frequency detector, a plurality of selectable filters, and a plurality of variable frequency signal generators connected in a loop to lock an output signal to an input signal. An out-of-frequency-range condition detector is provided to facilitate automatic selection of an appropriate in-range combination of filter and signal generator to cause lock to occur.

Abstract: A phase locked loop is disclosed which subtracts an estimated signal from an input signal and operates upon the residual signal. The residual signal is demodulated and applied to a controlled oscillator which produces feedback signals approximately the sine and cosine of the input signal. The cosine feedback signal is multiplied by the residual signal whose resultant signal is a frequency correction signal. The sine feedback signal is multiplied by the residual signal for multiplication again by the sine feedback signal to produce the estimated signal which is amplitude and frequency controlled. This signal is then subtracted from the input signal to reduce the residual signal to near zero.

Abstract: A voltage-controlled oscillator (VCO) comprises a current controlled oscillator (ICO) and control circuitry which independently adjusts the gain (K.sub.v) and free-run or center frequency of the VCO. The control circuitry includes a first current source selected to set the free-run frequency of the VCO and a second current source selected to set the gain (K.sub.v) of the VCO. The current sources are coupled to a common node in a summing/difference configuration. The controlled current generated from the summing/difference configuration is delivered into the ICO. Independent current mirrors are utilized to supply controlled current into the node of the summing/difference configuration.

Abstract: Color reference oscillator comprises a non-inverting amplifier, with positive feedback via a crystal filter linking its output and input. A quadrature phase shift network, coupled to the filter output, delivers phase shifted signals to a pair of independently controlled amplifiers. One of the controlled amplifiers is responsive to control voltage outputs of a burst-responsive phase detector so as to inject phase shifted signals into the oscillator loop, as and when required, to effect synchronization of oscillator with burst component of incoming color television signal. The second of the controlled amplifiers is responsive to a reference DC voltage and to a manually adjustable DC control voltage, and develops a phase shifted signal output, of a magnitude and polarity dependent upon the magnitude and sense of the difference, if any, between the respective DC voltages, for combination with the non-inverting amplifier's output.

Abstract: Color reference oscillator in a color television receiver comprises a non-inverting amplifier, with positive feedback from its output conveyed via a crystal filter to its input. A quadrature phase shift network, coupled to the filter output, develops phase shifted signals which are matrixed with signals derived directly from the non-inverting amplifier to form resultant signals with a phase intermediate the phases of the matrix inputs. Control voltage outputs of a phase comparator, responsive to oscillator signals and to received synchronizing bursts, determine the magnitude and polarity of the output of a controlled amplifier which has at its input the resultant signals produced by said matrixing. The controlled amplifier output, and the output of an inverting amplifier also responsive to said resultant signals, share the load resistor of the non-inverting amplifier.

Abstract: A phase-locked loop provides an output frequency, locked to a multiple N of a reference frequency, responsive to a frequency-control voltage supplied to the output-frequency-generating voltage-controlled oscillator from the output of a differential amplifier. The differential amplifier inputs are provided with voltages sampled from the output of a pair of integrators respectively enabled for integration during complementary, and substantially identical, portions of the phase detector output waveform. Output-frequency-control voltage ripple is substantially reduced, with concomitant reduction of frequency modulation of the output freqeuncy, over the reference frequency period.