Strip Type Patents (Class 333/246)
  • Patent number: 9647312
    Abstract: A transmission line includes an insulator as a base member, a transmission conductor, and a ground layer. A connector is provided at a wiring substrate to fix the transmission line. The transmission line includes a signal columnar conductor having a solid columnar shape integrated with the transmission conductor, and ground columnar conductors having solid columnar shapes integrated with the ground layer. The connector has a through hole corresponding to the signal columnar conductor, and through holes corresponding to the ground columnar conductors. Conductive films are respectively provided on the inner peripheral surfaces of the through holes. The signal columnar conductor is inserted into the through hole, and the ground columnar conductors are respectively inserted into the through holes.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 9, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Masahiro Ozawa
  • Patent number: 9607824
    Abstract: A semiconductor device includes a support substrate, an insulating layer provided on the support substrate, and a semiconductor element provided on the insulating layer. The insulating layer has a lower insulating layer consisting of amorphous boron nitride, and an upper insulating layer provided on the lower insulating layer and including amorphous boron nitride and an hexagonal system boron nitride (h-BN) particles.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: March 28, 2017
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Kazufumi Tanaka
  • Patent number: 9577340
    Abstract: An antenna apparatus includes a waveguide adapter plate for mounting an antenna flange and an RF system-in-package or other IC package. The waveguide adapter plate comprises a first surface and an opposing second surface and a waveguide flange interface. The waveguide flange interface comprises a waveguide channel section extending between the first surface and the second surface and a set of flange mounting holes extending from the first surface to the second surface. The waveguide adapter plate further includes a plurality of substrate alignment pins extending substantially perpendicular from the second surface.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 21, 2017
    Assignee: PERASO TECHNOLOGIES INC.
    Inventors: Mohammad Fakharzadeh, Andrew Charles Andrade, Saman Jafarlou, Bradley Robert Lynch, Mihai Tazlauanu
  • Patent number: 9564868
    Abstract: There is disclosed a balun for dividing an input electrical signal to produce first and second output electrical signals which are substantially out of phase, the balun including: an input port for receiving the input electrical signal; an input line for coupling the input electrical signal to a slotline; and an output line for coupling the first and second output electrical signals to, respectively a first output port and a second output port, the output line having a junction with the slotline; wherein the slotline couples the input electrical signal to the junction, and the junction acts as a divider to produce the first and second electrical signals; in which at least one of the input line, slotline and output line has a width and a length wherein the width varies over the length.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 7, 2017
    Assignee: BAE SYSTEMS plc
    Inventors: Mark Christopher Nguyen, Gareth Michael Lewis, Richard John Harper
  • Patent number: 9530437
    Abstract: A magnetic head has a magnetic head slider that includes a recording element that generates a recording signal magnetic field, a microwave magnetic field generating element that generates a microwave magnetic field, a terminal electrode, and a first transmission line that interconnects the terminal electrode and the microwave magnetic field generating element. A second transmission line is connected to the terminal electrode, the second transmission line being used to transmit a microwave signal from the outside of the magnetic head slider to the magnetic head slider. A capacitor connected to the first transmission line is provided between the terminal electrode and the microwave magnetic field generating element. Accordingly, in the magnetic head, a microwave signal is efficiently propagated.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: December 27, 2016
    Assignee: TDK Corporation
    Inventors: Tomohiko Shibuya, Atsushi Ajioka, Sadaharu Yoneda, Atsushi Tsumita
  • Patent number: 9526165
    Abstract: A multilayer circuit substrate includes: a first signal line and a first ground conductor formed in a first conductive layer; and a second signal line and a second ground conductor formed in a second conductive layer, the second conductive layer facing the first conductive layer via an insulating layer. The first signal line intersects with the second signal line in a plan view of the multilayer circuit substrate, and a space between the first ground conductor and first signal line is smaller in an intersection area of the first and second signal lines than a space in a non-intersection area, and a space between the second ground conductor and second signal line is smaller in the intersection area than a space in the non-intersection area.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 20, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo Saji, Hiroshi Nakamura
  • Patent number: 9526167
    Abstract: A many-up wiring substrate includes an insulating base substrate in which a plurality of wiring board regions are arranged in at least one of a vertical direction and a horizontal direction; a hole disposed in one main surface of the insulating base substrate, and straddling adjacent wiring board regions of the plurality of wiring board regions or straddling the wiring board regions and a dummy region; a conductor disposed on an inner surface of the hole; and a through hole disposed so as to extend from the inner surface of the hole of the wiring board regions to the other main surface of the insulating base substrate.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: December 20, 2016
    Assignee: KYOCERA CORPORATION
    Inventor: Hiroyuki Segawa
  • Patent number: 9525200
    Abstract: The present invention relates to a multi-layer substrate which can be used in a wireless signal transmission/reception apparatus, etc, a through-hole and a first waveguide and a second waveguide which are formed by conductive films enclosing the inner surface of the through-hole are formed on an upper substrate and a lower substrate of the multi-layer substrate, respectively, and an RF signal can be transmitted between an upper surface and a lower surface through the two waveguides. A process of manufacturing a multi-layer substrate by a Surface Mount Technology (SMT) is used, so that a waveguide passing through the multi-layer substrate can be precisely and easily formed.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 20, 2016
    Assignee: MANDO CORPORATION
    Inventors: Jong Gyu Park, Han Yeol Yu
  • Patent number: 9515031
    Abstract: In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: December 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Nevin Altunyurt, Kemal Aygun, Kevin J. Doran, Yidnekachew S. Mekonnen
  • Patent number: 9461677
    Abstract: The present invention is directed to integrated circuits and methods thereof. More specifically, embodiments of the present invention provide a local correction for bending communication line pairs. In an IC package, a pair of communication lines is used to provide a physical link for data communication between two or more components. At regions where the pair of communication lines is bent, the inner bend line is extended in length and shaped to match the length of the outer bend line while preserving integrity of its signal propagation characteristics, thereby providing local phase correction. There are other embodiments as well.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: October 4, 2016
    Assignee: INPHI CORPORATION
    Inventor: Mohammed Ershad Ali
  • Patent number: 9455570
    Abstract: An electrostatic discharge (ESD) limiting device for a coaxial transmission line can include an outer housing or shielding, a ground portion positioned within the outer housing, a center pin positioned within the ground portion, and a beam lead device—such as a Schottky diode or other diode—positioned between the ground portion and the center pin and electrically coupled between the ground portion and the center pin. The ESD limiting device may also include one or more spring members mounted on the ground portion to provide elasticity to the device to maintain signal transmission and grounding within the coaxial transmission line.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: September 27, 2016
    Assignee: TEKTRONIX, INC.
    Inventors: Sahand Noorizadeh, James D. Pileggi, Kyle Grist
  • Patent number: 9426871
    Abstract: The present invention is a wireless communications circuit protection structure, in which a microstrip structure is improved and a combined structure of the microstrip structure and the coplanar waveguide (CPW) structure are improved, so that an external ground and an internal system ground may be totally separated with each other to provide electromagnetic susceptibility (EMS), electrostatic discharge (ESD), electricity leakage proofing ability, and a loss within a specific wireless communications frequency range may satisfy the wireless communications ability requirement.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 23, 2016
    Assignee: MOXA INC.
    Inventors: Chung-En Hung, Hsin-Hung Liu
  • Patent number: 9419341
    Abstract: An IC package includes an IC die disposed at a first surface of a substrate, which includes a signal via extending between first and second metal layers. The first metal layer is proximate to the first surface and includes a first coplanar waveguide. The first coplanar waveguide has a first signal line coupling a die bump to the signal via and has a first ground plane co-planar with the first signal line. The second metal layer is proximate to a second surface and includes a second coplanar waveguide that has a second signal line coupling the signal via to a launcher element and has a second ground plane co-planar with the second signal line. The IC package further includes a waveguide channel aperture comprising a region surrounding the launcher element and which is substantially devoid of conductive material and a via fence disposed at a perimeter of the first region.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 16, 2016
    Assignee: Peraso Technologies Inc.
    Inventors: Saman Jafarlou, Mohammad Fakharzadeh
  • Patent number: 9397381
    Abstract: This electromagnetic coupling structure includes a laminated body that is laminated with an inner dielectric layer interposed between inner conductive layers, one pair of outer dielectric layers facing each other with the laminated body interposed therebetween, and one pair of outer conductive layers facing each other with the one pair of outer dielectric layers interposed therebetween. The one pair of outer conductive layers include wiring portions and conductive patch portions disposed at front ends of the wiring portions, and the conductive patch portions have portions longer than the wiring portions in a direction perpendicular to an extending direction of the wiring portions. In the laminated body, a hole passing through the inner dielectric layer and the inner conductive layers is arranged, and the one pair of outer conductive layers are electromagnetically coupled through a metal film formed inside the hole.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: July 19, 2016
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Yuusuke Kondou, Etsuo Mizushima, Yasushi Watanabe, Yasuyuki Mizuno
  • Patent number: 9362074
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Patent number: 9356397
    Abstract: A connector and an electronic system using the same. The electronic system (100) comprises a first electronic device (102), a second electronic device (200), and a connector (104), the connector being used for connecting the first electronic device and the second electronic device. The first electronic device has a first plane (P10). The second electronic device has a second plane (P20). The first plane and the second plane are not coplanar. The connector comprises multiple terminals (110, 120, 130), electrically connected to the first plane and the second plane respectively. In the connector, a signal terminal is located between a first ground terminal and a second ground terminal, which is beneficial to transmission of a low-noise high-frequency signal in a shielded environment. The connector and the electronic system using the same may transmit a signal between different planes by connecting junctions in different planes.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 31, 2016
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chien-Ming Hsu, Kuo-Chu Liao, Chung-Yuan Kuang, Chiuan Jian Huang
  • Patent number: 9318787
    Abstract: A transmission line structure emplaces at a substrate which includes a first layout layer, a first dielectric layer, a second dielectric layer, a second dielectric layer, and a grounding layer includes a first transmission line pair and at least one second transmission line. The first transmission line pair is set on the first layout layer. The second transmission line is set on the second layout layer. A line of first transmission line pair and a line of the second transmission line cross each other and form a crossing area. A width of the line is narrow. A distance between the first transmission line pair and the second transmission line at the crossing area is less than a distance at an outstanding area.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: April 19, 2016
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventor: Guang-Hwa Shiue
  • Patent number: 9312593
    Abstract: A signal carrier for carrying a signal in a direction within the X-Y plane of a multilayer composite electronic structure comprising a plurality of dielectric layers extending in an X-Y plane, the signal carrier comprising a first transmission line comprising a lower continuous metallic layer and further comprising a row of metallic via posts coupled to the continuous metal layer, wherein the transmission line is separated by a dielectric material from an underlying reference plane.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 12, 2016
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventor: Dror Hurwitz
  • Patent number: 9287220
    Abstract: Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 15, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Yun Tae Nam
  • Patent number: 9270248
    Abstract: An impedance matching network comprises a first and a second signal terminal and a reference potential terminal. The network further comprises a first shunt branch between the first signal terminal and the reference potential terminal, the first shunt branch comprising a variable inductive element and a first capacitive element. The impedance matching network also comprises a second shunt branch between the second signal terminal and the reference potential terminal and comprising a second capacitive element. A series branch between the first signal terminal and the second signal terminal comprises a third capacitive element. Optionally, the first, second, and/or third capacitive element may be implemented as a variable capacitive element. The variable capacitive element comprises a plurality of transistors, wherein a combination of off-capacitances Coff of the transistors provide an overall capacitance of the variable capacitive element as a function of at least two independent transistor control signals.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Anthony Thomas
  • Patent number: 9258886
    Abstract: A printed circuit board includes an outer signal layer, a first ground layer, a first ground layer located below the outer signal layer, an inner signal layer located below the first ground layer, an second ground layer located below the inner signal layer, and a first differential signal transmission pair and a second differential signal transmission pair laid on the outer signal layer and the inner signal layer. A value h is equal to a distance between the inner signal layer and its closest ground layer. A distance between the first pair and the second pair is not more than h×3.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: February 9, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yu-Hsu Lin
  • Patent number: 9253874
    Abstract: A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electromagnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hajase, Nanju Na, Nam H. Pham, Lloyd Walls
  • Patent number: 9236907
    Abstract: An electronic device comprising a laminate constituted by pluralities of insulation layers on which conductor patterns are formed; ground electrodes being formed on an upper-surface-side insulation layer and a bottom-surface-side insulation layer in the laminate; the laminate being partitioned to first and second regions by a first shield constituted by a line of via-holes electrically connecting the upper-surface-side ground electrode to the bottom-surface-side ground electrode; conductor patterns constituting a first filter for a first frequency band and conductor patterns constituting a first balun for the first frequency band being arranged in the first and second regions, respectively; pluralities of terminal electrodes being formed on bottom or side surfaces of the laminate; one of terminal electrodes of the first filter, which acts as an unbalanced port, being adjacent to a terminal electrode of the first balun, which acts as an unbalanced port, with no other terminal electrode than a ground electrode
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: January 12, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Hirotaka Satake
  • Patent number: 9190953
    Abstract: An oscillator and a method of fabricating the oscillator are described. The oscillator includes a resonator with a plurality of transmission lines. An oscillation frequency of the oscillator is independent of at least one dimension of the plurality of transmission lines. The oscillator also includes a negative resistance circuit coupled to the resonator that cancels internal loss resistance of the resonator.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mihai A. Sanduleanu, Bodhisatwa Sadhu
  • Patent number: 9124037
    Abstract: A high speed input/output plug assembly is disclosed having a plug body. A plurality of conductive traces are disposed on a surface of the plug body and connectable to an input/output cable. An electrically conductive grounding layer is positioned within the plug body and electrically insulated from the conductive traces, and has an opening extending through the grounding layer and below the conductive traces.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 1, 2015
    Assignees: TE Connectivity Nederland BV, Tyco Electronics Belgium EC BVBA
    Inventors: Rutger Smink, Lieven Decrock
  • Patent number: 9123738
    Abstract: In a transmission line via structure, a plurality of sub-structures are stacked in a via through the substrate along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion, an outer conductor portion, and at least one dielectric support member. The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume between the outer conductor portion and the center conductor portion. Conductive paste is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 1, 2015
    Assignee: XILINX, INC.
    Inventors: David M. Mahoney, Mohsen H. Mardi
  • Patent number: 9082785
    Abstract: A high-frequency circuit board capable of easily forming a bias line whose resonance frequency is sufficiently separated from operating frequency is provided. On a high-frequency circuit board 100, by electrically connecting a bias line 11 to a high-frequency circuit 10 using blind via holes 106 and 107, it is possible to limit the route that has a possibility of producing resonance only to the bias line connecting the ends 106a and 107a of the blind via holes 106 and 107 to the bias line 11. By adjusting the route length from the end 106a to the end 107a, it is possible to prevent production of resonance in the vicinity of the operating frequency.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 14, 2015
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.
    Inventors: Yoshiyuki Ishida, Sadao Matsushima, Toshihide Fukuchi
  • Patent number: 9064654
    Abstract: Input device manufacture techniques are described. In one or more implementations, a plurality of layers of a key assembly is positioned in a fixture such that one or more projections of the fixture are disposed through one or more openings in each of the one or more layers. The positioned plurality of layers is secured to each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: June 23, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Otto Whitt, III, Matthew David Mickelson, Joel Lawrence Pelley, Amey M. Teredesai, Timothy C. Shaw, Christopher Strickland Beall, Christopher Harry Stoumbos
  • Patent number: 9059491
    Abstract: Disclosed are a microstrip transmission line having a common defected ground structure (DGS) and a wireless circuit apparatus having the same. The microstrip transmission line realizes a common defected ground structure (DGS) and a double microstrip structure, and includes: a first dielectric layer; a first signal line pattern formed on a first surface of the first dielectric layer; a common ground conductive layer formed on a second surface of the first dielectric layer and having a defected ground structure, the first surface facing the second surface; a second dielectric layer having a first surface brought into contact with the common ground conductive layer, and facing the first dielectric layer while interposing the common ground conductive layer between the first dielectric layer and the second dielectric layer; and a second signal line pattern formed on a second surface of the second dielectric layer, the first surface facing the second surface.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: June 16, 2015
    Assignee: Soonchunhyang University Industry Academy Cooperation Foundation
    Inventors: Jongsik Lim, Dal Ahn
  • Patent number: 9055676
    Abstract: A differential signal transmission circuit comprises: an insulating layer; two signal lines provided in parallel on one surface of the insulating layer; a GND line formed on each of outer sides of the two signal lines on the one surface of the insulating layer; and a wiring line layer formed on the other surface of the insulating layer, the differential signal transmission circuit being configured by a double-sided flexible printed circuit board, the signal lines, the GND line and the wiring line layer being formed by a semi-additive method on the insulating layer, and the signal line and the GND line being formed such that a distance S between the two signal lines is greater than a distance D between the signal line and the GND line.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 9, 2015
    Assignee: FUJIKURA LTD.
    Inventor: Hirohito Watanabe
  • Patent number: 9019035
    Abstract: The high-frequency wiring board of the present invention includes: first coplanar lines provided with a first signal line and a first planar ground pattern formed on the same wiring layer as the first signal line; second coplanar lines provided with a second signal line formed on a different wiring layer than the first signal line and a second planar ground pattern formed on the same wiring layer as the second signal line; and a first ground pattern formed on the same wiring layer as the first coplanar lines. The first coplanar lines and the second coplanar lines are connected. At least the first ground pattern and the first planar ground pattern are separated in a region following the second signal line from the connection of the first signal line and the second signal line.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: April 28, 2015
    Assignee: NEC Corporation
    Inventor: Risato Ohhira
  • Publication number: 20150102874
    Abstract: An attenuation reduction structure of a circuit board includes an expanded thickness formed between high frequency signal contact pads and a grounding layer of the circuit board. The expanded thickness is greater than a reference thickness between the grounding layer and high frequency signal lines. The circuit board is made of polyethylene terephthalate (PET) or polyimide (PI). Alternatively, a rigid board including resin and fibrous material or a rigid-flex board is used. The circuit board can be a single-layer circuit board or a multi-layer board formed by combining at least two single-layer circuit boards. A thickness-expanding pad is mounted between the high frequency signal contact pads and the grounding layer or the thickness of a portion of a bonding layer of the circuit board is increased to provide an expanded thickness.
    Type: Application
    Filed: September 5, 2014
    Publication date: April 16, 2015
    Inventors: CHIH-HENG CHUO, KUO-FU SU, GWUN-JIN LIN
  • Publication number: 20150091676
    Abstract: A transmission line includes an insulator as a base member, a transmission conductor, and a ground layer. A connector is provided at a wiring substrate to fix the transmission line. The transmission line includes a signal columnar conductor having a solid columnar shape integrated with the transmission conductor, and ground columnar conductors having solid columnar shapes integrated with the ground layer. The connector has a through hole corresponding to the signal columnar conductor, and through holes corresponding to the ground columnar conductors. Conductive films are respectively provided on the inner peripheral surfaces of the through holes. The signal columnar conductor is inserted into the through hole, and the ground columnar conductors are respectively inserted into the through holes.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventors: Noboru KATO, Masahiro OZAWA
  • Patent number: 8994469
    Abstract: Rectangular-shape resonators as guard traces formed in a region between the victim and aggressor lines are disclosed. No shorting-vias or resistors are required. The rectangular resonators are found to have functions of improving far-end crosstalk (FEXT) and timing jitter in both frequency domain and time domain if the parameters are appropriated selected.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: March 31, 2015
    Assignee: National Taipei University of Technology
    Inventors: Ding-Bing Lin, Chen-Kuang Wang
  • Patent number: 8975987
    Abstract: Provided is a transmission line used to transmit high-frequency electrical signals which can remove a dip-shaped (S21) loss of transmission characteristics due to wall surface resonance, furthermore, can further decrease the size, and can suppress the manufacturing cost at a low level. The transmission line used to transmit high-frequency electrical signals (1) is made up of a signal line (3) used to transmit high-frequency electrical signals which is formed on a front surface (2a) of a dielectric substrate (2), GND electrodes (4) formed outside the signal line (3) and in vicinities of end portions of the front surface (2a), a GND electrode (6) that is electrically connected to the GND electrodes (4) through via holes (5) formed across an entire rear surface (2b) of the dielectric substrate (2), and band-shaped resistors (7) that are formed outside the GND electrodes (4) and in the end portions of the surface (2a) and are electrically connected to the GND electrodes (4).
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 10, 2015
    Assignees: Sumitomo Osaka Cement Co., Ltd., Toru Takada
    Inventors: Yuhki Kinpara, Toshio Kataoka, Toru Takada
  • Patent number: 8970328
    Abstract: Method of manufacturing a transmission line including the steps:—forming an element with at least one longitudinal groove on a surface of the element, the longitudinal groove being defined by two opposite wall portions in the element and having a longitudinal opening adjacent to the surface, and—locating a conductor line in the at least one longitudinal groove. The method is distinguished by the steps:—forming the conductor line from a metal strip upon punching the same from a sheet of metal,—attaching the metal strip to at least one holding device, and—mounting the at least one holding device, with the attached metal strip, on the element, so as to locate the metal strip in the longitudinal groove at a distance from the opposite wall portions of the element. The invention also concerns a transmission line manufactured in accordance with the method.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventor: Björn Lindmark
  • Patent number: 8965304
    Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 24, 2015
    Assignee: Nokia Corporation
    Inventors: Antti Ruha, Tarmo Ruotsalainen, Jussi-Pekka Tervaluoto
  • Patent number: 8957324
    Abstract: The invention relates to a printed circuit for high-frequency signals, and more particularly to interconnect means between transmission lines situated on different faces of the printed circuit. According to the invention, in the vicinity of the interconnect means, the transmission lines each extend in a main direction. The interconnect means comprise two vias each extending along an axis. In a plane containing the main direction of a first of the transmission lines and perpendicular to the face bearing the first transmission line, an orthogonal fix is formed whose abscissa is borne by the main direction of the first transmission line. The abscissae of the axes of the vias or of their projection on the plane, perpendicularly to the plane, are separate.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: February 17, 2015
    Assignees: Thales, Groupe des Telecommunications/Ecole Nationale Superieure des Telecoms Bretagne
    Inventors: Pascal Cornic, Jean-Philippe Coupez, Jérémie Hemery, Julien Boucher
  • Patent number: 8933765
    Abstract: A filter includes: an input terminal to which a fundamental wave signal and a harmonic signal group of the fundamental wave signal are supplied; an output terminal configured to output the fundamental wave signal supplied to the input terminal; a transmission line configured to connect the input terminal and the output terminal; an open-end stub configured to be provided corresponding to an odd harmonic signal among the harmonic signal group, coupled to the transmission line, and has a length corresponding to one quarter of a wavelength of the corresponding odd harmonic signal; a first short-end stub configured to be coupled to the transmission line and has a length corresponding to one quarter of a wavelength of the fundamental wave signal; and a second short-end stub configured to be coupled to the transmission line.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventor: Akihiko Akasegawa
  • Patent number: 8922306
    Abstract: A system can include a first radio frequency (RF) port, a second RF port electrically coupled with the first RF port, a direct current (DC) port, and a bias tee incorporated into a substrate. The bias tee can include multiple capacitors that are each integrated as a catch pad with a layer of the substrate. The bias tee can also include an inductor at least partially integrated with a layer of the substrate.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Tektronix, Inc.
    Inventors: Charles F. Clark, Jr., James D. Pileggi
  • Patent number: 8907739
    Abstract: A differential signal line structure is disposed on a substrate including a signal layer, a filter layer and a grounding layer. The signal layer, the filter layer and the grounding layer are arranged from up to down and in parallel manner. The differential signal line structure accordingly includes a differential signal line group, a first wire and a first grounding circuit; the differential signal line group is disposed in the signal layer; and the first wire is disposed in the filter layer and is arranged in a corresponding position right underneath the differential signal line group. The first grounding circuit is disposed in the grounding layer and is electrically connected to an end point of the first wire through a first via.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Chung Yuan Christian University
    Inventors: Guang-Hwa Shiue, Che-Ming Hsu, Cheng-Fu Hsu
  • Patent number: 8902025
    Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: December 2, 2014
    Assignee: STMicroelectronics SA
    Inventors: Sébastien Pruvost, Frédéric Gianessello
  • Patent number: 8866563
    Abstract: Aspects of the disclosure provide a connector. The connector includes a first signal conductor. The first signal conductor is configured to receive a first electronic signal that includes multiple frequency components. The first signal conductor includes a plurality of conductor portions having portion-dependent impedances. The first signal conductor is configured to transfer the first electronic signal between a via on a circuit board that has a via stub and an electronic device to reduce via stub effects. In addition, in an example, the connector includes a second signal conductor to transfer a second electronic signal. The second electronic signal and the first electronic signal are a pair of differential signals. In an example, the first signal conductor and the second signal conductor have different via stub effects.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 21, 2014
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Liav Ben Artsi
  • Publication number: 20140306776
    Abstract: An RF crossover structure includes a first and second independent transmission lines formed to cross with each other on a same surface of a dielectric substrate; first via-holes connected to the second transmission line so that the second transmission line is connected to a back surface from a front surface of the dielectric substrate and is connected again to the front surface of the dielectric substrate out of a crossing region at which the first and the second transmission lines are crossed. Further, the RF crossover structure includes CPW (Coplanar Waveguide) transmission lines used for a ground plane to improve a signal transmission property at the crossing region.
    Type: Application
    Filed: September 11, 2013
    Publication date: October 16, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Soon Young EOM, Joung Myoun KIM, JeongHo JU, Myung Sun SONG, Jae Ick CHOI
  • Patent number: 8862063
    Abstract: Methods and devices for phase shifting an RF signal for a base station antenna are provided. The device includes a transmission line that has a stationary ground plane coupled to the top of a substrate and a signal line on the bottom of the substrate. The signal line has an input port and an output port. The input port receives the RF signal with a certain phase and travels across the bottom of the substrate to the output port. The RF signal has a different phase at the output port because defected ground structures etched on the stationary ground plane shift the phase of the RF signal. In addition, the device includes a movable ground plane that may cover a portion of the defected ground structures, the substrate, and the stationary ground plane such that the moveable ground plane further adjusts the phase of the RF signal.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Thiagarajar College of Engineering
    Inventors: V. Abhaikumar, S. Raju, S. Deepak Ram Prasath, R. Senthilkumar, P. Vasikaran
  • Patent number: 8848385
    Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 30, 2014
    Assignee: R&D Sockets, Inc
    Inventors: Thomas P. Warwick, James V. Russell
  • Patent number: 8847698
    Abstract: A high-speed feedthrough (HSFT) is disclosed for transmitting a signal having a highest frequency of at least 10 GHz between first and second locations separated by a vertical distance of at least approximately half of the shortest transmitted wavelength, and separated by a horizontal distance. A substrate structure includes multiple stacked layers. An RF transmission line is connected through the structure between the first and second locations for transmitting the signal. The RF transmission line comprises a series of sequentially connected horizontal conductors having lengths less than half of the effective wavelength and vertical conductors having heights less than one quarter of the effective wavelength, thereby spanning the horizontal and vertical distance between the two locations in a stairs-like shape through the structure's layers. Each conductor's geometry may deviate from standard 50 ohm buried strip lines and is optimized for complete 3-dimensional structure.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 30, 2014
    Assignee: JDS Uniphase Corporation
    Inventors: Nikolai Morozov, Zhong Pan
  • Publication number: 20140266516
    Abstract: Disclosed in the present specification is a circuit board. The circuit board includes a first reference plane and a second reference plane, wherein the second reference plane includes a defected ground structure. The circuit board also includes a signal trace coupled to a signal via, wherein the signal trace is disposed above the first reference plane. The circuit board additionally includes a spiral inductor positioned adjacent to the defected ground structure, wherein the spiral inductor is coupled to the signal via.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Kai Xiao, Richard K. Kunze
  • Publication number: 20140253262
    Abstract: Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Taiwan Semiconductor Manufacturing Company Limited
  • Patent number: 8802496
    Abstract: Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 12, 2014
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Akira Ouchi