Abstract: A liquid crystal display device includes a controlling chip and a circuit wire electrically connected to the controlling chip, both disposed on a printed circuit board, and N wire sets and 2N driving chips, all disposed on a glass substrate. N is a positive integer. A characteristic impedance of the circuit wire is equivalent to an output impedance of the controlling chip. The k-th wire set includes 2k?1 peripheral wires, a midpoint of the first peripheral wire in the first wire set is electrically connected to the circuit wire, characteristic impedances of the peripheral wires in the k-th wire set are 2k times the output impedance, k is an integer, and 1?k?N. The driving chips are electrically connected to the N-th wire set, and each of the driving chips adjusts the input impedance according to a control information, so as to make the input impedance 2N times the output impedance.

Abstract: An impedance matching network comprises a first and a second signal terminal and a reference potential terminal. The network further comprises a first shunt branch between the first signal terminal and the reference potential terminal, the first shunt branch comprising a variable inductive element and a first capacitive element. The impedance matching network also comprises a second shunt branch between the second signal terminal and the reference potential terminal and comprising a second capacitive element. A series branch between the first signal terminal and the second signal terminal comprises a third capacitive element. Optionally, the first, second, and/or third capacitive element may be implemented as a variable capacitive element. The variable capacitive element comprises a plurality of transistors, wherein a combination of off-capacitances Coff of the transistors provide an overall capacitance of the variable capacitive element as a function of at least two independent transistor control signals.

Abstract: Provided is an impedance stabilization device having a configuration in which a circuit including a series matching impedance element (11a and 12a (11b and 12b)) and a high-frequency blocking element connected in parallel is inserted in series into at least one of lines (10a (10b)) constituting a power line, and the lines (10a and 10b) are connected via another circuit including a parallel matching impedance element (13) and a low-frequency matching element (14) connected in series. A high-frequency signal passes through the series matching impedance element, a power current passes through the high-frequency blocking element, and the parallel matching impedance element functions as a termination resistor when a terminal on an equipment side is an open end.

Abstract: An impedance matching device includes a first variable capacitor connected to an RF power source and including a first shaft moving linearly, a first linear motion unit axially coupled to the first shaft of the first variable capacitor to provide linear motion, a first insulating joint connecting the first shaft to a first driving shaft of the first linear motion unit, and a first displacement sensor adapted to measure a movement distance of the first driving shaft of the first linear motion unit.

Abstract: Methods and devices for modifying a tunable matching network are disclosed. In one aspect, a method of modifying a tunable matching network can include connecting one or more shunt inductors to a tunable matching network exhibiting parasitic capacitance to ground, whereby high-frequency performance of the tunable matching network is improved.

Abstract: An embodiment of the present invention provides an apparatus, comprising an RF matching network connected to at least one RF input port and at least one RF output port and including one or more voltage or current controlled variable reactive elements; a voltage detector connected to the at least one RF output port via a variable voltage divider to determine the voltage at the at least one RF output port and provide voltage information to a controller that controls a bias driving circuit which provides voltage or current bias to the RF matching network; a variable voltage divider connected to the voltage detector and implemented using a multi-pole RF switch to select one of a plurality of different resistance ratios to improve the dynamic range of the apparatus; and wherein the RF matching network is adapted to maximize RF power transferred from the at least one RF input port to the at least one RF output port by varying the voltage or current to the voltage or current controlled variable reactive elements to

Abstract: Systems and methods are disclosed for returning RF components which exhibit a mismatch with a coupled load. A tuning circuit may be coupled to a signal path of the RF component, wherein the tuning circuit includes a plurality of loads, a switching element associated with each load, wherein each switching element brings the associated load into and out of the signal path, a control line for each switching element, and a phase stage configured to introduce a phase shift, such as 90°, between a first subset of the loads and a second subset of the loads. The disclosure also includes routines for establishing optimum settings for the tuning circuit.

Abstract: A millimeter-wave radio frequency (RF) system, and method thereof for transferring multiple signals over a single transmission line connected between modules of a millimeter-wave RF system. The system comprises a single transmission line for connecting a first part of the RF system and a second part of the RF system, the single transmission line transfers a multiplexed signal between the first part and second part, wherein the multiplexed signal includes intermediate frequency (IF) signal, a local oscillator (LO) signal, a control signal, and a power signal; the first part includes a baseband module and a chip-to-line interface module for interfacing between the baseband module and the single transmission line; and the second part includes a RF module and a line-to-chip interface module for interfacing between the RF module and the single transmission line, wherein the first part and the second part are located away from each other.

Abstract: An antenna device includes an impedance-matching switching circuit connected to a feeding circuit, and a radiating element. The impedance-matching switching circuit matches the impedance of the radiating element as a second high frequency circuit element and the impedance of the feeding circuit as a first high frequency circuit element. The impedance-matching switching circuit includes a transformer matching circuit and a series active circuit. The transformer matching circuit matches the real parts of the impedance and matches the imaginary parts of the impedance in the series active circuit. Thus, impedance matching is performed over a wide frequency band at a point at which high frequency circuits or elements having different impedances are connected to each other.

Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

Abstract: In accordance with a representative embodiment, an impedance matching circuit for use at an output stage of a power amplifier is disclosed. The impedance matching circuit comprises: an input port for receiving a frequency band signal; and a plurality of paths, each path being allocated with a principal band signal to be transmitted therethrough and including a path on-off network and a fixed-value impedance matching network. Depending on a type of the received frequency band signal, the path on-off network is configured to activate a selected one of the plurality of paths by rendering an input impedance of the selected path to have a lower absolute magnitude so that the signal is transmitted therethrough, and to deactivate the remaining paths of the plurality of paths by rendering the input impedance thereof to have a higher absolute magnitude so that the signal is not transmitted therethrough.

Abstract: Adjustable impedance tuning circuitry includes a first impedance matching terminal, a second impedance matching terminal, and a plurality of passive components adapted to match the impedance of the first impedance matching terminal and the second impedance matching terminal. The plurality of passive components includes one or more tunable components adapted to adjust the impedance of the adjustable impedance tuning circuitry to maintain an impedance match between the first impedance matching terminal and the second impedance matching terminal over a variety of operating conditions. Each of the one or more tunable components includes one or more switches adapted to selectively alter the impedance of the tunable component. The one or more switches are integrated onto a single semiconductor die in order to facilitate the performance of the adjustable impedance tuning circuitry over a wide bandwidth.

Abstract: In an integrated circuit having a feedback amplifier circuit composed of the feedback which feedbacks a part of the output signal to the input side in the first stage, a semiconductor integrated circuit of the present invention can suppress the occurrence of the data signal distortion and the gain peaking of the frequency characteristic generated by inter-stage wiring between the first stage and the latter stage. A semiconductor integrated circuit of the present invention includes the first circuit and the second circuit having the first output connected to the first circuit, and the second output that is a signal similar to said first output is outputted from between said first circuit and said second circuit.

Abstract: A Marchand balun circuit includes a Marchand balun, an unbalanced matching circuit, and a balanced matching circuit. The Marchand balun includes an unbalanced terminal, and two balanced terminals. The unbalanced matching circuit includes a first and the second impedances which are connected between the unbalanced terminal and ground in series, and a first resistor which is connected between ground and a connection node of the first and the second impedances. The balanced matching circuit includes a third and a fourth impedances which are connected between one balanced terminal and ground in series, a fifth and a sixth impedance which are connected between the other balanced terminal and ground in series, a second resistor which is connected between ground and a connection node of the third and the fourth impedances, and a third resistor which is connected between ground and a connection node of the fifth and the sixth impedances.

Abstract: A system and method are provided for delivering power to a dynamic load. The system includes a power supply providing DC power having a substantially constant power open loop response, a power amplifier for converting the DC power to RF power, a sensor for measuring voltage, current and phase angle between voltage and current vectors associated with the RF power, an electrically controllable impedance matching system to modify the impedance of the power amplifier to at least a substantially matched impedance of a dynamic load, and a controller for controlling the electrically controllable impedance matching system. The system further includes a sensor calibration measuring module for determining power delivered by the power amplifier, an electronic matching system calibration module for determining power delivered to a dynamic load, and a power dissipation module for calculating power dissipated in the electrically controllable impedance matching system.

Abstract: A balanced-to-unbalanced converter (balun) is provided, including: a converting circuit having a first processing circuit including a first inductor and a first capacitor connected in series, a second processing circuit including a second capacitor and a second inductor connected in series, the second capacitor being electrically connected to the first inductor, and two balanced output ends connected to the first processing circuit and the second processing circuit, respectively; and a preprocessing circuit connected to the converting circuit and including an unbalanced input end for converting real impedance at the unbalanced input end into complex impedance at the balanced output ends. Accordingly, the balun satisfies the need of the wireless communication chips by providing differential signals with complex impedance.

Abstract: A heat dissipating output network (110) is provided. The heat dissipating output network (110) includes one or more impedance elements (204) and one or more capacitors (206), with the one or more impedance elements (204) and the one or more capacitors (206) coupled together in a network configuration, and with the one or more capacitors (206) selected to perform reactance matching and selected to perform a predetermined amount of heat dissipation in the heat dissipating output network (110).

Abstract: Disclosed is a tunable capacitor. The tunable capacitor according to a first embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L. The tunable capacitor according to a second embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: A semiconductor device includes: a terminal configured to input a signal from a signal source; a receiver configured to receive the signal from the signal source through the terminal; and a terminal circuit configured to be coupled between the terminal and an input end of the receiver, and to suppress reflected wave caused by signal reflection at the receiver, wherein impedance of a wire line connecting the terminal and the input end of the receiver, and direct-current impedance of a resistance component included in the terminal circuit are set lower than impedance of an external wire line connected to the terminal.

Abstract: A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells. The input matching network further includes a plurality of resistors coupled respectively between adjacent input terminals of the capacitors.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, a tuning system for a communication device having an antenna, where the tuning system includes at least one first tunable element connected with at least one radiating element of the antenna for tuning the antenna where the adjusting of the at least one first tunable element is based on at least one of a use case associated with the communication device and location information associated with the communication device, and a matching network having at least one second tunable element coupled at a feed point of the antenna, wherein the matching network receives control signals for adjusting the at least one second tunable element to tune the matching network. Additional embodiments are disclosed.

Abstract: A transmission line and method for implementing includes a plurality of segments forming an electrical path and a continuous optical path passing through the segments. Discrete inductors are formed between and connect adjacent segments. The inductors are formed in a plurality of metal layers of an integrated circuit to balance capacitance of an optical modulator which includes the transmission line to achieve a characteristic impedance for the transmission line.

Abstract: A directional coupler utilizes an inductive element of a power amplifier and a coupled conductive element. The inductive element of the power amplifier is a functioning element within the power amplifier and at least part of the inductive element of the power amplifier is disposed in a multi-layer substrate. At least part of the coupled conductive element is disposed in the multi-layer substrate. The coupled conductive element is configured to be inductively coupled to the inductive element of the power amplifier such that the coupled conductive element carries a first RF signal that is representative of a second RF signal within the inductive element of the power amplifier.

Abstract: Disclosed herein is a variable capacitor module, including: a capacitor circuit part including a plurality of capacitor units connected in parallel with each other; and a switching circuit part including a plurality of switch units connected between the plurality of capacitor units, and varying a capacitance of the capacitor circuit part by selecting at least one capacitor unit according to operations of the switch units, and thus, an asymmetric phenomenon where the RF terminal has directivity by gate resistance of the switch can be removed.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, an adaptive impedance matching network having an RF matching network coupled to at least one RF input port and at least one RF output port and comprising one or more controllable variable reactive elements. The RF matching network can be adapted to reduce a level of reflected power transferred from said at least one input port by varying signals applied to said controllable variable reactive elements. The one or more controllable variable reactive elements can be coupled to a circuit adapted to map one or more control signals that are output from a controller to a signal range that is compatible with said one or more controllable variable reactive elements. Additional embodiments are disclosed.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, an apparatus having an RF matching network including one or more variable reactive elements, where the RF matching network has a first port coupled to a transceiver and second port coupled to an antenna. The RF matching network can modify signal power transferred between the first port and the second port according to one or more bias signals applied to the one or more variable reactive elements to vary a variable impedance of the RF matching network. The one or more variable reactive elements are coupled to a circuit that maps one or more control signals to the one or more bias signals, and wherein the one or more control signals are generated by a controller according to a mode of operation of a communication device. Additional embodiments are disclosed.

Abstract: Method and circuit topology for an impedance compensation circuit (ICC), for compensating a DC voltage regulator circuit (RC). The ICC comprises individual components that are workable in combination with an inherent output impedance characteristic of the RC. The components are optimizable for providing a substantially uniform AC output impedance characteristic and impedance phase over a first defined frequency range and an operating idle current under a load, by creating a condition where a source impedance and a load impedance are complex conjugates. The source impedance is a series combination of the inherent output impedance characteristic of the RC and a first impedance due to a first portion of the individual components. The load impedance is a parallel combination of a second impedance due to a second portion of the individual components and the load, when the ICC is configured with the RC and the load.

Abstract: Disclosed is a tunable capacitor. The tunable capacitor according to a first embodiment of the present invention includes: a variable capacitor unit placed between a first terminal and a second terminal; and a bypass switch which on/off controls a bypass connection between the first terminal and the second terminal, wherein the variable capacitor unit and the bypass switch are integrated on one semiconductor die or on one module. The tunable capacitor according to a second embodiment of the present invention includes: a variable capacitor unit placed between a first terminal and a second terminal; an impedance tuner placed between aground terminal and either the first terminal or the second terminal; and a tuning switch which on/off controls the connection between the variable capacitor unit and an impedance tuner, wherein the variable capacitor unit, the impedance tuner and the tuning switch are integrated on one semiconductor die or on one module.

Abstract: An electronic balun circuit is provided for converting a single-ended signal into a differential signal and vice versa, comprising a center-tapped inductor having a first node, a center-tap coupled to a constant voltage source, and a second node. A first impedance circuit is coupled with the first node and with a line carrying single-ended signal to and from the first node. A second impedance circuit is coupled with the second node. The first node receives the single-ended signal to produce a differential signal at the first and second nodes. The first and second nodes receive the differential signal to produce the single-ended signal at the first node. Both first and second impedance circuits have an impedance of 2RL, resulting in a total effective impedance of Rin for achieving an impedance match between the line and the first node. Furthermore, a passive network is added to balance the balun.

Abstract: An electrical filter structure for forwarding an electrical signal from a first filter port to a second filter port in a frequency-selective manner includes a filter core structure having a working impedance, wherein the working impedance is different from a first characteristic port impedance of a first filter port, and also different from a second characteristic port impedance of a second filter port. The electrical filter structure also includes a first matching arrangement electrically coupled between the first filter port and the filter core structure and a second matching arrangement electrically coupled between the second filter port and the filter core structure.

Abstract: A high-frequency circuit according to one embodiment of the present invention includes a plurality of transistors, a plurality of input matching circuits, a plurality of output matching circuits, a plurality of resistors, and low-frequency oscillation suppressing circuits. The transistors are arranged on a substrate in parallel. The input matching circuits and output matching circuits are arranged on insulating substrates and connected to the transistors. The oscillation suppressing circuits are a circuit configured by a filter circuit having a desired transmission band and a resistor, and are connected to gate terminals of transistors located on both sides of the transistors, respectively. Each of resistors is formed to include a position closest to the transistor between the input matching circuits and between the output matching circuits. Furthermore, each of resistors has a length at which the oscillation suppressing circuit can suppress oscillation at the lowest frequency in the transmission band.

Abstract: An impedance matching network includes an impedance matching circuit for dynamically matching an impedance between a source and a load. Matching is done by varying the real part and the imaginary part of the impedance of the impedance matching circuit independently.

Abstract: In an impedance matching circuit selectively operable in a normal matching mode and a protection mode, the impedance matching circuit includes a set of reactances in a first reactance arrangement configured to transform an impedance of a load to an impedance within a range of a nominal impedance of an HF generator in the normal matching mode, and a PIN diode switch having a first invariable switching state in the normal matching mode and a second switchomg state that reconfigures the set of reactances into a second reactance arrangement in the protection mode, such that the second reactance arrangement is configured to transform the impedance of the load to prevent damage to the HF generator or to transmission circuitry arranged between the HF generator and the load.

Abstract: Disclosed is an impedance matching device. Variable devices of the impedance matching device installed in a mobile terminal, such as a portable terminal, are configured to have a MEMS structure. The MEMS structure and other components are integrated as one package, so the manufacturing cost is reduced and the manufacturing efficiency is improved.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: A transmission line and method for implementing includes a plurality of segments forming an electrical path and a continuous optical path passing through the segments. Discrete inductors are formed between and connect adjacent segments. The inductors are formed in a plurality of metal layers of an integrated circuit to balance capacitance of an optical modulator which includes the transmission line to achieve a characteristic impedance for the transmission line.

Abstract: Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Abstract: An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.

Abstract: In accordance with this invention the above and other problems are solved by a switching apparatus and method that uses a switching circuit having a pair of parallel solid-state diodes (e.g., PN or PIN diodes), one of which is connected to a transistor (e.g., power MOSFET or IGBT), to switch a capacitor (or reactance element) in or out of a variable capacitance element (or variable reactance element) of an impedance matching network. Charging a body capacitance of the transistor reverse biases one of the two diodes so as to isolate the transistor from the RF signal enabling a low-cost high capacitance transistor to be used. Multiple such switching circuits and capacitors (or reactance elements) are connected in parallel to provide variable impedance for the purpose of impedance matching.

Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.

Abstract: An impedance matching network includes a first terminal, a second terminal, and a reference potential terminal. The impedance matching network further includes a first shunt branch between the first terminal and the reference potential terminal, the first shunt branch including a capacitive element. The impedance matching network also includes a second shunt branch between the second terminal and the reference potential terminal, the second shunt branch including an inductive element. Furthermore, the impedance matching network includes a transmission line transformer with a first inductor path and a second inductor path, wherein the first inductor path connects the first terminal and the second terminal. An alternative impedance matching network includes a transformer and an adaptive matching network. The transformer is configured to transform an impedance connected to a first port so that a corresponding transformed impedance lies within a confined impedance region in a complex impedance plane.

Abstract: Systems and methods are provided for reading an associated state of a qubit. A first soliton is injected along a first Josephson transmission line coupled to the qubit. A velocity of the first soliton is selected according to a physical length of the qubit and a characteristic frequency of the qubit. A second soliton is injected at the selected velocity along a second Josephson transmission line that is not coupled to the qubit. A delay associated with the first soliton is determined relative to the second soliton.

Abstract: This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

Abstract: An output circuit with an integrated directional coupler and impedance matching circuit is disclosed. In an exemplary design, an apparatus includes a switchplexer and an output circuit. The switchplexer is coupled to at least one power amplifier. The output circuit is coupled to the switchplexer and a load (e.g., an antenna) and includes a directional coupler and an impedance matching circuit sharing at least one inductor. The output circuit performs impedance matching for the load. The output circuit also acts as a directional coupler and provides an input radio frequency (RF) signal as an output RF signal and further couples a portion of the input RF signal as a coupled RF signal. Reusing the at least one inductor for both the directional coupler and the impedance matching circuit may reduce circuitry, size, and cost of the wireless device and may also improve performance.

Abstract: Embodiments of circuits, apparatuses, and systems for a lattice matching network are disclosed. Embodiments may include a power amplifier to provide single-ended amplification of a radio frequency signal. A lattice matching network may be coupled with the power amplifier and may transform a source impedance associated with an output of the power amplifier to a load impedance. In some embodiments, the lattice matching network may include first and second arms coupled in parallel between the power amplifier and an output node. The first arm may include a serial high-low network and the second arm may include a serial low-high network. The serial high-low network and the serial low-high network may provide a passband response with respect to the radio frequency signal. The serial high-low network and serial low-high network may include one or more Pi networks. Other embodiments may be described and claimed.

Abstract: An electro-mechanical VHF harmonic load pull tuner is made as a cascade of three independent tuning sections, each including three adjustable shunt air capacitors inter-connected using coaxial cables of appropriate length, or one section of nine shunt capacitors inter-connected using coaxial cables; each capacitor is adjustable to at least 20 values (states); the tuner creates independently controllable impedances at three (harmonic) frequencies in the frequency range between 10 and 150 MHz. An Error Function-based optimization algorithm allows impedance tuning at three frequencies independently, by optimized searching among the more than 209?512,000,000,000 possible combined tuner states. This allows matching the output of VHF transistors and amplifiers at the fundamental and harmonic frequencies. Stepper motors, drivers and control software are used to automate, calibrate and use the harmonic tuner in an automated harmonic load pull measuring setup.

Abstract: A circuit includes a passive element having an impedance. An active circuit can be configured to receive an impedance signal associated with the impedance. The impedance includes a real portion and an imaginary portion. The active circuit removes at least a portion of the real portion of the impedance signal. The circuit can be utilized in a wide array of applications including radio applications.

Abstract: An impedance converting circuit module includes a first matching circuit, a feeding-circuit-side matching circuit interposed between the first matching circuit and a feeding circuit, and an antenna-side matching circuit interposed between the first matching circuit and a radiating element. The feeding-circuit-side matching circuit performs impedance matching between a feeding port of the feeding circuit and the first matching circuit, and the antenna-side matching circuit performs impedance matching between a port of the radiating element and the first matching circuit.

Abstract: Methods and apparatus for a resonant transmit/receive switch with transformer gate/source coupling. The resonant transmit/receive (T/R) switch includes a switchable inductor having a first inductance value for use in receive (Rx) mode and a second inductance value for use in transmit (Tx) mode. The first inductance value is used for input matching to a low noise amplifier in Rx mode. The second inductance value is selected to resonant with parasitic capacitance of the antenna port to produce a high impedance in Tx mode. In one implementation, the switchable inductor is gate sourced coupled to at least one of first and second inductors of a low noise amplifier (LNA), thereby allowing use of smaller inductors due to the resulting coupling factor.