Having Variable Sampling Rate Patents (Class 341/123)
  • Patent number: 7821437
    Abstract: A method includes sensing a process parameter to generate a sensor signal that includes a process signal and line noise components, digitizing the sensor signal at a sample rate, detecting line noise zero crossings in the sensor signal, determining a line noise frequency as a function of the detected line noise zero crossings, and adjusting the sample rate as a function of the line noise frequency to reduce an impact of line noise on the digitized sensor signal.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 26, 2010
    Assignee: Rosemount Inc.
    Inventors: Jason Harold Rud, Douglas Wayne Arntson
  • Patent number: 7738565
    Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: June 15, 2010
    Assignee: Magnetic Recording Solutions, Inc.
    Inventors: Victor Pogrebinsky, Vladimir Pogrebinsky
  • Patent number: 7729441
    Abstract: A method for generating a modulated carrier signal with reduced bit error rates based on a plurality of data symbols. A plurality of data symbols are received, and a digital input signal is generated based on the plurality of data symbols. The digital input signal are filtered to produce a digital output signal including a phase characteristic. The phase characteristic of the digital output signal remains close to the desired symbol phase for substantial portion of the symbol period. A carrier signal is modulated using the digital output signal to produce the modulated carrier signal.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: June 1, 2010
    Assignee: Pine Valley Investments, Inc.
    Inventor: Richard Duane Taylor
  • Patent number: 7663457
    Abstract: Magnetically latching and releasing a voice coil actuator for controlling electrical switchgear. The voice coil actuator includes a voice coil magnet disposed on a common longitudinal axis with respect to a voice coil assembly. A coil of the voice coil assembly exerts a magnetic force on the voice coil assembly, thrusting the voice coil assembly towards the voice coil magnet. At least one pair of latching members mounted to the voice coil assembly creates a permanent magnet circuit between the latching members and the voice coil magnet. The permanent magnet circuit maintains the position of the voice coil assembly relative to the voice coil magnet, even when power to the coil is removed. This latch can be released by applying a current in the coil or by applying an external, physical force to a member coupled to the voice coil assembly.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 16, 2010
    Assignee: Cooper Technologies Company
    Inventors: Bela Peter Szeifert, Michael Peter Dunk
  • Patent number: 7656332
    Abstract: A method and apparatus for a multi-mode and multi-rate telemetry transmitter includes a digital baseband lineup, a digital-to-analog converter (“DAC”), and an analog reconstruction filter. The digital baseband lineup may be programmed to any desired bit rate, enabling the transmitter to support multi-rate capabilities. Different coefficients and numerical values may be programmed in the digital baseband lineup to support any desired modulation scheme, enabling the transmitter to support multi-mode capabilities. The digital baseband lineup may be designed by implementing up-sampling stages, down-sampling stages, and digital filters in a variety of arrangements.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: February 2, 2010
    Assignee: Cobham Defense Electronic Systems Corporation
    Inventor: Walid Khairy Mohamed Ahmed
  • Patent number: 7629907
    Abstract: A method of modulating the sampling period of a sampled system with a factor N, and correcting the data stream of the sampling system with the same factor N, thus minimizing distortion artifacts induced by sample frequency modulation. At least a one-period delay from receipt of a new data stream value is used to avoid heterodyning with the incoming stream.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: December 8, 2009
    Inventor: Larry Kirn
  • Patent number: 7579970
    Abstract: In a timing recovery method, two consecutive sampling values may be generated based on a sampled input signal. The input signal may be sampled according to a phase interval of a sampling clock. A slope between the two consecutive sampling values may be calculated, and a difference between a target slope and the calculated slope may be determined. A phase of the sampling clock may be compensated based on the difference between the target slope and the calculated slope.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: August 25, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: II-Won Seo, Jae-Hwan Ahn
  • Patent number: 7573409
    Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: August 11, 2009
    Assignee: VNS Portfolio LLC
    Inventors: Charles H. Moore, Leslie O. Snively, John Huie
  • Patent number: 7561084
    Abstract: A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value based on the magnitude of a previous error value for a previous loop iteration, plus margins conversion housekeeping and the step size of the next loop iteration. At a timing prior to a filter reading the error value that equals the number of clock cycles set by the predictor, a timing unit triggers the analog-to-digital conversion, reducing loop latency and improving performance.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: July 14, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Hee Wong
  • Publication number: 20090174585
    Abstract: A method for converting analog values into digital form comprises comparing a current analog sample value with an analog input value to produce an outcome, generating a count value based on the outcome, the count value increasing upon successive like outcomes and being reset to an initial count value upon successive unlike outcomes, adding or subtracting the count value to/from a current digital sample value to generate a next digital sample value, the adding or subtracting being based on the outcome, and converting the next digital sample value to the current analog sample value.
    Type: Application
    Filed: March 6, 2009
    Publication date: July 9, 2009
    Inventor: Allan L. Swain
  • Patent number: 7523238
    Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: April 21, 2009
    Assignee: Teradyne, Inc.
    Inventor: Jason Messier
  • Patent number: 7515076
    Abstract: A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: April 7, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Rahul Singh, Prashanth Drakshapalli, Jie Fang, Edwin De Angel, Mohit Sood
  • Patent number: 7495591
    Abstract: Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 24, 2009
    Assignee: Agilent Technologies, Inc.
    Inventors: Joachim Moll, Heiko Schmitt, Michael Fleischer-Reumann
  • Patent number: 7492293
    Abstract: An analog-to-digital converter can use a variable sampling rate. By using a variable sampling rate analog-to-digital converter and an anti-aliasing filter lower sampling rates, and accordingly, generally lower power consumption may be achieved. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over-sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or a signal farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 17, 2009
    Assignee: Olympus Communication Technology of America, Inc.
    Inventors: Robert Townsend Short, Ghobad Heidari-Bateni, Layne Lisenbee
  • Patent number: 7477170
    Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce a
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: January 13, 2009
    Assignee: Analaog Devices, Inc.
    Inventor: Ganesh Ananthaswamy
  • Patent number: 7466247
    Abstract: Methods for processing waveforms may include decimating an over-sampled waveform by identifying samples for which the sample's position within a data period indicates that is closest to a selected time within a data period. In some example applications, the selected time may be determined as a preferred time to sample the waveform within a data period. In an illustrative example, a sequence of samples representing an over-sampled waveform may be reduced by identifying a sample in each data period that is closest in time to the selected time. In another illustrative example, a sample within each data period may be identified if it falls within a range that is a function of the selected time within the data period and an integral ratio of a sample period to the data period. The identified samples may be used to reconstruct the original waveform with fewer samples than the over-sampled waveform.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: December 16, 2008
    Assignee: LeCroy Corporation
    Inventor: Mark S. Gorbics
  • Patent number: 7456765
    Abstract: A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: November 25, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Publication number: 20080284625
    Abstract: A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jomy G. Joy, Ankit Seedher, Ayaskant Shrivastava
  • Patent number: 7439889
    Abstract: The ?? AD converter includes: a sampling section for sampling an input signal at each cycle Ts; an AD conversion section for performing AD conversion of the input signal; a DA conversion section for performing DA conversion of an output of the AD conversion section; and a loop filter for integrating a difference obtained by subtracting an output of the DA conversion section from an output of the sampling section so as to output the integrated difference to the AD conversion section, wherein the sampling section includes two sampling circuits disposed parallel to each other, and the two sampling circuits respectively operate at timings different from each other, and each of the sampling circuits delays the input signal so as to output the delayed input signal.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 21, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshihisa Fujimoto
  • Patent number: 7439897
    Abstract: Staggered interleaved Nyquist regions associated with differing ADC clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered interleaved Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable anti-aliasing filters associated with each Nyquist region and its ADC clock rate are used to enforce the staggered Nyquist regions and their various guard bands. For example, and neglecting guard bands, an initial raw band of operation RB1 may be the First Nyquist region for a basic sampling frequency Fs. An adjacent raw band of operation RB2 that overlaps RB1 may be the Second Nyquist region for an alternate sampling frequency 2Fs/3. An adjacent raw band of operation RB3 that overlaps RB2 may be the Second Nyquist region for the basic sampling frequency Fs. These raw bands interleave and overlap: RB1: DC to Fs/2 1st Nyq. for FCLK = Fs RB2: (2/3)Fs ? to 2(2Fs/3)/2 = 2nd Nyq.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: October 21, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Joseph M. Gorin, Kenneth D. Poulton
  • Publication number: 20080231484
    Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.
    Type: Application
    Filed: May 7, 2007
    Publication date: September 25, 2008
    Inventors: Charles H. Moore, Leslie O. Snively, John Huie
  • Patent number: 7424275
    Abstract: A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: September 9, 2008
    Assignee: Silicon Laboratories, Inc.
    Inventor: Shyam S. Somayajula
  • Patent number: 7379834
    Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal, the master clock frequency measurement biased by a past operating mode selection, and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In an additional embodiment, the measurement circuitry biases the master clock frequency measurement based on a past master clock frequency measurement.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: May 27, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson
  • Patent number: 7353126
    Abstract: A method of determining coherent test conditions is disclosed. The method includes receiving constraints from a user, wherein the constraints include desired test conditions, desired tolerances for the desired test conditions, and desired instrument. Further, the method includes determining the coherent test conditions using the constraints. Moreover, the method includes providing each determined coherent test condition to the user, wherein each determined coherent test condition includes a calculated sampling frequency and a calculated analog frequency.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: April 1, 2008
    Assignee: Credence Systems Corporation
    Inventor: Chris Oberhauser
  • Patent number: 7352167
    Abstract: An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 1, 2008
    Assignee: Tektronix, Inc.
    Inventors: Steven K. Sullivan, Kristie Veith, Terrance R. Beale
  • Patent number: 7352303
    Abstract: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 1, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Patent number: 7345603
    Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. In some embodiments, the apparatus (10) generally includes a receiving element (12) operable to receive an input signal, an integrate/dump circuit (14), a sampling element (16), and a processor (18). The integrate/dump circuit (14) is operable to integrate at least a portion of the received signal to provide an integrated signal and the sampling element (16) is operable to sample the integrated signal at a first sampling rate which is less than the Nyquist rate for the input signal. The processor (18) is operable to form a compressed sensing matrix utilizing a first set of time indices corresponding to the first sampling rate, form a measurement vector utilizing at least a portion of the sampled signal, and reconstruct at least a portion of the input signal utilizing the compressed sensing matrix and the measurement vector.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: March 18, 2008
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Mark L. Wood, Chen-Chu Alex Yeh, Gerald Lothair Fudge
  • Patent number: 7339509
    Abstract: A signal sampling system includes an input signal and a plurality of samplers. The plurality of samplers produces a plurality of sample output signals. Each sampler from the plurality of samplers samples the input signal to produce a corresponding sample output signal from the plurality of sample output signals. Each sampler samples the input signal with a sampling pulse having a sampling aperture. A first sampling aperture used by a first sampler from the plurality of samplers to sample the input signal differs in duration from a second sampling aperture used by a second sampler from the plurality of samplers to sample the input signal.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: March 4, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Mark Joseph Woodward, Marlin Viss
  • Patent number: 7327302
    Abstract: An asynchronous sampling arrangement utilizes sampling of both a high speed data signal and a trigger (clock) signal. The data signal may be either an optical signal or an electrical signal. The data and trigger signals are sampled in parallel by two separate gates, the gates based on the same strobe frequency. The samples corresponding to the trigger signal are then processed through an algorithm that determines the time-base related to the sampled signal. This established time-base is then used to reconstruct the sampled version of the high data rate input signal waveform.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: February 5, 2008
    Assignee: PicoSolve Inc.
    Inventors: Mathias Westlund, Peter Andrekson
  • Patent number: 7307562
    Abstract: Methods and structures are provided for generating a digital display signal in response to an analog display signal whose amplitude varies at a pixel rate and in response to a synchronization signal that defines spatial order for the analog display signal. The structures include a transform generator for providing a Fourier transform of the digital display signal and a transform analyzer which generates frequency and phase control signals in respective response to the frequency of an error spectral component and amplitudes of image spectral components in the transform. The frequency and control signals are applied to respectively adjust the sample rate of the sample clock and alter the phase of the sample clock.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: December 11, 2007
    Assignee: Analog Devices, Inc.
    Inventor: Willard Kraig Bucklen
  • Patent number: 7298296
    Abstract: A real-time sample rate converter having a non-polynomial convolution kernel provides reduction in die area and power for performing sample rate conversion in real-time. A non-polynomial convolution kernel, which may be a gaussian operator, is used to determine output sample values from values of an incoming stream of values. If the input sample rate is higher than the output sample rate, the input sample stream is convolved with the gaussian kernel and then decimated to yield the output stream. If the input sample rate is lower than the output sample rate, the input stream is resampled to a small multiple of the output sample rate and convolved with the gaussian kernel to produce the output sample stream directly.
    Type: Grant
    Filed: September 2, 2006
    Date of Patent: November 20, 2007
    Assignee: Cirrus Logic, Inc.
    Inventor: Gautham Devendra Kamath
  • Patent number: 7292168
    Abstract: An implantable medical device uses a sampling scheme to obtain digital representation from analog signals. The analog signals represent intracardiac activity. Generally, a detector detects the amplitude of the analog signals and generates first and second difference signals. The first difference signal is generated after detection of significant changes in the analog signal amplitude. The second difference signal is generated upon confirmation of the absence of significant changes in the analog signal amplitude over a predetermined period of time. A frequency selection is implemented to select the sampling frequency based on the first and second difference signal.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: November 6, 2007
    Assignee: Medtronic, Inc.
    Inventors: Willem A. Wesselink, Henricus W. M. De Bruyn
  • Patent number: 7289049
    Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. The method generally comprises forming a first compressed sensing matrix utilizing a first set of time indices corresponding to a first sampling rate, forming a second compressed sensing matrix utilizing a plurality of frequencies and a second set of time indices corresponding to a second sampling rate, forming a combined compressed sensing matrix from the first compressed sensing matrix and the second compressed sensing matrix, and reconstructing at least a portion of the input signal utilizing the combined compressed sensing matrix. The first and second sampling rates are each less than the Nyquist sampling rate for the input signal.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: October 30, 2007
    Assignee: L3 Communications Integrated Systems L.P.
    Inventors: Gerald Lothair Fudge, Mark L. Wood, Chen-Chu Alex Yeh
  • Patent number: 7286069
    Abstract: A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: October 23, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Patent number: 7253756
    Abstract: A method and a device for dynamically accelerating an analog-to-digital converter (ADC) are provided. The device for dynamically accelerating ADC is capable of detecting the sampling frequency and controlling the maximum conversion rate by boosting the current into the ADC such that the maximum conversion rate of the ADC is larger than or equal to the sampling frequency. The efficiency of the ADC is optimized.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: August 7, 2007
    Assignee: Mstar Semiconductor, Inc.
    Inventor: Chih-Shiun Lu
  • Patent number: 7236109
    Abstract: A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: June 26, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson
  • Patent number: 7236532
    Abstract: A method of communicating across a channel includes receiving information having a known bandwidth and a known spectrum. The information is preferably in the form of a multicarrier modulated signal, e.g., a DMT signal. In one aspect, this information is received at a receiver having a reduced channel bandwidth. An aliasing spectrum can be calculated based on the known spectrum and the frequency difference between the known bandwidth and the reduced-channel bandwidth. The received information can then be modified based upon the aliasing function to compensate for alias distortion. For example, the received information can be modified by modifying the noise component or signal-to-noise ratio of the received information.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 26, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Fernando A. Mujica, Michael O. Polley, Arthur J. Redfern, Nirmal C. Warke, Yaser M. Ibrahim
  • Patent number: 7218261
    Abstract: A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: May 15, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jin-Sheng Gong, Yu-Pin Kuo, Yu-Pin Chou, Hung-Jen Chu
  • Patent number: 7212139
    Abstract: A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is operative to reduce the requirements for or completely eliminate the need for the anti-aliasing filter by dynamically modifying the sub-sampling rate (or decimation ratio). Rather than maintain a constant sampling rate (or decimation ratio), the sampling rate (or decimation ratio) is randomized such that its average remains at the nominal value and the effective jitter is low enough for the low rate (or low decimation ratio) system to tolerate. This smears or spreads interfering signals across the spectrum resulting in a noise floor at a significantly reduced level much lower than that of the original interferer signal. The interfering signals are reduced to background noise wherein the level of the resulting noise floor is not nearly as strong as the original interfering signal.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Ran Katz
  • Patent number: 7193543
    Abstract: In one set of embodiments, a temperature measurement system may include an analog to digital converter (ADC) to produce digital temperature readings according to a difference base-emitter voltage (?VBE) developed across a PN-junction. A clock generating circuit may be configured to provide a sampling clock used by the ADC, which in some embodiments may be a delta-sigma ADC, in performing the conversions. The clock generating circuit may be configured to change the frequency of the sampling clock a specified number of times within each one of the one or more conversion cycles to reduce an error component in the temperature measurement, where the error component is produced by an interfering signal, such as an electromagnetic interference (EMI) signal being coherent with the sampling clock, and/or a noise residing on the voltage supply and also being coherent with the sampling clock.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: March 20, 2007
    Assignee: Standard Microsystems Corporation
    Inventors: Scott C. McLeod, Kenneth W. Gay
  • Patent number: 7193549
    Abstract: A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: March 20, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, Giri Rangan, Aryesh Amar
  • Patent number: 7190752
    Abstract: The scale and complexity of an apparatus is reduced by omitting a clock extraction section. The apparatus includes: a sampling pulse train generation device which generates an optical or electrical sampling pulse train, independently of an input optical or electrical data signal with a bit rate f0(bit/s), and which has a repetition frequency f1(Hz); a data signal sampling device which samples the data signal in accordance with the sampling pulse train to obtain a sampled signal; a voltage retaining device which converts the sampled signal, and stores pieces of electrical digital data; an electrical signal processing device which reads the digital data at once or sequentially to obtain a signal eye-diagram and evaluates optical data signal quality parameters; and a trigger signal generation device which applies triggers indicating the start/finish of data acquisition and data read to the voltage retaining device and the electrical signal processing device, respectively.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 13, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ippei Shake, Hidehiko Takara
  • Patent number: 7132965
    Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 7, 2006
    Assignee: Teranetics, Inc.
    Inventors: Sandeep Kumar Gupta, Oleksly Zabroda
  • Patent number: 7132766
    Abstract: A technique for controlling a switching circuit, such as a relay, includes one or more sensing circuits that generate signals based upon the presence of an actuating object and upon a randomly applied strobe signal. The generated signals are sampled and are used as a basis for determining the state of an output signal. The sensing circuit may generate the signals based upon capacitive coupling with the actuating object. The randomization of the sampling provides enhanced immunity to periodic or cyclic noise. Where more than one sensing circuit is included, the output of the circuits may be considered together for determining the state of the output signal, such as based upon predetermined ranges of signal levels. Signals of the sensing circuit may be sampled in the absence of the strobe to provide an indication of the relative noise level. If the noise level is determined to be elevated, the output signal may not change states.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: November 7, 2006
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Michael Lee Gasperi, David Dale Brandt, Thong T. Nguyen
  • Patent number: 7123652
    Abstract: A digital filtering system for filtering sample data includes a delay network for delaying input sample data to provide multiple delayed sample data outputs. The filtering system also includes a filter network represented by a decomposed coefficient weighting matrix for processing the delayed sample data outputs. A processor produces a filtered output by computing a weighted product summation of the delayed sample data outputs and the coefficient weighting matrix. The decomposed coefficient weighting matrix is derived by factoring a first coefficient weighting matrix with a common row factor and/or sparse matrix or by factoring based on matrix row or column symmetry.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 17, 2006
    Assignee: Thomson Licensing S.A.
    Inventor: David Lowell McNeely
  • Patent number: 7113117
    Abstract: An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several parallel connected capacitors for different time durations with at least some non-overlap. In an embodiment, such an approach is used in a switched capacitor amplifier circuit of an ADC. The capacitors in that embodiment start charging at the same time instance, but stop charging at different time instances due to the design of associated switches and control signals.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Visvesvaraya A Pentakota, Nitin Agawal
  • Patent number: 7057539
    Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: June 6, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson
  • Patent number: 7049988
    Abstract: A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: May 23, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson
  • Patent number: 7015842
    Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: March 21, 2006
    Assignee: Teranetics, Inc.
    Inventors: Sandeep Kumar Gupta, Oleksiy Zabroda
  • Patent number: 6952461
    Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, includes a storage device 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the writable address, and an interpolation processing unit 14 for interpolating the data read-out from the storage device 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a writable address and a readable address in the storage device 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: October 4, 2005
    Assignee: Sony Corporation
    Inventors: Nobuyuki Yasuda, Kazunobu Ohkuri