Abstract: To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

Abstract: A system and methods for synchronizing quantized sampled data in a monitoring device. A variable frequency output signal is coupled to an analog to digital converter. A fixed frequency clock is coupled to the analog to digital converter. The analog to digital converter samples the output signal at a fixed frequency to produce high speed samples. A group of initial high speed samples is stored from the analog to digital converter over a fixed window of time. The group of initial high speed samples is interpolated to produce a group of fewer low speed samples from the initial group of high speed samples over the fixed window of time. The group of low speed samples is stored as a representation of the variable frequency output signal.

Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

Abstract: Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time. The SRC determines relative timing of generated output samples based on non-approximated integer components that are recursively updated. The SRC may further base relative timing of output samples on a value of one or more step size components associated with the integer components. Also according to techniques of this disclosure, a conversion rate of an SRC may be adjusted in real-time based on a detected mismatch between a source clock of a digital input signal and a local clock.

Abstract: A system and method for clocking in analog-to-digital (ADC) converter in a synthetic instrument unit is presented. A method begins by applying an input clock to an amplifier to produce an amplified clock. The amplified clock is filtered to produce a filtered clock. The ADC of this synthetic instrument unit is clocked with the filtered clock. The input frequency of the ADC corresponds to a second or higher order Nyquist zone that is above the sampling frequency of the ADC. The input data is carried by an intermediate frequency (IF) signal. The filtered clock of ADC is switched off a clock path of the ADC when the ADC is not in use.

Abstract: A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.

Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.

Abstract: A patient monitoring signal processing system adaptively varies medical signal data rate. The system uses an analog to digital converter for digitizing an analog cyclically varying input signal derived from a patient in response to a sampling clock input. The sampling clock determines frequency of analog to digital sampling of the analog input signal by the analog to digital converter. A detector detects first and second different signal portions within a cycle of the cyclically varying input signal.

Abstract: A method and apparatus for error avoidance in data transmission using dynamic modification of sampling rates. An embodiment of a method for transmission of data includes determining the transmission capacity for a transmission channel or channels. A sampling rate is selected based at least in part on the determined transmission capacity for the one or more transmission channels. An instruction, command, or information regarding the sampling rate is inserted in a data packet, and the data packet is transmitted.

Abstract: A point of sale terminal includes a microcontroller integrated circuit. In one aspect, a regulator within the IC receives power from a supply voltage terminal and/or a battery terminal. If the regulator does not receive adequate power from either terminal, then energy stored on-chip in a capacitor is used to erase secure memory. In another aspect, pulses of current are made to pulse through conductors of a conductive mesh. A tamper condition is detected if an improper voltage is detected on the IC terminal through which the pulse is conducted. In another aspect, each vendor signs his/her firmware with his own vendor ID. A bootloader uses the vendor ID to lookup a public key that is then used to verify a private key supplied by the firmware to be executed. In another aspect, a magnetic card reader includes a digital peak detector circuit involving programmable positive and negative thresholds.

Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.

Abstract: A method includes sensing a process parameter to generate a sensor signal that includes a process signal and line noise components, digitizing the sensor signal at a sample rate, detecting line noise zero crossings in the sensor signal, determining a line noise frequency as a function of the detected line noise zero crossings, and adjusting the sample rate as a function of the line noise frequency to reduce an impact of line noise on the digitized sensor signal.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: A method for generating a modulated carrier signal with reduced bit error rates based on a plurality of data symbols. A plurality of data symbols are received, and a digital input signal is generated based on the plurality of data symbols. The digital input signal are filtered to produce a digital output signal including a phase characteristic. The phase characteristic of the digital output signal remains close to the desired symbol phase for substantial portion of the symbol period. A carrier signal is modulated using the digital output signal to produce the modulated carrier signal.

Abstract: Magnetically latching and releasing a voice coil actuator for controlling electrical switchgear. The voice coil actuator includes a voice coil magnet disposed on a common longitudinal axis with respect to a voice coil assembly. A coil of the voice coil assembly exerts a magnetic force on the voice coil assembly, thrusting the voice coil assembly towards the voice coil magnet. At least one pair of latching members mounted to the voice coil assembly creates a permanent magnet circuit between the latching members and the voice coil magnet. The permanent magnet circuit maintains the position of the voice coil assembly relative to the voice coil magnet, even when power to the coil is removed. This latch can be released by applying a current in the coil or by applying an external, physical force to a member coupled to the voice coil assembly.

Abstract: A method and apparatus for a multi-mode and multi-rate telemetry transmitter includes a digital baseband lineup, a digital-to-analog converter (“DAC”), and an analog reconstruction filter. The digital baseband lineup may be programmed to any desired bit rate, enabling the transmitter to support multi-rate capabilities. Different coefficients and numerical values may be programmed in the digital baseband lineup to support any desired modulation scheme, enabling the transmitter to support multi-mode capabilities. The digital baseband lineup may be designed by implementing up-sampling stages, down-sampling stages, and digital filters in a variety of arrangements.

Abstract: A method of modulating the sampling period of a sampled system with a factor N, and correcting the data stream of the sampling system with the same factor N, thus minimizing distortion artifacts induced by sample frequency modulation. At least a one-period delay from receipt of a new data stream value is used to avoid heterodyning with the incoming stream.

Abstract: In a timing recovery method, two consecutive sampling values may be generated based on a sampled input signal. The input signal may be sampled according to a phase interval of a sampling clock. A slope between the two consecutive sampling values may be calculated, and a difference between a target slope and the calculated slope may be determined. A phase of the sampling clock may be compensated based on the difference between the target slope and the calculated slope.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value based on the magnitude of a previous error value for a previous loop iteration, plus margins conversion housekeeping and the step size of the next loop iteration. At a timing prior to a filter reading the error value that equals the number of clock cycles set by the predictor, a timing unit triggers the analog-to-digital conversion, reducing loop latency and improving performance.

Abstract: A method for converting analog values into digital form comprises comparing a current analog sample value with an analog input value to produce an outcome, generating a count value based on the outcome, the count value increasing upon successive like outcomes and being reset to an initial count value upon successive unlike outcomes, adding or subtracting the count value to/from a current digital sample value to generate a next digital sample value, the adding or subtracting being based on the outcome, and converting the next digital sample value to the current analog sample value.

Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

Abstract: A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.

Abstract: Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.

Abstract: An analog-to-digital converter can use a variable sampling rate. By using a variable sampling rate analog-to-digital converter and an anti-aliasing filter lower sampling rates, and accordingly, generally lower power consumption may be achieved. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over-sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or a signal farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.

Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce a

Abstract: Methods for processing waveforms may include decimating an over-sampled waveform by identifying samples for which the sample's position within a data period indicates that is closest to a selected time within a data period. In some example applications, the selected time may be determined as a preferred time to sample the waveform within a data period. In an illustrative example, a sequence of samples representing an over-sampled waveform may be reduced by identifying a sample in each data period that is closest in time to the selected time. In another illustrative example, a sample within each data period may be identified if it falls within a range that is a function of the selected time within the data period and an integral ratio of a sample period to the data period. The identified samples may be used to reconstruct the original waveform with fewer samples than the over-sampled waveform.

Abstract: A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.

Abstract: A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.

Abstract: The ?? AD converter includes: a sampling section for sampling an input signal at each cycle Ts; an AD conversion section for performing AD conversion of the input signal; a DA conversion section for performing DA conversion of an output of the AD conversion section; and a loop filter for integrating a difference obtained by subtracting an output of the DA conversion section from an output of the sampling section so as to output the integrated difference to the AD conversion section, wherein the sampling section includes two sampling circuits disposed parallel to each other, and the two sampling circuits respectively operate at timings different from each other, and each of the sampling circuits delays the input signal so as to output the delayed input signal.

Abstract: Staggered interleaved Nyquist regions associated with differing ADC clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered interleaved Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable anti-aliasing filters associated with each Nyquist region and its ADC clock rate are used to enforce the staggered Nyquist regions and their various guard bands. For example, and neglecting guard bands, an initial raw band of operation RB1 may be the First Nyquist region for a basic sampling frequency Fs. An adjacent raw band of operation RB2 that overlaps RB1 may be the Second Nyquist region for an alternate sampling frequency 2Fs/3. An adjacent raw band of operation RB3 that overlaps RB2 may be the Second Nyquist region for the basic sampling frequency Fs. These raw bands interleave and overlap: RB1: DC to Fs/2 1st Nyq. for FCLK = Fs RB2: (2/3)Fs ? to 2(2Fs/3)/2 = 2nd Nyq.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.

Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal, the master clock frequency measurement biased by a past operating mode selection, and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In an additional embodiment, the measurement circuitry biases the master clock frequency measurement based on a past master clock frequency measurement.

Abstract: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

Abstract: A method of determining coherent test conditions is disclosed. The method includes receiving constraints from a user, wherein the constraints include desired test conditions, desired tolerances for the desired test conditions, and desired instrument. Further, the method includes determining the coherent test conditions using the constraints. Moreover, the method includes providing each determined coherent test condition to the user, wherein each determined coherent test condition includes a calculated sampling frequency and a calculated analog frequency.

Abstract: An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.

Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. In some embodiments, the apparatus (10) generally includes a receiving element (12) operable to receive an input signal, an integrate/dump circuit (14), a sampling element (16), and a processor (18). The integrate/dump circuit (14) is operable to integrate at least a portion of the received signal to provide an integrated signal and the sampling element (16) is operable to sample the integrated signal at a first sampling rate which is less than the Nyquist rate for the input signal. The processor (18) is operable to form a compressed sensing matrix utilizing a first set of time indices corresponding to the first sampling rate, form a measurement vector utilizing at least a portion of the sampled signal, and reconstruct at least a portion of the input signal utilizing the compressed sensing matrix and the measurement vector.

Abstract: A signal sampling system includes an input signal and a plurality of samplers. The plurality of samplers produces a plurality of sample output signals. Each sampler from the plurality of samplers samples the input signal to produce a corresponding sample output signal from the plurality of sample output signals. Each sampler samples the input signal with a sampling pulse having a sampling aperture. A first sampling aperture used by a first sampler from the plurality of samplers to sample the input signal differs in duration from a second sampling aperture used by a second sampler from the plurality of samplers to sample the input signal.

Abstract: An asynchronous sampling arrangement utilizes sampling of both a high speed data signal and a trigger (clock) signal. The data signal may be either an optical signal or an electrical signal. The data and trigger signals are sampled in parallel by two separate gates, the gates based on the same strobe frequency. The samples corresponding to the trigger signal are then processed through an algorithm that determines the time-base related to the sampled signal. This established time-base is then used to reconstruct the sampled version of the high data rate input signal waveform.

Abstract: Methods and structures are provided for generating a digital display signal in response to an analog display signal whose amplitude varies at a pixel rate and in response to a synchronization signal that defines spatial order for the analog display signal. The structures include a transform generator for providing a Fourier transform of the digital display signal and a transform analyzer which generates frequency and phase control signals in respective response to the frequency of an error spectral component and amplitudes of image spectral components in the transform. The frequency and control signals are applied to respectively adjust the sample rate of the sample clock and alter the phase of the sample clock.

Abstract: A real-time sample rate converter having a non-polynomial convolution kernel provides reduction in die area and power for performing sample rate conversion in real-time. A non-polynomial convolution kernel, which may be a gaussian operator, is used to determine output sample values from values of an incoming stream of values. If the input sample rate is higher than the output sample rate, the input sample stream is convolved with the gaussian kernel and then decimated to yield the output stream. If the input sample rate is lower than the output sample rate, the input stream is resampled to a small multiple of the output sample rate and convolved with the gaussian kernel to produce the output sample stream directly.

Abstract: An implantable medical device uses a sampling scheme to obtain digital representation from analog signals. The analog signals represent intracardiac activity. Generally, a detector detects the amplitude of the analog signals and generates first and second difference signals. The first difference signal is generated after detection of significant changes in the analog signal amplitude. The second difference signal is generated upon confirmation of the absence of significant changes in the analog signal amplitude over a predetermined period of time. A frequency selection is implemented to select the sampling frequency based on the first and second difference signal.

Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. The method generally comprises forming a first compressed sensing matrix utilizing a first set of time indices corresponding to a first sampling rate, forming a second compressed sensing matrix utilizing a plurality of frequencies and a second set of time indices corresponding to a second sampling rate, forming a combined compressed sensing matrix from the first compressed sensing matrix and the second compressed sensing matrix, and reconstructing at least a portion of the input signal utilizing the combined compressed sensing matrix. The first and second sampling rates are each less than the Nyquist sampling rate for the input signal.

Abstract: A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal.

Abstract: A method and a device for dynamically accelerating an analog-to-digital converter (ADC) are provided. The device for dynamically accelerating ADC is capable of detecting the sampling frequency and controlling the maximum conversion rate by boosting the current into the ADC such that the maximum conversion rate of the ADC is larger than or equal to the sampling frequency. The efficiency of the ADC is optimized.

Abstract: A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.

Abstract: A method of communicating across a channel includes receiving information having a known bandwidth and a known spectrum. The information is preferably in the form of a multicarrier modulated signal, e.g., a DMT signal. In one aspect, this information is received at a receiver having a reduced channel bandwidth. An aliasing spectrum can be calculated based on the known spectrum and the frequency difference between the known bandwidth and the reduced-channel bandwidth. The received information can then be modified based upon the aliasing function to compensate for alias distortion. For example, the received information can be modified by modifying the noise component or signal-to-noise ratio of the received information.