Abstract: A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is operative to reduce the requirements for or completely eliminate the need for the anti-aliasing filter by dynamically modifying the sub-sampling rate (or decimation ratio). Rather than maintain a constant sampling rate (or decimation ratio), the sampling rate (or decimation ratio) is randomized such that its average remains at the nominal value and the effective jitter is low enough for the low rate (or low decimation ratio) system to tolerate. This smears or spreads interfering signals across the spectrum resulting in a noise floor at a significantly reduced level much lower than that of the original interferer signal. The interfering signals are reduced to background noise wherein the level of the resulting noise floor is not nearly as strong as the original interfering signal.

Abstract: A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Abstract: In one set of embodiments, a temperature measurement system may include an analog to digital converter (ADC) to produce digital temperature readings according to a difference base-emitter voltage (?VBE) developed across a PN-junction. A clock generating circuit may be configured to provide a sampling clock used by the ADC, which in some embodiments may be a delta-sigma ADC, in performing the conversions. The clock generating circuit may be configured to change the frequency of the sampling clock a specified number of times within each one of the one or more conversion cycles to reduce an error component in the temperature measurement, where the error component is produced by an interfering signal, such as an electromagnetic interference (EMI) signal being coherent with the sampling clock, and/or a noise residing on the voltage supply and also being coherent with the sampling clock.

Abstract: The scale and complexity of an apparatus is reduced by omitting a clock extraction section. The apparatus includes: a sampling pulse train generation device which generates an optical or electrical sampling pulse train, independently of an input optical or electrical data signal with a bit rate f0(bit/s), and which has a repetition frequency f1(Hz); a data signal sampling device which samples the data signal in accordance with the sampling pulse train to obtain a sampled signal; a voltage retaining device which converts the sampled signal, and stores pieces of electrical digital data; an electrical signal processing device which reads the digital data at once or sequentially to obtain a signal eye-diagram and evaluates optical data signal quality parameters; and a trigger signal generation device which applies triggers indicating the start/finish of data acquisition and data read to the voltage retaining device and the electrical signal processing device, respectively.

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Abstract: A technique for controlling a switching circuit, such as a relay, includes one or more sensing circuits that generate signals based upon the presence of an actuating object and upon a randomly applied strobe signal. The generated signals are sampled and are used as a basis for determining the state of an output signal. The sensing circuit may generate the signals based upon capacitive coupling with the actuating object. The randomization of the sampling provides enhanced immunity to periodic or cyclic noise. Where more than one sensing circuit is included, the output of the circuits may be considered together for determining the state of the output signal, such as based upon predetermined ranges of signal levels. Signals of the sensing circuit may be sampled in the absence of the strobe to provide an indication of the relative noise level. If the noise level is determined to be elevated, the output signal may not change states.

Abstract: A digital filtering system for filtering sample data includes a delay network for delaying input sample data to provide multiple delayed sample data outputs. The filtering system also includes a filter network represented by a decomposed coefficient weighting matrix for processing the delayed sample data outputs. A processor produces a filtered output by computing a weighted product summation of the delayed sample data outputs and the coefficient weighting matrix. The decomposed coefficient weighting matrix is derived by factoring a first coefficient weighting matrix with a common row factor and/or sparse matrix or by factoring based on matrix row or column symmetry.

Abstract: An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several parallel connected capacitors for different time durations with at least some non-overlap. In an embodiment, such an approach is used in a switched capacitor amplifier circuit of an ADC. The capacitors in that embodiment start charging at the same time instance, but stop charging at different time instances due to the design of associated switches and control signals.

Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.

Abstract: A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, includes a storage device 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the writable address, and an interpolation processing unit 14 for interpolating the data read-out from the storage device 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a writable address and a readable address in the storage device 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.

Abstract: A receiving apparatus constructed to store data received from a network in a buffer and read the data in the buffer based on a reference clock, has a detecting means for detecting change of a sampling frequency of the data, a first controlling means for controlling to stop writing of the data into the buffer and reading of the data from the buffer in response to an output of the detecting means, a clearing means for clearing the data in the buffer in response to the output of the detecting means, a clock changing means for changing a frequency of the reference clock in response to the output of the detecting means, and a second controlling means for controlling to restart the writing of the data into the buffer and the reading of the data from the buffer in response to the output of the detecting means.

Abstract: An in-vehicle device data communicates with data processing resources, including global network based data processing resources for the purpose of programming and receiving data from an in-vehicle device where the data communicated can include sampling intervals, global position system (GPS) data, or scientific instrumentation data related to certain weather, environmental, traffic, or road conditions. Scientific instrumentation data gathering can be effectuated proximate to a vehicle, wherein the vehicle has an in-vehicle device and the in-vehicle device has a scientific instrumentation interface. In this regard, scientific instrumentation data can be obtained while the vehicle is stationary or in motion. Scientific instrumentation data gathered at the data processing resource or gathered by the in-vehicle device can be utilized to effectuate a wide variety of data dissemination.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with the existing software.

Abstract: An apparatus for producing a digital depiction of a signal (10) which is adaptive to the signal itself. A constant rate sampling means, such as an analogue to digital converter (2), samples the signal (10) at a constant rate and produces a first digital depiction (12) of a signal. A transformation means (14) is responsive to the first digital depiction (12) and produces a second digital depiction based on the evolution of the signal. The transformation means may be capable of determining when a predetermined threshold level has been crossed and measuring the time interval between predetermined threshold level crossings. The transformation means (14) may include a logic arrangement and a timer counter and is run from a clock signal (16) from the same clock (6) as drives the sampling means. A method of adapting a conventional ADC (2) to adaptively sample the signal (10) by adding a transformation means (14) run off the same clock (6) as the ADC (2) is also provided.

Abstract: A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device.

Abstract: A sampling apparatus including two or more samplers, where a signal is sampled simultaneously by each sampler and the values sampled by one of the samplers is then used. In this way, sampling operations for the purpose of ranging are eliminated, and the time required for ranging can be shortened. Moreover, the possibility that the instantaneous values of the signal input to the sampler will exceed the input range of the sampler can be inferred in each sampler by establishing a suitable threshold value for its sample values.

Abstract: A sigma-delta modulator. The sigma-delta modulator comprises an integrator, a first quantizer, a dither generator and an adding device. An input terminal of the first quantizer and an input terminal of the dither generator are coupled to an output terminal of the integrator. The first quantizer generates a first random signal. The dither generator comprises a second quantizer for generating a second random signal, an input terminal thereof coupling to the output of the integrator; a random sequencer for receiving the first random signal and the second random signal to produce a third random signal output; and an attenuator for attenuating the third random signal to produce a dither signal to output. The dither signal is added to an input terminal of the integrator by the adding device.

Abstract: The analog-to-digital conversion system comprises an analog-to-digital converter that includes a digital output, memory having a data input and a data output, an output port, an input data bus that extends from the digital output of the analog-to-digital converter to the data input of the memory and an output data bus that extends from the data output of the memory to the output port. The analog-to-digital converter is structured to generate digital samples at a sampling rate. The input data bus is structured to operate at the sampling rate of the ADC. At least one of the data output of the memory, the output data bus and the output port is structured to operate at a maximum rate less than the sampling rate.

Abstract: A method and device are described for detecting bits in a read signal sampled at a system clock frequency which deviates from the bit frequency. A series of bit-frequency relevant signal values (B12) is computed from the series of system clock frequency-measured sample values (B1, B2, . . . ) as a convolution of the measured sample values having a function centered around the desired sampling instant, which function is the Fourier transform of a predetermined pulse response of the sampling procedure. This pulse response is chosen to be such that the sampling procedure is reliable for bit frequencies up to twice the system clock frequency. To be able to process such high bit frequencies in actual practice, a bit detector (320) according to the invention has two data outputs (321, 322) and one validity output (225). Whenever a computation has been finished, a pulse is supplied at the validity output whose frequency may be maximally equal to the system clock frequency.

Abstract: A digital controller comprises two control paths each having an A/D converter. One of the two converters has a substantially higher sampling speed and lower resolution than the other. Thus, one is suitable to deal with the fast responses while the other is suitable to deal with the slow responses, and can replace high-speed high-resolution A/D converter which is high in both cost and power consumption.

Abstract: A data converter includes first and second input signal paths receiving an input signal having an input frequency, the first input signal path dividing the input frequency by a first divisor and the second input signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first input signal path and an output from the second input signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and a current state of the control signal and selectively resets the state of the control signal to set the selector output frequency to a desired frequency.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: Techniques and systems for identifying coding rates of transmitted frames are described. Unused bits in rate adapted frames are used to carry frame type indicator patterns. Maximal rate frames (i.e., with a highest coding rate) need not include a frame type indicator.

Abstract: A resampler is used to convert an input digital signal sequence having an input sampling rate into an output digital signal sequence having an output sampling rate (fout). An estimating unit estimates the sampling rate ratio between the input sampling rate and the output sampling rate (fout) and estimates the set point phase of the output signal sequence in observation intervals whose observation length is variable. A controlling system compares the actual phase of the output signal sequence with the set point phase and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio and the deviation of the actual phase from the set point phase. An interpolator interpolates the input signal sequence for generating the output signal sequence at sampling times whose location in time is predetermined by the control signal (RTC,k).

Abstract: A method comprising identifying a sample rate of received audio content, receiving a conversion sample rate, and converting the received audio content to the received conversion sample rate. Wherein the conversion comprises utilizing a repeating sequence of packets where all but one of the packets of each sequence are truncated to a whole number of samples, while the remaining packet is rounded up to the next whole number of samples if the conversion fails to resolve packet size to a whole number.

Abstract: In a method for prescribing an essentially linear ramp with a prescribable slope by a quantity, and which is clock-pulse-controlled and which describes the ramp by an increment per clock interval, the ramp is described by a number of regular increments and by at least one first and one second irregular increment. The regular increments exhibit a value corresponding to the prescribable slope. The irregular increments exhibit a value deviating from the prescribable slope. The first irregular increment is a first increment describing the ramp and the second irregular increment is a last increment describing the ramp.

Abstract: Disclosed is a data converter and a method for converting a digital audio stream representing an analog signal that has been sampled at a certain rate. The circuit includes a divider that receives a clock signal associated with the digital audio stream and divides the clock signal by a selectable division factor. The division factor is set according to divider control signals. At the output of the divider is provided an internal clock signal. A frequency detection circuit receives the signal from the output of the divider, and the frequency detection circuit detects the original sampling rate of the audio signal based upon intrinsic characteristics (e.g., MCLK to LRCK ratio) of the digital audio stream.

Abstract: An apparatus and method for converting digital input signals sampled at different rates to analog signals includes a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.

Abstract: There is provided a data storage device concurrently allowing storage of data that can be reproduced in higher quality and storage of data that can be used also in a data transmission path with a lower transfer speed. The data storage device comprises an A/D converter 103 for sampling analog audio signals based on a sampling frequency, a DSP 104 for compressing sample data sequentially output from the A/D converter 103, a storing and reading control unit 107 for storing the compressed data sequentially output from the DSP 104, and a control unit 105 for controlling the DSP 104 and the storing and reading control unit 107 for dividing the sample data sequentially output from the A/D converter 103 into a group under odd number of turns and a group under even number of turns, compressing the groups at each different compression rate and storing them on different storage areas A and B, respectively.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.

Abstract: A method for sampling a signal for signal processing, such as calculating the coefficients of a Fourier or other transform of the signal. The sampling occurs at sampling points which are the union of sets of points, each set being points separated by regular intervals of 1/pn where pn is a prime number. Where the signal is not accurately reconstructed from the sampled values the method recurses and increases the set of distinct primes. The invention relies upon the incommensurate nature of different primes to prevent the invention from degenerating into an inefficient sampling technique such as using regular intervals would provide. The scale, termed a D scale, is applicable to problems in diverse domains such as signal processing, including digital signal processing (DSP), image processing, scientific and engineering computational applications, data acquisition and statistical data analysis.

Abstract: A method for decoding information contained in a waveform having a series of peaks is disclosed which is particularly directed to a method for reading a magnetic stripe for example on a card that allows the information on the stripe to be read without the need for unidirectional, single stroke swiping motion of the stripe. Features are disclosed that permit the accurate decoding of magnetic stripe data to define the bi-phase coded bits in the presence of signal degradations caused specifically, but not exclusively, by variations in the read speed including stop events and reversals. The method uses sampling of the waveform at a variable rate based upon the area of the waveform. The samples are used to locate peaks in the waveform, the profiles of which are then compared using various criteria with trained model peaks to classify the peaks into different types based upon the intersection between the different bits allowed under the bi-phase coding rules.

Abstract: A sampling device for sampling an input signal having intrinsic filter properties. The sampling device samples a continuous analog input signal according to a sampling signal. The sampling device includes a first sampling switch for sampling the input signal, in response to a sampling signal, to create a first set of samples. Furthermore, the sampling device incorporates a time delay device for time delaying the first set of samples. The sampling device also includes a phase shift device for phase shifting the input signal. The phase delayed input signal is then fed into a second sampling switch for sampling in response to the sampling signal to create a second set of samples. Further, a summer is incorporated to sum the first set of samples with the second set of samples to create the output samples.

Abstract: The present invention relates to a sigma-delta analog-to-digital converter using a mixed mode integrator composed of an analog integrator and a digital integrator, which can prevent the performance degradation due to the saturation of an integrator of the overload of a quantizer. A sigma-delta analog-to-digital converter having an anti-aliasing filter, a sample and hold circuit, a sigma-delta modulator and a decimation filter comprises an overload estimating unit for judging the saturation or overload of an analog integrator; a mixed mode integrator which has the analog integrator and a digital integrator composed of a digital adder and a digital storing unit and integrates the output of the overload estimating unit in analog or digitally; and a quantization unit for converting the output of the mixed mode integrator to a digital signal.

Abstract: An analog to digital converter (ADC) circuit suitable for processing serial data at a fast rate includes a clock control block for receiving a reference strobe signal REF_STB, a reference clock signal REF_CLK, and number of bit control signals CONT—1, CONT—2. The clock control block outputs first and second internal clock signals CLK_A, and CLK_B, and a forwarding direction control signal CONT—3. The ADC circuit also includes a parallel analog to digital converter for receiving and converting analog signal into a parallel digital data synchronously with the first internal clock signal CLK_A. A parallel to serial transform logic control block then transforms the parallel digital data into serial digital data synchronously with the second internal clock signal CLK_B.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.

Abstract: The invention relates to a method and apparatus for achieving maximal coding gain for audio transmission. More particularly, at a chosen sample rate and frequency range value, an audio input signal is downsampled to the sample rate, encoded and transmitted at a given bit rate. At the receiving end, the downsampled signal is decoded and upsampled to the original or other suitable sample rate. The upsampled signal is then audibly output. Since resampling ratios using “small” numbers prove to be more computationally efficient, this method and apparatus supports resampling ratios which imply both standard and non-standard sampling ratios in the codec.

Abstract: A circuit is disclosed for sampling analog signals at a rate which is a rational, non-integer fraction of a clock frequency. The analog signal is sampled at non-equidistant sampling points, with the distances between successive points forming a jitter sequence. The jitter sequence is pre-calculated and stored in a memory within the circuit, reducing processing requirements in use.

Abstract: A low power sample rate converter adapted for use with a telecommunications system transceiver. The sample rate converter includes a first circuit that provides an input signal characterized by a first sample rate and a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, samples in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, samples in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal providing a rate-converted version of the input signal as an output signal in response thereto.

Abstract: A data reproduction device includes an A/D converter quantizing a reproduction signal read from data recorded on a recording medium to produce quantized data based on a sampling clock; a reproduction signal determination unit determining rising and falling parts of the reproduction signal based on the quantized data, and outputting a gate signal corresponding to a result of determining the rising and falling parts; a leading-edge clock generation unit generating a leading-edge clock signal synchronous to a leading edge indicating a rising part of the reproduction signal; a trailingedge clock generation unit generating a trailingedge clock signal synchronous to a trailing edge indicating a falling part of the reproduction signal; a signal switch unit generating the sampling clock by selecting one of the leading-edge clock signal and the trailing-edge clock signal based on a value of the gate signal; and a signal supply unit supplying the sampling clock to the A/D converter, wherein the data reproduction device

Abstract: A signal processing circuit for converting a 2-channel analog signal into a digital signal includes an analog/digital conversion component for sequentially converting the 2-channel analog signal into digital data according to a sampling clock, and an operation control component for setting a high sampling frequency of the sampling clock at a frequency higher than a normal sampling frequency of the sampling clock and setting a sampling clock duty ratio so that digital data of at least one channel can be sampled.