Abstract: Pulses are produced in accordance with physical quantity changes in order to express the amount of change by count of the pulses produced. The changes are input to a convertor which converts them to corresponding electrical output values which are made available to a sample and hold circuit and to a first input of a comparator. An output value accepted from the convertor is held, as a held value, in the sample and hold circuit and provided therefrom to a second input of the comparator. The comparator produces an output pulse, so as ultimately to provide a trigger pulse and to be counted, only when the first input of the comparator differs from the second input thereof by a preset reference amount. At each trigger pulse, the sample and hold circuit accepts the next available electrical output value from the convertor as the value to be hold and provided to the comparator.

Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.

Abstract: A pseudo-random repetitive sampling circuit which is capable of sampling fast signals, sampling negative and positive time around a trigger event, and rapidly building the waveform for display. The circuit accomplishes this by acquiring negative and positive time in two different ways. Positive time information is acquired using a modified form of sequential sampling, since sequential sampling can rapidly build the signal for samples that occur after the trigger event. The system also may take multiple samples for each trigger event. For samples occurring prior to the trigger event, the system uses a modified form of random repetitive sampling. The modification comprises sampling of the waveform prior to allowing any trigger events to occur, and qualifying each trigger event so that a trigger event is only recognized when it occurs in a programmable time window after a sample.

Abstract: Method of, and apparatus for, providing automatic detection of potential information loss due to undersampling and automatic detection of potential storage waste due to oversampling based on automatic determination of an analog signal's Nyquist rate. The invention acquires an analog signal, determines a maximum frequency of the analog signal and a corresponding Nyquist rate, and allows a user to select a sampling rate based on either the automatically determined Nyquist sampling rate, a user specified sampling rate, a sampling rate determined by a user specified bandwidth, or a sampling rate determined by user specified available space. The invention also informs a user when a loss of information may occur due to a sampling rate being less than the Nyquist rate. The invention also informs a user when a waste of storage may occur due to a sampling rate being greater than the Nyquist rate.

Abstract: Aliasing and synchronization difficulties in determining transfer functions in mixed domain (analog and digital) systems are overcome by sampling the analog signal at a higher sampling frequency that the digital signal, and zero filling the set of sampled digital data (if necessary) so that the sampled digital data corresponds to the more densely sampled analog data. By so doing, a single fixed frequency anti-alias filter in the analog channel can be used to avoid aliasing problems in mixed domain measurements over any span of frequencies, up to the entire passband of the filter. The invention is particularly illustrated with reference to measurements both across digital-to-analog boundaries and across analog-to-digital boundaries.

Abstract: An analog-to-digital (A/D) converter has a simple arrangement and achieves an accurate high-speed A/D converting operation. The A/D converter comprises an analog data input unit (2), an A/D conversion circuit (3), a controller (4) for controlling the A/D conversion circuit (3), and a digital data output unit (100). The controller (4) includes a sampling time controller (5) and a bit conversion time controller (6).

Abstract: An AC input signal is sampled with a plurality of sets of equally spaced samples, but whose sample interval between the samples does not exactly divide the period of the input signal. Nevertheless, and error cancellation technique allows ultra accurate measurements to be made. The samples in each set of the plurality of sets are supplied to a computational process that extracts some parameter; e.g., RMS voltage. The extracted parameter is in error, owing to the non aliquot nature of the sampling. The size of the error is related to, among other things, where on the input waveform the associated set began. The error is a period AC function of that starting location. By arranging for n-many sets to start at phase differences of 1/n apart on the input waveform, a series of n-many parameter.sub.i are obtained that are each of the form [result.sub.i +error.sub.i ]. Thus, the error.sub.i are sampled at aliquot locations along an error function, and therefore sum to zero. Thus, averaging the parameter.sub.

Abstract: In this digital signal measurement apparatus, an approach is employed to deliver a measurement signal from a measurement signal generator to a measured circuit to transform the signal on the time base through the measured circuit to a signal on the frequency base by a frequency base transform circuit and to further obtain a signal on the time base by a time base transform circuit. Thus, a difference between the signal on the time base through the measured circuit and the signal on the time base from the time base transform circuit is employed. Thus, for example, even if the measured circuit is a linear system, a measured result in the digital region and a result of the analog measurement can be in correspondence with each other. Accordingly, gain correction of a measurement signal is unnecessary, thus making it possible to prevent an increase in an error of a measured result of S/N.

Abstract: A signal acquisition system using an ultra-wide time range digitizer with variable time interval data sampling and data storage includes signal conditioning and sampling stages, a digitizing stage for generating digital representations of a signal, and a memory for storing the digital representations. Timing circuitry controls sampling and digitizing which may be varied so as to acquire signals on linear, logarithmic, or other time bases. Signal compression may be obtained by digitizing information only when a desired change rate is observed. A display allows acquired signals to be displayed in linear, logarithmic or other manner.

Abstract: This is a technique for extending the frequency range which employs a power divider having two outputs, one output being supplied to a first A/D converter, and the other output being supplied via a delay device to a second A/D converter. A processor receives the outputs of the two A/D converters. In operation, the input signal is subjected to a known delay .tau. and both original and delayed signals are sampled simultaneously. Both sampled signals are Fourier transformed and the phase and amplitudes calculated, using the expressions:.phi.(f)=tan.sup.-1 [I(f)/R(f)]A(f)=[R.sup.2 (f)+I.sup.2 (f)].sup.1/2where R(f) and I(f) are respectively the real and imaginary parts of the frequency transform. The phase difference between the original and delayed signals is calculated and an approximation to the true frequency for each peak observed in the amplitude spectrum is estimated using the expression.phi.=2.pi.f.tau.where .tau. is the delay.In general, one would expect that when f.tau.

Abstract: A system is provided for converting an input digital data sampled at a first sampling frequency to an output digital data to be sampled at a second sampling frequency. The input digital data is sampled to obtain sampling data with respect to an estimating data corresponding to a data at a sampling point of the output data. The sampling is performed within a period of the least common multiple between a period of sampling of the input digital data and a period of sampling of the output digital data. The estimating data is interpolated from the obtained sampling data.

Abstract: Current switching apparatus including at least one current switching tree comprised of cascaded sets of switching circuits, with an input set operable with sampling clock pulses supplied at a fixed frequency and the remaining cascaded sets operable at different frequencies, and further including a sample skipping circuit interconnected between successive sets for reducing the effective sampling frequency of the switching tree while maintaining the fixed frequency at which the input set operates. The sample skipping circuit includes a dump circuit selectively energized to dump selected samples produced by the input set. When the apparatus is formed of plural switching trees of different phases, a sampling clock generator having an adjustable delay circuit is used to delay sampling clock pulses by adjustable amounts so as to establish predetermined phases of sampling clock pulses of the same frequency and different phases for use in each switching tree.

Abstract: In one embodiment, the sampling order of voltage/current data channels from a power transmission line is controlled so that the average sampling instant for each channel is the same. In one example involving a six-channel system, the sampling order will alternate between 1,2,3,4,5,6 and 6,5,4,3,2,1. The sampled data is applied through a digital filter which averages the sampling instant for each channel. In another embodiment, low-pass filters are positioned on each channel, the low-pass filter introducing a predetermined delay for each channel which compensates for the sampling delay on each channel where the channels are sampled in a particular sequential order, i.e. 1,2,3,4 . . . n. The shortest delay will be present in the low-pass filter associated with the first channel, a slightly longer delay will be present in the low-pass filter associated with the second channel and so on through the nth channel.

Abstract: A technique covered by patent applicaton S.N. 07/672,309 divides power of an input signal to two A/D converters. A processor receives the outputs of the two A/D converters. The input signal is subjected to a known delay .tau. for one of the converters, and both original and delayed signals are sampled simultaneously. Both sampled signals are Fourier transformed and the phase and amplitudes calculated, using the expressions:.phi.(f)=tan.sup.-1 [I(f)/R(f)]A(f)=[R.sup.2 (f)+I.sup.2 (f)].sup.1/2where R(f) and I(f) are respectively the real and imaginary parts of the frequency transform. The phase difference between the original and delayed signals is calculated and an approximation to the true frequency for each peak observed in the amplitude spectrum is estimated using the expression.phi.=2.pi.f.tau.where .tau. is the delay. Herein the input signal is down-converted into two parallel paths with frequencies which differ by f.sub.s /4 where f.sub.s is the sampling rate. The alias boundaries are at multiples of f.

Abstract: Aliasing and synchronization difficulties in determining transfer functions in mixed domain (analog and digital) systems are overcome by sampling the analog signal at an integer multiple of the digital signal, and zero filling the set of sampled digital data so that the sampled digital data corresponds to the more densely sampled analog data. By so doing, a single fixed frequency anti-alias filter in the analog channel can be used to avoid aliasing problems in mixed domain measurements over any span of frequencies, up to the entire passband of the filter.

Abstract: Sample values of a digital signal of a first sample rate are supplied to a digital filter for conversion into a digital signal of a second sample rate. The coefficients of the digital filter are calculated by a processor from the ratio of the sample rates or are obtained by a read-only memory containing sets of coefficients for respective sample rate ratios for which the apparatus is usable. Filtered sample values are read out of the digital filter at the desired second sample rate. A buffer memory is used at the input of the digital filter and a regulator is provided to prevent fluctuations in the filling of the buffer memory from emptying or exceeding the capacity of the buffer memory.

Abstract: A signal processing device comprises a comparator, a first reference signal generating unit, a second reference signal generating unit and reference signal controller and switch which is switched when the data head data of the input signal is detected by the controller. In the case when the content of the input signal is a clock producing data, the reference signal generated in a rapid process of the first reference signal generating unit is entered in the comparator, and in the case when the content of the input signal is a reproduction data, the reference signal generated in a slow process of the second reference signal generating unit is entered in the comparator so as to be compared with the input signal.

Abstract: A relatively simplified sampling frequency converter for use in a format conversion apparatus is operative to convert sampled input data of an input sampling frequency into sampled output data of an output sampling frequency. The converter has an over-sampling circuit for increasing the sampling frequency of the sampled input data by a predetermined factor or coefficient to provide over-sampled data; an output data extractor for periodically extracting data from the over-sampled data in response to a timing pulse having the output sampling frequency; and a controller for controlling the phase of the timing pulse which controls the phase of the sampled output data.

Abstract: A multi-channel digital random access recorder-player receives an analog audio signal, converts the audio signal into a digital signal, and stores the digital signal in a memory for random access. The memory includes sixteen channels, each channel having sixteen memory boards, each channel and each memory board being assigned a unique four bit binary address by an address counter. An external control is provided by which the user selects an address for recording or playback and a comparator compares the selected address with the addresses of the memory. When the memory address corresponding to the selected address is detected, that memory board is enabled so that data can be recorded on the memory board or retrieved from the memory board for playback through an audio output device such as a loudspeaker. The recorder-player thereby provides random access to a memory. Also provided is a system in which several modules, each with a logic board and a memory, are combined into a single system.

Abstract: An A/D (analog-to-digital) converter circuit that controls a frequency characteristic of an input video signal in response to a sampling signal of a variable frequency to reduce distortions such as a folded distortion and so on caused by the A/D conversion.

Abstract: An unkown signal is sampled by simultaneously comparing its value with that of each of a plurality of predetermined monitoring levels. An independent time variable is recorded that represents the instant when the signal has a value equal to that of a given monitoring level. Equality of the signal value to that of a given level is detected regardless of whether the signal has increased or decreased to that value. The values of the monitoring levels are changed automatically whenever the signal has a value greater than the highest value monitoring level or less than the lowest value monitoring level. Signal sections having infinitely high rates of change over time may thus be accurately sampled and reconstructed.

Abstract: A signal transmission system and method is provided in which analog signals are sampled quasi-randomly and the samples stored. The samples are thereafter retrieved with an equal interval between them and transmitted. At the receiver, the transmitted samples are stored, decoded and reconstituted with the original quasi-random sample interval therebetween. The transmission system and method permits the faithful capture and transmission of signals across bandwidth limited transmission systems even though such signals lie outside that bandwidth.

Abstract: A signal path setting circuit for a digital recorder comprising: a digital-to-analog converter hereinafter referred to as a D/A converter to convert a digital signal into an analog signal, a first switch to supply to the D/A converter a selected signal from a plurality of digital signals including a first digital signal from recording and playing back means for making a digital recording and playback through a recording medium, a second switch to supply a selected signal from a plurality of analog signals including the analog signal from the D/A converter, and an analog-to-digital converter (hereinafter referred to as an A/D converter) to convert the analog signal from the second switch into a second digital signal which is adapted to be directly or selectively supplied to the recording and playing back means.

Abstract: A data compression method and appartus particularly suitable for use in electrical power line fault data recorders. The system performs both gain compression and frequency compression. For gain compression, a predetermined number of samples are analyzed to determine a gain setting common to each sample in the set of samples. A reduced data string consisting of a gain code and data words having fewer bits than the input words are transmitted as a compressed data string. For frequency compression, a sample set representing the input signal is decimated until there remain only a sufficient number of data samples to satisfy the Nyquist criterion for the highest frequency component of interest. Also included is a circuit for reproducing the waveform envelope. Positive and negative peak detectors provide signals representative of the peaks of the waveforms.

Abstract: A noise shaping modulator for use in sigma delta modulation data conversion has two or more cascaded quantization loops. A first quantization loop is operated at a first sampling frequency and one or more higher order quantization loops are operated at a second sampling frequency. Due to speed limitations of analog circuitry in the first quantization loop, a significant improvement in signal to noise ratio may be achieved in a sigma delta modulation data converter by selecting the second sampling frequency higher than the first sampling frequency.

Abstract: An apparatus for displaying monitoring data of a continuously varying operation condition of a drive mechanism driven by an actuator, in which data of one operation cycle of the drive mechanism is detected preliminarily as reference data and displayed on a coordinate axis on a monitor to show deviation between the reference data and the detected data of each operation cycle. Allowable uppermost and lowermost limit data of the reference data are also calculated and displayed on the same coordinate axis of the displaying surface of the monitor.

Abstract: A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

Abstract: A circuit samples and stores high frequency transient events that affect low frequency steady state signals. The circuit digitizes the high frequency transient signal and samples the digital signals. The present and previously stored data samples are compared, and if the difference exceeds a threshold, the present sample is stored in memory, if the memory is not full, and simultaneously the internal counter is reset. If a number of successive samples do not exceed the threshold and are not stored within a defined interval, the last sample of the interval is stored and an interval counter is reset to zero. A logic circuit controls the timing and operation of the counter and storage of the sampled data.

Abstract: A method of and apparatus for converting between first and second digital data formats is disclosed whereby digital words of the first format are analyzed to detect an upper bandwidth limit of a corresponding analog signal in an interval thereof defined by such words and to determine the level of the analog signal at the beginning of such interval. A digital word of the second format is encoded with first and second pluralities of bits representing the determined upper bandwidth limit and the level of the corresponding analog signal at the beginning of the interval.

Abstract: In a sample rate converter having a non-rational conversion factor the input samples coincide with low-rate clock pulses and the output samples coincide with high-rate clock pulses, or inversely. It comprises a filter coefficient generator which, based on the distance (deviation) between a low-rate clock pulse and the immediately preceding or immediately subsequent high-rate clock pulse, continuously supplies a series of filter coefficients. To determine the deviation a phase-locked loop is provided, with a phase detector receiving the low-rate clock pulses as well as synthetic low-rate clock pulses and supplying a discrete-time phase difference signal which is applied to a processor circuit. This circuit supplies the desired deviation and a reference number which is applied to a counter circuit. This circuit also receives the high-rate clock pulses and each time after receiving the number of clock pulses corresponding to the reference number it supplies a synthetic low-rate clock pulse.

Abstract: An electricity metering transducer is disclosed which samples voltages and currents at an innerconnection terminal of an electrical energy distribution system, converts those samples to digital form and computes selected electricity metering quantities. In a multiphase system current and voltage signals are multiplexed to a pair of codecs, one for current signals and one for voltage signals. The period of the signals being sampled is detected and used to generate a substantially nonsynchronous sampling signal so that a sample migration system is created which provides a large number of samples of a composite wave form. The steps of a digitally generated stepwise approximation of a sawtooth waveform are summed with the sequential analog samples and then removed from the digital value of each sample by software operation in order to increase the resolution of the digital to analog conversion.