Abstract: Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.

Abstract: Verifying whether correcting data used for proximity effect correction is normal before or during actual lithographic writing. A lithographically written region is virtually divided into subfields. Verification of a correcting value for proximity effect correction for each subfield is normal is made. The correcting values (in percent) for proximity effect corrections for the subfields are stored in a memory. The correcting values are successively supplied to a FIFO and to a comparator. A reference value from a register is also supplied to the comparator. The correcting value for the first subfield r(1) and the output data from the FIFO are supplied to the comparator. The output data from the FIFO includes data about subfields located above and left, respectively, of the subfield r(1). The comparator produces the differences between the incoming values and takes their absolute values. The absolute values are compared with a reference value from the register.

Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: A flash analog-to-digital converter (ADC). Each comparator of the flash ADC has an OFF-ON-OFF transfer function. For each analog value to be converted, only one comparator is in the ON condition, and the other comparators are in the OFF condition. In this way, the average power consumption of the flash ADC is much less than the average power consumption of prior similar devices.

Abstract: A method and structure for a digital-to-analog converter comprising a voltage source supply; a voltage division stack connected to the voltage source supply; a multiplexer connected to the voltage division stack; a digital circuit connected to the multiplexer; an analog circuit connected to the multiplexer; and an input binary word source connected to the digital circuit, wherein outputs of the digital circuit are input into the analog circuit and converted as analog output. According to the invention, the multiplexer comprises any of an NFET and/or a PFET. The digital-to-analog converter further comprises a capacitor connected to the analog circuit and a binary-weighted tunneling current device connected to the digital circuit. The multiplexer and the capacitor are made of thick oxide (at least 5 nm thick). The tunneling current device outputs tunneling current, wherein the tunneling current is adjusted in proportion to a binary weight of the input binary word source.

Abstract: A circuit includes a resonant tunneling device which is responsive to an input signal for causing an electrical signal characteristic to undergo a quantum jump in magnitude that takes an interval of time. According to one feature, a differentiator responds to the quantum jump in magnitude by producing a narrow pulse with a duration which is approximately the interval of time. According to a different feature, a sampling portion responds to the quantum jump in magnitude by sampling a signal during a time period having a duration which is approximately the interval of time.

Abstract: Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These parameters are the basis for mapping the groups of pulses to information symbols which collectively constitute the data to be recovered.

Abstract: A sub-flux quantum generator includes an N-turn ring having a plurality of connected turns about a common aperture. The width of each respective turn in the N-turn ring exceeds the London penetration depth of a superconducting material used to make the respective turn. The generator includes a switching device configured to introduce a reversible localized break in the superconductivity of at least one turn in the N-turn ring. The generator includes a magnetism device configured to generate a magnetic field within the aperture of the N-turn ring. A method for biasing a superconducting structure that encompasses all or a portion of an N-turn ring. While a supercurrent is flowing through the N-turn ring, a quantized magnetic flux is introduced into the aperture of the N-turn ring using a reversible localized break in a turn in the ring. The quantized magnetic flux is trapped in the ring by removal of the localized break. The trapped flux biases the superconducting structure.

Abstract: A Josephson junction has a Si substrate, a two layer film comprising an amorphous MgO layer and a high orientation MgO layer on the Si substrate, and a NbN film or the NbCN film laminated on the two layer film.

Abstract: An apparatus includes a quantizer circuit having a resonant tunneling device with an operational characteristic that includes a first region of unstable operation, and second and third regions of stable operation. An input terminal and an output terminal are each coupled to one end of the resonant tunneling device. A bias section is coupled to the resonant tunneling device, and responds to a clock signal by alternately operating in a first mode where the resonant tunneling device is forced to operate within the first region, and a second mode where the resonant tunneling device is permitted to operate in either of the second and third regions.

Abstract: A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Abstract: A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

Abstract: To make a decision circuit for RZ format optical signals at a very high data rate, the device (1′) comprises an electronic component (2) having a tunnel diode characteristic presenting a peak current (IP) and a valley current (IV). The device (1′) comprises a control current source (9) controlled by a control signal (VRESET) said current being injected into the component (2) and taking a first value or a second value. In response to an input optical signal (E), generator means (2) generate a current (IRZ) into the component (2). The valley current (IV) is of a value greater than the first current value and the peak current (IP) is of a value lying between a second current value (IR) and the sum of said second value plus the value (IRZ) of the current generated the generator means (2).

Abstract: A Rapid Single-Flux-Quantum (“RSFQ”) encoder output interface device is provided. The RSFQ output interface device includes a variable phase multi-junction voltage controlled oscillator (VCO) that provides multiple clock signals having similar frequencies based on a DC bias current setting. The multiple clock signals are phase shifted from one other based on a flux bias current setting. The clock signals are then mixed together according to logic states of a data stream to provide an encoded output data stream. The encoded output data stream can be in a phase shifted keying (PSK) format. The PSK format can be provided in binary, quadrature or other PSK formats. The Single-Flux-Quantum (SFQ) voltage pulses of the encoded output data stream are converted to a voltage level appropriate for transmitting over a wire.

Abstract: A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit (26) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit (52) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit (52) includes two Josephson transmission lines (60, 62), where the magnetic coupling between the lines (60, 62) provides the SFQ pulse repulsion.

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.

Abstract: The present invention provides ultra-wide band communication systems and methods, including multi-band ultra-wide band communication systems and methods. Methods and systems are provided in which frequency sub-bands of an ultra-wide band spectrum are allocated for signal transmission. An ultra-wide band transmission including the information is sent, including sending a signal over each of the plurality of sub-bands.

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: A dual function superconducting digitizer circuit which can selectively function either as an analog-to-digital converter (ADC) or as a time-to-digital converter (TDC). Superconducting ADCs and TDCs can provide performance far superior to that obtained using conventional electronics by taking advantage of the intrinsic properties—high switching speed, quantum accuracy, dispersion-less transmission lines, radiation hardness, and extremely low power dissipation—of superconductivity. Since both ADC and TDC functions are desired in most measurement systems, a dual-function digitizer is not only more attractive from a system integration perspective but is also more marketable.

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.

Abstract: An analog-to-digital converter for converting an analog input signal to a digital output signal is described. The ADC includes a comparator circuit having first to nth stages of comparators responsive to the analog input signal. Each comparator includes a plurality of magnetoelectronic devices for performing comparison function. Each magnetoelectronic device has one or more ferromagnetic elements capable of being switched into a first or second magnetization states. The amplitude of analog input signal upon exceeding a predetermined threshold level (Is or Vs) of a respective magnetoelectronic device sets a magnetization state of the respective magnetoelectronic device to the first state and the resulting output of the respective magnetoelectronic device to a HIGH state, and vice-versa. In one embodiment, the magnetoelectronic device is a Hybrid Hall Effect device. In another embodiment, the magnetoelectronic device is an isolator.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: The present invention provides a DAC constructed from a series of floating gate devices which are programmable to a series of predetermined values. Addressing one or more of the programmed floating gate devices, will select from a wide variety of analog outputs. Reprogramming the floating gate devices, can provide a different variety of analog outputs. For example, the floating gate devices can be preprogrammed to a different range of outputs matching a range of perceptible signals.

Abstract: A dual function superconducting digitizer circuit which can selectively function either as an analog-to-digital converter (ADC) or as a time-to-digital converter (TDC). Superconducting ADCs and TDCs can provide performance far superior to that obtained using conventional electronics by taking advantage of the intrinsic properties—high switching speed, quantum accuracy, dispersion-less transmission lines, radiation hardness, and extremely low power dissipation—of superconductivity. Since both ADC and TDC functions are desired in most measurement systems, a dual-function digitizer is not only more attractive from a system integration perspective but is also more marketable.

Abstract: Subranging techniques using “digital SQUIDs” are used to design systems with large dynamic range, high resolution and large bandwidth. Analog-to-digital converters (ADCs) embodying the invention include a first SQUID based “coarse” resolution circuit and a second SQUID based “fine” resolution circuit to convert an analog input signal into “coarse” and “fine” digital signals for subsequent processing. In one embodiment, an ADC includes circuitry for supplying an analog input signal to an input coil having at least a first inductive section and a second inductive section. A first superconducting quantum interference device (SQUID) is coupled to the first inductive section and a second SQUID is coupled to the second inductive section.

Abstract: According to the invention, oscillating signals are generated from analog signals by providing an analog signal having a variable slope or amplitude to a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first and a second stable operating region. The unstable operating region contains a first and a second reference point. The circuit is capable of producing an oscillating signal having a variable duty cycle, the duty cycle increasing as the variable operating point is positioned closer to the first reference point, the duty cycle decreasing as the variable operating point is positioned closer to the second reference point. The variable operating point is positioned substantially within the unstable region to produce the oscillating signal. The positioning of the operating point relative to the first and the second reference points is a function of the variable slope or amplitude of the analog signal.

Abstract: A method and apparatus for generating pulses that includes a circuit having a dynamical transfer function is disclosed. The circuitry exhibits oscillatory behavior when its operating point is forced to an unstable region of the transfer function by means of manipulating the transfer function. In an embodiment, a voltage source signal is used to manipulate the transfer function of the circuit. By manipulating the transfer function, the operating points can be dynamically set in the stable or the unstable region.

Abstract: Methods and apparatus for detecting ultra wide-band signals using circuitry having nonlinear dynamics characteristics are disclosed. The receiver circuit can be implemented using a simple tunnel diode or using an op-amp to provide dynamic characteristics. The detector can be used in a variety of modulation schemes, including but not limited to an ON-OFF keying scheme, an M-ary pulse position modulation scheme, and a pulse width modulation scheme. The approach requires only a single frame to detect the signal.

Abstract: A decoder for generating output pulses or oscillations in response to input analog waveforms includes a circuit having a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. In one embodiment, the circuit is characterized by having a resistive input impedance. The analog waveform forces the operating point of the circuit into its unstable and stable regions to produce oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: A method and apparatus that allows an analog waveform to carry multilevel of information is disclosed. This allows information capacity enhancement in pulse decoding communication system by concatenating several information regions in one cycle of analog waveform.

Abstract: An electric current switch circuit in accordance with the present invention is arranged so that an output of an IIL logic circuit is connected with the base of the first transistor of NPN type that switches ON or OFF the electric current. The first constant current source and the second transistor cause the first transistor to switch ON during a period when the output of the IIL logic circuit is in an OFF state, to switch OFF during a period when the output of the IIL logic circuit is in an ON state. Thus, only a voltage of 0.9V to 1.1V (the sum of a drop voltage across the first resistor and the base-emitter voltage) is applied to the base of the first transistor. Accordingly, a voltage less than the withstand voltage of the IIL logic circuit is applied to the base of the first transistor.

Abstract: A method and apparatus are provided for generating output pulses or oscillations in response to input analog waveforms which involves exciting, with a known but arbitrary analog waveform, a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. The analog waveform is characterized by having a first information region and a second information region. In response to sensing the first and second information regions, the operating point of the circuit is forced into its unstable and stable regions. This produces a sequence of oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: In one aspect of the invention, a system for quantizing an input signal having a time-varying voltage includes a voltage-to-current converter operable to convert the input signal to a proportional current. The system also includes a first negative differential resistance element coupled in series with the voltage-to-current converter. The first negative differential resistance element is operable to switch from a first state to a second state based on the proportional current. In addition, the system includes a reset circuit coupled in parallel with the first negative differential resistance element. The reset circuit includes a second negative differential resistance element, and the reset circuit is operable to reset the first negative differential resistance element to the first state based on a reset signal.

Abstract: A high-speed comparator and an associated method are disclosed. The comparator utilizes input circuitry to receive the input signal and utilizes resonant tunneling diode (RTD) circuitry to provide a high or low level determination. The RTD circuitry may be made weak compared to the input circuitry to eliminate hysteresis, and the comparators may be cascaded together to provide a positive-gain. In addition, clocked switches may be added to the cascaded comparator circuitry to create a clocked quantizer for analog to digital conversion. If desired, the RTD circuitry may include two RTDs connected to the output signal, and the input circuitry may include a transistor connected as a source-follower and transistor connected as a current sink.

Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: Subranging techniques using “digital SQUIDs” are used to design systems with large dynamic range, high resolution and large bandwidth. Analog-to-digital converters (ADCs) embodying the invention include a first SQUID based “coarse” resolution circuit and a second SQUID based “fine” resolution circuit to convert an analog input signal into “coarse” and “fine” digital signals for subsequent processing. In one embodiment, an ADC includes circuitry for supplying an analog input signal to an input coil having at least a first inductive section and a second inductive section. A first superconducting quantum interference device (SQUID) is coupled to the first inductive section and a second SQUID is coupled to the second inductive section.

Abstract: An oscillator/multiply-accumulator AID converter (100) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (100) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (102). The voltage controlled oscillator (102) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (104) that either passes or blocks the pulses depending on a gate control signal (103). When the pulses are passed by the gate circuit (104), a multiply-accumulator (106) multiplies the pulse by a binary coefficient (109) and accumulates the products (111) resulting from the multiplication during a predetermined time period.

Abstract: A &Dgr;-&Sgr; converter comprises a &Dgr;-&Sgr; modulator and a digital filter. The &Dgr;-&Sgr; modulator has a comparator having two resonant tunnel diodes connected to each other in series between two terminals and a field effect transistor connected in parallel to one of the resonant tunnel diodes, a conversion input transistor for converting an input voltage into electric current, a capacitor provided so that charge amount thereof is decreased by flow of electric current through the conversion input transistor and an electric potential proportional to the charge amount is used for the input electric potential to the comparator, and a feedback transistor, to which an output of the comparator is inputted, operating in such a way as to increase the charge amount of the capacitance element when the output of the comparator becomes a high level.

Abstract: A method and apparatus for generating pulses that includes a circuit having a dynamical transfer function is disclosed. The circuitry exhibits oscillatory behavior when its operating point is forced to an unstable region of the transfer function by means of manipulating the transfer function. In an embodiment, a voltage source signal is used to manipulate the transfer function of the circuit. By manipulating the transfer function, the operating points can be dynamically set in the stable or the unstable region.

Abstract: A continuous-time modulator comprises a modulator bridge having a bridge input terminal, an inverted bridge input terminal, a clock terminal and an inverted clock terminal. The modulator further comprises an input amplifier for amplifying an input signal and the input signal inverted and a bridge amplifier coupled to the input amplifier. The bridge is coupled to the bridge amplifier. The modulator further comprises a feedback amplifier coupled to the bridge, with the bridge amplifier coupled to the feedback amplifier. A clock amplifier for amplifying a clock signal and the clock signal inverted is also coupled to the bridge. An output signal is provided at an output terminal coupled to the bridge input terminal. An inverted output signal is provided at an output terminal coupled to the inverted bridge input terminal.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A sample-and-hold circuit is coupled to the input terminal, the inverted input terminal, the clock terminal, and the inverted clock terminal. A comparator circuit is coupled to the sample-and-hold circuit, the clock terminal, and the inverted clock terminal. A latch circuit is coupled to the comparator circuit, the clock terminal, and the inverted clock terminal. An output terminal having a quantized output signal is coupled to the latch circuit. An inverted output terminal having an inverted output signal is coupled to the latch circuit.

Abstract: Switch driver circuity having first and second output nodes with a current-voltage converter connected therebetween and providing current paths of first and second directions between the nodes, switching circuity connected therewith being switchable between first and second states respectively permitting current flow of a common preselected magnitude in respective first and second opposite directions producing potential differences between the first and second output nodes of a common magnitude but respective, opposite polarities.

Abstract: An electric current switch circuit in accordance with the present invention is arranged so that an output of an IIL logic circuit is connected with the base of the first transistor of NPN type that switches ON or OFF the electric current. The first constant current source and the second transistor cause the first transistor to switch ON during a period when the output of the IIL logic circuit is in an OFF state, while to switch OFF during a period when the output of the IIL logic circuit is in an ON state. Thus, only a voltage of 0.9V to 1.1V (the sum of a drop voltage across the first resistor and the base-emitter voltage) is applied to the base of the first transistor. Accordingly, a voltage of not more than a withstand voltage of the IIL logic circuit can be applied to the base of the first transistor.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the clock terminal coupled to the input terminal. A second negative-resistance device has a third terminal coupled to the clock terminal and a fourth terminal coupled to the inverted input terminal. A third negative-resistance device has a fifth terminal coupled to the input terminal and a sixth terminal coupled to the inverted clock terminal. A fourth negative-resistance device has a seventh terminal coupled to the inverted input terminal and an eighth terminal coupled to the inverted clock terminal. An output terminal for producing an output signal is connected to the input terminal.

Abstract: A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.