Abstract: A voltage following device is described, for the driving of a sampling network coupleable to an analog/digital converter, comprising at least one first transistor provided with a first terminal to receive an input signal, and a second terminal to provide an output signal to the sampling network which is representative of the input signal translation of an amount equal to a gate and source voltage of said at least one first transistor. The voltage following device having a driving network of said at least one first transistor to keep said gate and source voltage equal to a shift reference voltage.

Abstract: A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order “N” being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.

Abstract: A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Abstract: An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Abstract: A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

Abstract: An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.

Abstract: A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an Nth-order, having N resonators, with N being at least 2. The ADC also may have N-1 amplifiers, where the amplifiers directionally couple sequential pairs of the resonators. The ADC further includes a Josephson Junction (JJ) comparator. All N resonators connect in parallel to the JJ comparator, and the JJ comparator is providing an implicit feedback for all N resonators. A method for implementing the sigma-delta ADC without any explicit feedback loops is also disclosed.

Abstract: A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators.

Abstract: A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an Nth-order, having N resonators, with N being at least 2. The ADC also may have N?1 amplifiers, where the amplifiers directionally couple sequential pairs of the resonators. The ADC further includes a Josephson Junction (JJ) comparator. All N resonators connect in parallel to the JJ comparator, and the JJ comparator is providing an implicit feedback for all N resonators. A method for implementing the sigma-delta ADC without any explicit feedback loops is also disclosed.

Abstract: The present invention relates to an analog-to-digital converter (ADC) and an analog-to-digital conversion method employing a Josephson digital-to-analog converter (DAC) into an extremely accurate ADC of a physical metrology grade. The ADC includes: a front end ADC for converting an analog input signal into digital data; the Josephson DAC for receiving the digital data from the front end ADC and converting the received digital data into reference analog voltage; a differential ADC for extracting a difference voltage between a reference analog voltage of the Josephson DAC and an unknown input signal; and a data processor for summing output data of the differential ADC and output data of the front end ADC and outputting the summed result.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: A current cell matrix type of digital-to-analog (D/A) converter to prevent deterioration of a.c. characteristics on a current path for digital-to-analog conversion includes a array of current source cells arranged in a matrix configuration. Each current source cell includes a current source transistor to generate the cell current. During the regular operation, the cell current is flowed on output lines via a first transistor connected in cascode to the current source transistor. During the calibration operation, the cell current is flowed into a current comparator via a second transistor connected in cascode to the current source transistor. This prevents parasitic capacitance from being additively caused in switches for the first transistor and in another switch for the second transistor to prevent deterioration of a.c. characteristics on the current path.

Abstract: A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators.

Abstract: Digital mixers which permit mixing of asynchronous signals are constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Abstract: A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order “N” being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.

Abstract: A voltage following device is described, for the driving of a sampling network coupleable to an analog/digital converter, comprising at least one first transistor provided with a first terminal to receive an input signal, and a second terminal to provide an output signal to the sampling network which is representative of the input signal translation of an amount equal to a gate and source voltage of said at least one first transistor. The voltage following device having a driving network of said at least one first transistor to keep said gate and source voltage equal to a shift reference voltage.

Abstract: An analog-to-digital converter (ADC) is provided to determine a digital output value according to whether electric current flows between a plurality of probes, to which an input voltage is applied, and a plurality of electrodes. Therefore, high resolution and high speed operation is possible, but with lower power consumption.

Abstract: One embodiment of the invention includes a quantization circuit. The circuit comprises a sense resistor configured to provide a voltage that is indicative of a digital quantization of an input voltage. The circuit also comprises a plurality of resonant tunneling diodes (RTDs) arranged in series between the input voltage and the sense resistor. The circuit further comprises a sequencing circuit arranged in parallel with the plurality of RTDs and configured to conduct a portion of a current flowing between the input voltage and the sense resistor to define a sequential order of triggering of the plurality of RTDs in response to a given magnitude of the input voltage.

Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data buss. Signals on the data buss are used to drive the multiple peripheral devices.

Abstract: A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit.

Abstract: The length portion of part of a multiband superconductor line 10 is used as a closed circuit line part Rc that constitutes part of a closed circuit allowing passage of an electric current Io generated by an electric current source 12. Meantime, the line part extending and continuing into the closed circuit line part Rc is used as an open circuit line part Ro adapted to serve as an open circuit regarding the electric current source 12. By keeping the multiband superconductor line 10 under a temperature environment falling short of the critical soliton temperature and injecting a nonequilibrium electric current Io from the electric current source 12 into the closed circuit line part of the multiband superconductor line, it is rendered possible to induce generation of an interband phase different soliton So. The generated interband phase difference soliton So is forwarded as separated from the electric current Io to the open circuit line part Ro and is made to run therein.

Abstract: The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.

Abstract: Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another.

Abstract: A voltage comparator including a quantum tunneling coupled transistor and a method for tuning the voltage comparator. The comparator includes a quantum tunneling coupled transistor coupled to a resistor and is capable of operating above 10 Giga-samples-per-second or a clock rate of 10 GHz. The comparator has a low power consumption of about 1 mW excluding the power required for clock generation and independent from the sampling rate. The threshold or reference voltage of the comparator is controllable by adjusting the pulse height of the clock signal. The comparator has relatively low hysteresis estimated at about 1 mV.

Abstract: A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

Abstract: The present invention provides a DAC constructed from a series of floating gate devices which are programmable to a series of predetermined values. Addressing one or more of the programmed floating gate devices will select from a wide variety of analog outputs. Reprogramming the floating gate devices, can provide a different variety of analog outputs. For example, the floating gate devices can be preprogrammed to a different range of outputs matching a range of perceptible signals.

Abstract: A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.

Abstract: A method and apparatus for converting an analog waveform to a series of digital values includes receiving an input analog waveform to be digitized over a particular frequency band. A phase-sensitive frequency-domain representation of the input analog waveform is recorded. The phase-sensitive frequency-domain representation is read out and digitized to produce a spectral series of digital values. An output series of digital values that represent the analog waveform digitized over the particular frequency band is determined based on the spectral series. In some embodiments, the spectral series of digital values is produced with a conventional high dynamic range, low bandwidth digitizer that has a bandwidth at least a factor of two less than a width of the particular frequency band for digitizing the target analog waveform.

Abstract: An analog-digital converter is provided. The analog-digital converter includes: a comparing section for comparing an input signal voltage and an analog ramp voltage in which a voltage level gradually increases; and a latch section for storing a digital value of a digital ramp signal, in which a digital value of a voltage level gradually increases in synchronization with the analog ramp voltage when the analog ramp voltage or a voltage corresponding to the analog ramp voltage and the input signal voltage are equal. A voltage in which part or all of a plurality of analog ramp signals are added is used as the analog ramp voltage so that a gain is selectable.

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract: A DAC cell comprising: two or more PMOS core devices coupled in series between a power supply and a steering node; a first core transistor coupled between the steering node and a complementary power supply line and controlled by a control signal; and a second core transistor coupled between the steering node and an output of the DAC cell and controlled by a logical inverse of the control signal, wherein the control signal and its logical inverse direct a current from the steering node to either the complementary power supply line or to the output of the DAC cell based on the control signal.

Abstract: A quantum Turing machine constituted using a quantum bit created by localizing a phase difference soliton S between superconducting electrons existing in each of multiple of bands in a ring R0 that includes a ring main body R1 formed of a superconductor, and well-shaped portions W1, W2 formed with a reduced line-width at at least two positions on the ring main body R1, can easily constitute a quantum bit, can surely execute a basic logical operation, has multiple-bit capability and, moreover, can ensure sufficient time for executing a quantum algorithm.

Abstract: An integration type A/D converter in which a dynamic range is enlarged while keeping a simple circuit configuration is provided. Offset potential of an integrator is to be variable. Specifically, offset potential in proportion to input potential is supplied to the integrator. Since an operation point of the integrator is changed in accordance with the input potential, a dynamic range can be enlarged. Further, reference potential input to the integrator in discharging is to be variable. Specifically, reference potential having a constant difference from the offset potential is input to the integrator. Accordingly, time necessary for discharging and the input potential are in proportion, so that a simple circuit configuration which is one feature of the integration type ADC can be maintained.

Abstract: A superconducting analog-to-digital converter includes a superconducting input loop to which is applied an analog voltage to be converted to a digital format. The superconducting loop includes two Josephson junctions for converting said analog input voltage into a single flux quantum (SFQ) pulse stream having a frequency f1 which is directly proportional to the amplitude of the analog input voltage. The loop includes two outputs for distributing the pulse stream in a cyclical and staggered fashion onto the two loop outputs such that the frequency of the pulses along each one of the loop outputs is f½. Additional frequency divider circuits may be coupled to the loop outputs to produce pulse streams on N output lines having a frequency of f1/N.

Abstract: A system for converting an analog signal into a digital data stream includes a recurrent network with a plurality of converter circuits that individually receive the same analog signal as input. The circuits then generate a plurality of spike outputs that exhibit characteristics of the analog signal. Interconnecting feedback loops from each circuit output to the input of neighboring circuits queues the plurality of spike outputs to thereby self-organize the network. A digital clock is then used to establish predetermined time intervals for counting the spike outputs to create the digital data stream.

Abstract: A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.

Abstract: A method and apparatus for optically clocked optoelectronic track and hold (“OCOETH”) device. The OCOETH device includes a diode bridge, input node, at least two current sources and at least two photodetectors. The input node is operatively coupled to the diode bridge and can receive an analog input signal. The at least two current sources are operatively coupled to the diode bridge and can forward bias the diode bridge. The at least two photodetectors are operatively coupled to the diode bridge and can receive an optical input clocking signal, and can reverse bias and forward bias the diode bridge in response to the optical input clocking signal. The hold capacitor is operatively coupled to the diode bridge and can track the analog input signal when the diode bridge is forward biased, and can hold the analog input signal when the diode bridge switches from forward biased to reverse biased.

Abstract: A transmitter having a vertical BJT, capable of reducing power consumption, carrier leakage of a local oscillator and an error vector magnitude (EVM), is disclosed. In the transmitter, vertical BJTs implemented by a standard triplex well CMOS process are used in a frequency up-mixer and a baseband analog circuit including a DAC, an LPF, a VGA and a PGA, thereby improving the overall performance of the transmitter.

Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.

Abstract: A distributed resonator or filter in a continuous-time delta-sigma modulator is disclosed, where the transfer function of the resonator or filter repeats every Fs, where Fs is the sampling frequency of the modulator. On one side, like continuous-time delta-sigma modulators, the disclosed modulator does not require a high-precision track-and-hold, and additionally can take advantage of the high Q of distributed resonators. On the other side, like discrete-time delta-sigma modulators, the disclosed modulator is insensitive to feedback loop delays and can subsample.

Abstract: Disclosed is a single flux quantum circuit that uses a flux quantum as an information carrier, which generates a SFQ clock signal with little clock jitter and supplies the SFQ clock signal to a SFQ function circuit of the SFQ circuit, the SFQ function circuit is configured to include a current steering type single flux quantum circuit that is capable of concurrently achieving both a conversion function of converting a current signal into a SFQ signal and a comparator function of outputting a SFQ data signal in response to the amount of a to-be-compared current. At the same time, a SFQ clock signal oscillation circuit for generating a SFQ clock signal in response to the amount of DC voltage is formed.

Abstract: The present invention provides a DAC constructed from a series of floating gate devices which are programmable to a series of predetermined values. Addressing one or more of the programmed floating gate devices, will select from a wide variety of analog outputs. Reprogramming the floating gate devices, can provide a different variety of analog outputs. For example, the floating gate devices can be preprogrammed to a different range of outputs matching a range of perceptible signals.

Abstract: A switch having a first arrangement for providing a first set of first and second complementary intermediate signals; a second arrangement for providing a second set of third and fourth complementary intermediate signals; a third arrangement responsive to the first set of signals for providing complementary output signals; a fourth arrangement responsive to the second set of signals for providing complementary output signals; and a fifth arrangement for selectively activating the third means or the fourth arrangement in response to a control signal.

Abstract: An apparatus for converting an input analog audio signal into digital form including an analog-to-digital converter. An amplifier circuit and step-down transformer provide an interface for the input analog audio signal to the analog-to-digital converter. The step-down transformer includes a primary winding operably coupled to the amplifier circuit and a secondary winding operably coupled to the analog-to-digital converter. The amplifier circuit drives the primary winding with the input analog audio signal (or an amplified version thereof). The step-down transformer generates a stepped-down representation of the input analog audio signal at its secondary winding. Advantageously, the step-down transformer lowers the effective output impedance of the amplifier circuit, which reduces distortion in the audio analog input signal supplied to the analog-to-digital converter.

Abstract: In an A/D converter having a single flux quantum circuit having a flux quantum as an information carrier, a superconducting amplifier circuit driven by an AC current, and a semiconductor circuit, the operations of the circuits are synchronized with each other and a data signal from the single flux quantum circuit is transmitted to the semiconductor circuit. An AC current as the power source of a superconducting amplifier circuit is inputted as a master clock signal to the single flux quantum circuit and the semiconductor circuit to synchronize the operations of the circuits with the master clock signal. The single flux quantum circuit has a clock signal frequency multiplier circuit, a demultiplexing circuit and a memory circuit.

Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.

Abstract: The converter of the invention essentially comprises, along the path of the microwave signal to be measured, a series of superconducting loops spaced apart by x/2 and each having a critical current junction facing which an optical waveguide is placed. Each of these loops absorbs, as the case may be, a bit of the wave to be measured, their inductances following an increasing geometric progression of common ratio 2 and their critical currents following a decreasing geometric progression of common ratio ½.