Abstract: The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a sigma-delta ADC, and to a digital control loop comprising the same. According to the present invention, part of the filtering function required for noise-shaping is implemented in the feedback path. By suitably distributing the poles over the forward and feedback paths, stable operation can be achieved while offering low latency.

Abstract: A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.

Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.

Abstract: There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ?? modulation and a second modulated signal obtained by subjecting the input signal to the ?? modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.

Abstract: A device for measuring electromyographic signals 2 is adapted to receive, through multiple channels “C”, electromyographic signals “EMG” sensed by a plurality of electrodes 3 arranged on a patient “P”. The device 2 includes: a conditioning circuit 21; a conversion circuit 22; a transmission circuit 23 to transmit the digitalized signals to a central control unit 1; an external casing 20 to enclose the circuits (21, 22, 23). The conditioning circuit 21 can be assembled modularly by establishing a cascade connection of one or more conditioning circuits 21. The conversion circuit 22 can be assembled modularly by connecting in parallel one or more conversion circuits 22 to vary the number of channels “C” through which electromyographic signals “EMG” are received. The conditioning circuits 21 and the conversion circuits 22 overlap at least partially to limit the dimensions of the external casing 20, ensuring wearability on the patient “P”.

Abstract: A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N?1 level quantizer function.

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract: Disclosed is a completely digital solution for a new type of root-mean-square to direct current conversion (RMS-to-DC) apparatus. The design is based on delta-sigma modulation (?-?M) and the direct nonlinear processing of the ?-? modulated pulse stream. The only external component of the integrated circuit (IC) is capacitor C. The disclosed apparatus consists of low power consuming components which are simple, reliable and inexpensive.

Abstract: A semiconductor device measures a state of a MEMS as a first voltage variation at a sensing node. The state of the MEMS includes a capacitance. A first capacitor is coupled between the sensing node and an input of an integrator for transferring the first voltage variation to a second node as a first signal. A second voltage variation is routed through a second capacitor to the second node as a second signal. The integrator integrates the first signal and second signal to provide an integrated signal. An ADC has an input coupled to an output of the integrator and converts the integrated signal to a digital signal representative of the capacitance of the MEMS. A DAC has an input coupled to the output of the ADC. A second capacitor is coupled between an output of the DAC and the sensing node.

Abstract: A digitized system operates to receive one or more analog signals from a sensor or other component and convert the analog signals to one or more digital signals. An analog-to-digital converter comprises a loop filter, a quantizer and one or more feedback digital-to-analog converters. A gain component provides coefficients along different points of a signal processing path to extend a bandwidth of the analog-to-digital converter. The gain component can modify a signal transfer function of the analog-to-digital converter while preserving a noise transfer function in order to process a signal in a higher frequency band in an extended mode of operation than other signals being processed in a normal operating mode.

Abstract: A base station device includes: a converting unit that converts a transmission signal with a multi-bit quantization bit rate to a signal with a quantization bit rate smaller than the quantization bit rate of the transmission signal; a first amplifier that amplifies the signal; an extracting unit that extracts a noise component generated in the signal due to the conversion; a second amplifier that amplifies the noise component; a combining unit that combines the signal amplified by the first amplifier with the noise component amplified by the second amplifier to remove a noise component included in the amplified signal; and an adding unit that adds, based on an error between the signal from which the noise component has been removed and the transmission signal, distortion to the signal that is input to the first amplifier or the noise component that is input to the second amplifier.

Abstract: A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter (44) to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (44); a digital-to-analog converter (46, 47) to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (44), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators (41, 42) in series, each having a feedback path comprising the analog-to-digital converter (44) in cascade with a digital-to-analog converter (46, 47), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.

Abstract: An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

Abstract: A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit.

Abstract: A motor control device has a motor current detector for detecting current in windings to control the operation of a motor with a stator having three-phase windings. The motor control device includes a digital controller for outputting a PWM switching signal, a power converter for applying drive voltage to the windings using the PWM switching signal, a motor current detector for converting current flowing in the windings to analog voltage, a ?? AD converter for converting the analog voltage to a 1-bit digital signal, an AD conversion decimating filter for generating a detected motor current value from the 1-bit digital signal, a clock generator for generating a clock for the ?? AD converter and the AD conversion decimating filter, and a stop signal generator for generating a clock stop signal for stopping the clock of the clock generator for a predetermined period.

Abstract: A delta-sigma analog-digital converter and method to generate a digital output signal from an analog input signal are provided. A delta-sigma analog-digital converter includes a loop input signal generating unit configured to generate a loop input signal based on both the analog input signal and a feedback signal that is based on the digital output signal, a noise shaping unit including a plurality of feedback loop stages that respectively filter fed back local error signals that are respectively based on the digital output signal, to generate a loop output signal with reduced noise over the loop input signal, and a quantizing unit configured to quantize the loop output signal and to generate the digital output signal based on the quantized loop output signal.

Abstract: This disclosure describes techniques for controlling spectral aggressors in a sensing device that uses a chopper amplifier to amplify an input signal prior to sampling the signal. In some examples, the techniques for controlling spectral aggressors may include generating a chopper-stabilized amplified version of an input signal based on a chopper frequency, sampling the chopper-stabilized amplified version of the input signal at a sampling rate to generate a sampled signal, and analyzing a target frequency band of the sampled signal. The chopper frequency and the sampling rate may cause spectral interference that is generated due to the chopper frequency to occur in the sampled signal at one or more frequencies that are outside of the target frequency band of the sampled signal. The techniques for controlling spectral aggressors may reduce the noise caused by the chopper frequency in the resulting sampled signal, thereby improving the quality of the signal.

Abstract: A circuit includes a first digital filter that generates a first output based on a digital input and a first digital output signal. A first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. A second digital modulator generates a second output and a second error output based on the first error output. A second digital filter generates a second digital output signal based on the second output, and a third digital filter generates the feedback error output based on the second error output. The second digital output signal and the second error output are based on the first error output amplified by a predetermined gain.

Abstract: A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.

Abstract: Disclosed is a feed forward sigma-delta analog to digital conversion (ADC) modulator. The disclosed structure combines feedback circuit, adder circuit and quantization circuit, and has advantages of high stability, without active circuit, and using successive approximation register (SAR) control circuit, thus realizes the function of multi-bit quantization by using only one comparator.

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Abstract: A sigma-delta (??) analog-to-digital converter (ADC) comprises a main ?? modulator configured to receive an analog input signal at a main ?? modulator input and to provide a main digital output signal representative of the analog input signal and an auxiliary ?? modulator configured to receive an auxiliary input signal at an auxiliary ?? modulator input and to provide an auxiliary digital output signal, wherein the ?? ADC comprises a shared integrator stage, the shared integrator stage is configured to be used by the main ?? modulator and the auxiliary ?? modulator, wherein, alternatingly, the shared integrator stage is selectively communicatively coupled to receive the analog input signal when configured to be used by the main ?? modulator and selectively communicatively coupled to receive the auxiliary input signal when configured to be used by the auxiliary ?? modulator.

Abstract: A modulator is configured to respond to input swings by providing a feedback voltage via a feedback path to compromise an increase in noise and distortion power with increasing signal power at signal levels exceeding a predetermined threshold. A digital-to-analog converter (DAC) generates a feedback voltage with a resistor string biased with a given current and switches as a function of an input value to mitigate the voltage swing at a summing node.

Abstract: A digital microphone includes: a cavity resonator operatable in a micrometer, millimeter, or electromagnetic waveband, the cavity resonator having a metal wall including a conductive membrane 32 that vibrates in response to incident acoustic waves and converts the shift of the membrane 32 into a resonance frequency of the cavity resonator; an FM-signal generator that modulates the resonance frequency of the cavity resonator in response to the shift of the membrane 32 and outputs FM signals from the metal wall other than the membrane; and a ??-modulated-signal generator that generates ??-modulated signals from the FM signals. The FM-signal generator includes a slot 36, a micro-strip line 38, and a negative resistive element 40. The ??-modulated-signal generator includes an edge detector 42.

Abstract: Systems and methods are disclosed to integrate signals. Some embodiments include an integrator comprising an active input; a passive input; a first integrator having a first integrator input and a first integrator output; a second integrator having a second integrator input and a second integrator output; a first plurality of switches coupled with the first integrator input, the second integrator input, the active input, and the passive input; a second plurality of switches coupled with the first integrator output and the second integrator output; and a controller. The controller may be configured to control the operation of the first plurality of switches to switch the active input between the first integrator input and the second integrator input, and control the operation of the first plurality of switches to switch the passive input between the first integrator input and the second integrator input.

Abstract: A method of implementing Correlated Multi-Sampling (CMS) in an image sensor with improved analog-to-digital converter (ADC) linearity starts with an ADC circuitry included in a readout circuitry that generates a plurality of uncorrelated random numbers used as a plurality of ADC pedestals for sampling image data. A Successive Approximation Register (SAR) included in the ADC circuitry stores a different one of the ADC pedestals before each sampling of the image data. The ADC circuitry samples an image data from a row a plurality of times against plurality of ADC pedestals to obtain a plurality of sampled input data. The ADC circuitry converts each of the plurality of sampled input data from analog to digital, which includes performing a binary search using the SAR. Other embodiments are also described.

Abstract: An analog-to-digital converter circuit is described.

Abstract: Provided is an audio output device capable of preventing noises and improving the S/N ratio even if no audio signal is inputted in the middle of the input of audio signals, or even if an audio-signal input state and a no-signal state are alternately repeated. In the provided audio output device, a multiplier is provided on the input side of each of the delayers. Each multiplier multiplies the addition output of the corresponding one of adders by a multiplier coefficient supplied by the coefficient counter. If there is no input of digital audio signals into a ?? modulator, the counter control circuit decreases the output of the coefficient counter down to 0 stepwise at predetermined intervals.

Abstract: A high-order delta-sigma modulator is realized with amplifying/integrating circuits each having a small circuit scale, to thereby provide a small-size and low-power consumption delta-sigma modulator having a high precision. The delta-sigma modulator including the amplifying/integrating circuits connected in series in a plurality of stages has a delta-sigma modulator configuration in which one of adjacent amplifying/integrating circuits includes a delay integrating circuit and another thereof includes a non-delay integrating circuit. In an actual circuit, one amplifying circuit is operated in a time division manner to be shared between the adjacent amplifying/integrating circuits. The circuit scale is reduced in this way.

Abstract: Techniques and mechanisms provide a technique for compression using an approximation of a mu-law algorithm.

Abstract: There is provided a ?? modulator including a loop filter for inputting an m-value digital signal into a subtractor, an n-value quantizer for inputting a first output signal to be output from the loop filter and outputting a second output signal as an n-value digital signal, and a selecting device for inputting the first output signal and the second output signal therein, feeding back the first output signal to a subtractor of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to the subtractor of the loop filter when the absolute value is less than a predetermined value. The predetermined value in the selecting device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.

Abstract: Provided is a delta-sigma modulator having a differential output, the modulator including a switched-capacitor integrator configured to generate a non-inverted integral signal and an inverted integral signal and also including a switched-capacitor circuit configured to sample an input signal based on a control signal and to integrate the feedback signal and the input signal based on the control signal and also a feedback circuit configured to generate the feedback signal.

Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Abstract: Provided is a system, method, and computer program product for improving the quality of voice communications on a mobile handset device by dynamically and adaptively selecting adjusting the latency of a voice call to accommodate an optimal speech enhancement technique in accordance with the current ambient noise level. The system, method and computer program product improves the quality of a voice call transmitted over a wireless link to a communication device dynamically increasing the latency of the voice call when the ambient noise level is above a predetermined threshold in order to use a more robust high-latency voice enhancement technique and by dynamically decreasing the latency of the voice call when the ambient noise level is below a predetermined threshold to use the low-latency voice enhancement techniques. The latency periods are adjusted by adding or deleting voice samples during periods of unvoiced activity.

Abstract: A quantization circuit includes a quantizer configured to provide a quantized sample using an input quantity and an error estimator configured to determine a quantization error of the quantized sample. An error corrector is configured to correct the quantized sample by a correction value depending on the quantization error.

Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

Abstract: A delta sigma modulator (DSM) may be improved by configuring it to set the high-order nonlinear function values to zero when the quantization value being output is at its minimum or maximum value. In one embodiment, a DSM may include at least a quantizer having an input responsive to one of two state variables of the DSM and providing a feedback signal and a modulator output signal. The DSM may also include two mutually nonlinear function blocks, each applying a nonlinear function to the feedback from the quantizer, to form two mutually nonlinear feedback signals. At least one of the nonlinear functions applied by the function blocks may comprise a zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer.

Abstract: Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.

Abstract: A ?? modulator converts an input analog quantity into a digital value quantized with a predetermined number of bits and outputs the digital value. The ?? modulator includes an integrator that includes a capacitor and integrates a difference between the input analog quantity and an analog quantity acquired from D/A conversion of the output digital value by a D/A converter; a quantizer that quantizes an analog quantity acquired from integration by the integrator; and a digital integrator that carries out an integration operation on data acquired from quantization by the quantizer.

Abstract: Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a digital output stream of a forward circuit path using a digital modulator or digital chopper circuit in a feedback circuit to create a DAC digital input signal responsive to a chopper clock signal having a clock rate lower than a DSM quantizer clock signal, and chopping a differential DAC output signal using an analog chopper circuit responsive to the chopper clock signal to provide a differential feedback signal to a forward circuit path of the DSM to mitigate DAC error induced offset and even order harmonic distortion in the digital output stream.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Devices and methods convert signals into pulse-width modulated signals. A noise-shaping loop can be clocked at a lower frequency than a PWM modulator, resulting in lower power requirements, and greater ease of synchronization. The delay introduced by the noise-shaping loop can be reduced by implementations using sample-and-hold devices, look-up tables and logic circuitry to predict output signals.

Abstract: A continuous-time ??-ADC (1) is disclosed. It comprises a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ??-ADC (1) at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (5). Furthermore, the ??-ADC (1) comprises one or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5). Moreover, the ??-ADC (1) comprises a continuous-time analog network (20) arranged to generate the analog input signal to the quantizer (5) based on the feedback signal(s) from the one or more DACs (10a-b) and an analog input signal to the ??-ADC (1). At least one DAC (10b) of the one or more DACs (10b) comprises two switched-capacitor DACs (40, 50) arranged to operate on the same input but with a mutual delay in time.

Abstract: The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M?1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N?1 bit(s) ahead of the LSB while the number N is an integer greater than one.

Abstract: A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients.

Abstract: An asynchronous analog-to-digital converter (AADC) and a method of using the AADC are shown. The AADC includes a digital-to analog-converter (DAC), a continuous-time comparator that provides an output including a digital value of the DAC and a time value, and a first and a second continuous-time summer, each connected to receive an analog differential input on a first input, to receive a differential output of the DAC on a second input, and to provide a difference between the analog input and the output of the DAC to the continuous-time comparator and to an error estimator. The continuous-time comparator provides the output responsive to the difference between the analog input and the output of the DAC being zero.

Abstract: A system and method: provide a digital input signal to a digital-to-analog converter (DAC) which, in response to a DAC clock signal, converts the digital input signal to an analog output signal; generate from the DAC clock signal a sampling clock signal having pulses spaced apart from each other in time by a plurality of DAC clock periods, wherein a timing of at least one of the pulses is offset with respect to the DAC clock signal by a first fraction of a DAC clock period, and a timing of at least an other one of the pulses of the sampling clock signal is offset with respect to the DAC clock signal by a second fraction of the DAC clock period; sample-and-hold the analog output signal in response to the sampling clock signal; and digitize the sampled-and-held analog output signal to output digital values representing the sampled-and-held analog output signal.

Abstract: A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

Abstract: A delta-sigma analog-to-digital converter (?? ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.