Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

Abstract: In some embodiments, a method of operating a sigma-delta analog-to-digital converter (ADC) includes converting an analog input signal into a sequence of digital data using a sigma-delta modulator of the sigma-delta ADC, setting a first configuration for a decimation filter of the sigma-delta ADC according to a first condition of a measurement window, filtering the sequence of digital data using a low-pass filter (LPF) of the decimation filter, and in response to a change in the measurement window, setting a second configuration for the decimation filter according to a second condition of the measurement window.

Abstract: The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a ?? modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

Abstract: An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

Abstract: An optical sensor arrangement (10) comprises a photodiode (11) for providing a sensor current (IPD) and an analog-to-digital converter arrangement (12) which is coupled to the photodiode (11) and determines a digital value of the sensor current (IPD) in a charge balancing operation in a first phase (A) and in another conversion operation in a second phase (B).

Abstract: A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.

Abstract: Provided is a selection device including an acquisition section for acquiring digital selection signals, and an output section for outputting selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. The selection device is characterized in that: each selection signal is for commanding the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells.

Abstract: An information processing apparatus includes a quantization unit that further quantizes a quantized first code, and hence generates a second code; an inverse quantization unit that inversely quantizes the second code quantized by the quantization unit, and hence generates a third code; a calculating unit that calculates a difference between the first code and the second code; a first encoding unit that encodes the second code; and a second encoding unit that encodes the difference calculated by the calculating unit.

Abstract: A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.

Abstract: A semiconductor device and operating method thereof are provided.

Abstract: A position-determining apparatus, such as a GPS receiver, determines the position of the mobile device based on the time of flight of a transmitted probe signal using a method in which sections of the received signal is classified into two or more categories and accumulated according to categories before being used to compute the convolutions familiar in the context of a matched filter. Using the method of the present invention to compute the convolutions, and optionally applying additional time-saving techniques described herein, a position determination is achieved using a number of arithmetic operations that is significantly reduced from that required in prior art methods to compute the convolutions. The reduced number of arithmetic operations can reduce significantly the power consumption required of a device carrying out a method of the present invention, and thereby realizing a significant advantage.

Abstract: An analog-to-digital converter (ADC) is provided includes a first sigma-delta modulator (SDM) electrically coupled to a first signal input. The first SDM includes a first summing junction configured to receive a plurality of inputs to the first SDM. The ADC further includes a second sigma-delta modulator (SDM) electrically coupled to a second signal input. The second SDM includes a second summing junction configured to receive a plurality of inputs to the second SDM. The first SDM also includes a cross-coupled feedback loop from an output of the first SDM to a negative input of the first summing junction and to a positive input of the second summing junction. The second SDM also includes a cross-coupled feedback loop from an output of the second SDM to a negative input of the first summing junction and to a negative input of the second summing junction.

Abstract: An impedance-to-digital converter is provided. A sensible impedance range of the impedance-to-digital converter is adjustable by changing magnitudes of signals inputted thereto.

Abstract: A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.

Abstract: A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

Abstract: A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter.

Abstract: A cellular radio architecture that includes a receiver module having a delta-sigma modulator that includes a plurality of gm cells configured in stages, where each stage includes at least two gm cells and an LC filter circuit. The gm cells in each stage can be controlled to be active or inactive to convert, for example, the modulator from a fourth order modulator to a second order modulator to reduce power dissipation. Further, the gm cells can be controlled to optimize a dynamic range of the modulator and to redirect current from inactive cells to active cells in order to optimize power consumption.

Abstract: A multiplying analog to digital converter including an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.

Abstract: A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.

Abstract: A cellular radio architecture for a vehicle that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a triplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the triplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the triplexer.

Abstract: An apparatus includes a low noise amplifier (LNA) having an input configured to receive a radio frequency signal. The apparatus also includes a notch filter coupled to an input of the LNA. The notch filter is configured to attenuate the radio frequency signal at a notch frequency.

Abstract: In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output node of the reference buffer wherein the first switched capacitor comprises at least one first capacitor and at least one first switch may be provided. The method may include coupling a passive network to the output node of the reference buffer in response to a presence of a condition for encountering the voltage kickback in order to create an approximately equal and opposite voltage kickforward by the passive network to at least partially neutralize the voltage kickback.

Abstract: A transmitter circuit comprises: an input, an encoder circuit, and a transmitter. During operation, the transmitter circuit receives an input signal. The encoder circuit encodes the received input signal into an encoded signal. The encoder circuit produces the encoded signal: i) to indicate changing states of the input signal, and ii) to include a supplemental transient signal with respect to the received input signal. The transmitter transmits the encoded signal from an output of the first circuit over a link to a second circuit such as a receiver circuit. A receiver decodes the encoded signal to reproduce a rendition of the input signal to control remote power supply circuitry. Presence of the supplemental transient signal in the encoded signal indicates to the receiver circuit that the first circuit actively transmits the output signal even though there may not be any change to a current state of the input signal.

Abstract: A switched capacitor circuit includes a first sampling circuit having a first sampling capacitance element. The first sampling circuit receives an input voltage and outputs a sampled voltage according to a first sampling operation. A quantizer quantizes the sampled voltage output from the first sampling circuit and outputs a quantized value corresponding to the sampled voltage. A digital-to-analog converter outputs an analog signal in accordance with the quantized value from the quantizer. A first logic circuit outputs an instruction to start a sampling operation of a second sampling circuit, which is configured to sample the analog signal output from the digital-to-analog converter, when the quantizer completes quantization of the sampled voltage.

Abstract: A ?? ADC includes a forward path, a feedback path, and offset compensation circuitry. The forward path is configured to convert an analog input signal to a digital output signal and includes analog chopper circuitry configured to shift the analog input signal to a chopper frequency to generate a chopped analog signal. The feedback path includes a ?? DAC configured to convert a digital offset compensation signal configured to compensate for offset error in the analog input signal to an analog feedback signal that is subtracted from a forward path signal. The offset compensation circuitry is configured to accumulate a chopped digital signal from the forward path to generate a digital offset error signal; add the digital offset error signal to the digital output signal to generate the digital offset compensation signal; and provide the digital offset compensation signal to the ?? DAC.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit.

Abstract: The present invention addresses the problem of reducing a circuit scale without causing a reduction in processing efficiency. This multi-stage filter processing method measures, at each stage, either the number of input data or the number of intermediate data that is generated by filter calculation processing during the stages before the final stage is reached. Coefficient data regulating for each stage the number of data sufficient to perform the filter calculation processing is held. Input data or the intermediate data that is generated in a current stage is held in a memory until the number of data reaches the number of data sufficient to perform the filter calculation processing in the current stage, on the basis of the coefficient data. When the number of data has reached, the filter calculation processing for the current stage is performed on the input data or the intermediate data that was held.

Abstract: A digital error feedback system, method and device adjusts the output voltage of a power converter. The digital error feedback system uses a digital comparator and one or more digital signal generators to generate and compare a digital signal corresponding to the output voltage to a reference digital signal in order to determine the current amount of error in the output voltage. The error is then able to be compensated for using a control signal generated based on the determined error.

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.

Abstract: As one embodiment a drive circuit is disclosed. When a three-value signal including a value representing zero is input, the drive circuit outputs two two-value signals that drive two drive elements such that the difference between values representing the two two-value signals corresponds to a value representing the input three-value signal. When the value of the input three-value signal represents zero, output signals are determined in accordance with the input history of the three-value signal. The drive circuit may also be provided with a memory that records a flag value that is reversed in accordance with the input history of the input three-value signal, and the combination of the output two two-value signals being determined in accordance with the flag.

Abstract: A power router apparatus includes: a power divider that divides predetermined power into a plurality of divided powers including first divided power and second divided power; a first code modulator that code-modulates the first divided power with a first modulation code to generate first code-modulated power, which is alternating-current power; and a second code modulator that code-modulates the second divided power with a second modulation code to generate second code-modulated power, which is alternating-current power.

Abstract: A touch control detection system, a delta-sigma modulator and a modulating method thereof are provided. The delta-sigma modulator includes a quantizer and N integrating units. The quantizer generates a modulating result signal. The integrating units are coupled in series. Each of the integrating receives an input signal, and each of the integrating units receives a plurality of gain parameters, N is a positive integer. The quantizer quantizes a signal on an output end of the Nth stage integrating unit according to an error signal for generating the modulating result signal. A center frequency of a noise transfer function (NTF) of the delta-sigma modulator is adjusted according to the gain parameters, and the gain parameters are determined according to a frequency of the input signal.

Abstract: Various embodiments of the present technology may comprise a method and device for a delta-sigma ADC. The method and device may comprise receiving an input signal to at least two parallel-connected first-stage integrators and corresponding feedback DACs, and simultaneously integrating the input signal by each of the first-stage integrators. The method and device may further comprise a second stage integrator connected in series with the first-stage integrators, a quantizer, and digital to analog converters, coupled between the output of the quantizer and the inputs of the first-stage integrators.

Abstract: A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Abstract: A low power consumption sigma-delta modulator architecture capable of dynamic detection of output signal strength to change dynamic range, a method for implementing low power consumption circuit thereof, and a method for automatically correcting and extending dynamic range of the sigma-delta modulator are provided. An automatic correction unit is utilized to detect system output signal strength of the sigma-delta modulator, compare system input signal specifications to come out multiple sets of dynamic range curves, and thereby extract an appropriate combination of system order and feed-forward coefficients so as to extend the system dynamic range. The circuit architecture of the automatic correction unit is in a digital circuit form, including a digital signal processor, a counter and register array, a comparator, a digital coefficient controller, a feed-forward gain control unit and a system order control unit.

Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

Abstract: A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Abstract: A method and device for handling an in-phase and quadrature (“I/Q”) channel mismatch of an I/Q down-converted signal, and a use of the device. A discrete-time complex valued signal r(n) based on an analog-to-digital conversion of the I/Q down-converted signal is obtained. The obtained discrete-time complex valued signal r(n) is oversampled by a factor of two or more. An intermediate signal v(n) is formed from the discrete-time complex valued signal r(n). The intermediate signal v(n) corresponds to the real part of a ?/2 frequency shifted version of the obtained discrete-time complex valued signal r(n). A procedure for obtaining an estimate of a frequency dependent mismatch of a two-channel time-interleaved analog-to-digital converter (“TI-ADC”) is applied on the formed intermediate signal v(n). Thereby a TI-ADC mismatch estimate is obtained. The I/Q channel mismatch is estimated and/or compensated based on the obtained TI-ADC mismatch estimate.

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Abstract: An audio processing device includes an initial processing module to generate a stream of frequency coefficients based on input audio data, a watermarking module to embed a digital watermark into the stream of frequency coefficients to generate a modified stream of frequency coefficients, and a final processing module to process the modified stream of frequency coefficients to generate output audio data. In some implementations, the input audio data comprises unencoded audio data, the initial processing module comprises a frequency domain transform module to perform a time-to-frequency domain transform to generate the unencoded audio data, and the output audio data is encoded audio data. In other instances, the input audio data comprises encoded audio data, the initial processing module comprises an initial decoding module to partially decode the encoded audio data to generate the stream of frequency coefficients, and the output audio data is decoded audio data.

Abstract: A differential amplitude pulse width modulation (aPWM) digital to analog converter (DAC) is provided, including an aPWM module for generating differential pulse from an input digital audio data stream, a power driver module for providing energy to a terminal load and a filter for removing unwanted harmonic signal to reconstruct analog signal, wherein the aPWM module further includes a PWM pulse generator to convert the digital input numerical code to a series of time domain pulse width; an amplitude modulation unit, for increasing time domain resolution of the pulse width, and a differential pulse width generator to convert series of PWM pulse into voltage and time domain differential form; the power driver module further comprising a pulse amplitude selector, connected to a power source, and two power stages connected respectively to the pulse amplitude selector.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches, with each of the processing branches including a bandpass noise-shaping circuit, a sampling/quantization circuit coupled to an output of the bandpass noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the sampling/quantization converter circuit back into the bandpass noise-shaping circuit. A center frequency of the digital bandpass filter in each processing branch corresponds to a stopband region in a quantization noise transfer function for the bandpass noise-shaping circuit in the same processing branch.

Abstract: A device for quantizing an analog input signal, for supply of a continuous-time output signal quantized using a plurality of bits, includes a sign analysis electronic circuit, configured to supply a first signal representative of a first sign bit of the output signal, and an envelope analysis electronic circuit, including a comparator/quantizer with two inputs one of which receives the analog input signal, configured to supply a second signal representative of at least a second bit of the output signal, as a quantized envelope signal, and a feedback loop with continuous-time digital-to-analog conversion of the quantized envelope signal, arranged between the output and the other of the two inputs of the comparator/quantizer. The quantized envelope signal is a signal of which a low pass filtering is representative of the amplitude of an envelope signal of the input signal and the feedback loop includes a low pass filter.

Abstract: Imaging system, imaging system unit cell, and a method of detecting an image. One example of an imaging system unit cell includes a photodetector configured to generate a photo-current, a transimpedance amplifier circuit configured to integrate an electrical charge accumulated from the photo-current during an integration period and provide an integration voltage at an output node, and quantization circuitry configured to generate a digital signal during the integration period based at least in part on the integration voltage, the quantization circuitry including a comparator configured to receive the integration voltage and a voltage ramp signal, compare the integration voltage and the voltage ramp signal, and determine an intersection of the voltage ramp signal and the integration voltage at an intersection time, and a latch coupled to the comparator and configured to latch a digital counter value corresponding to the intersection time, the digital signal including the digital counter value.

Abstract: Methods, systems, and devices for conducting a seismic survey. The system includes at least one seismic sensor configured to supply a signal responsive to reflections of acoustic energy from an earth surface; and at least one processor configured to: mitigate sensor offset from a sequence of samples representative of the signal by filtering the sequence of samples using a symmetrical-in-time finite impulse response (FIR) filter. The FIR filter may approximate a sinc-in-frequency filter. The at least one processor may be configured to process the sequence of samples using a plurality of filter stages that are rectangular in time. The length of one filter stage of the plurality of filter stages may be different than the length of another filter stage of the plurality of filter stages.

Abstract: A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a multiplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer.

Abstract: The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a sigma-delta ADC, and to a digital control loop comprising the same. According to the present invention, part of the filtering function required for noise-shaping is implemented in the feedback path. By suitably distributing the poles over the forward and feedback paths, stable operation can be achieved while offering low latency.