Abstract: A topology for converting an analog input signal at an input port into a corresponding digital output signal at an output port includes a plurality of substantially identical ADC stages. Each ADC stage includes a multi-bit sigma-delta loop having an analog input coupled to the input port and a digital output coupled to a combining circuit. The combining circuit adds the outputs of the ADC stages to generate the digital output signal.

Abstract: A small sized digital Nyquist filter having a high processing speed is provided. A delay in a delay element in the digital Nyquist filter is synchronized with a symbol rate of an input signal, and filtering coefficients at respective taps in the filer are sequentially selected synchronously with a sampling clock in accordance with a predetermined procedure, thereby reducing the number of taps to 1/oversampling number.

Abstract: An analog to digital converter oversamples an image signal, and uses the oversampled information to obtain additional resolution. The analog to digital converter is included in an image sensor device having a photosensor array of photosensitive of pixels and a plurality of analog to digital converters. Each of the analog to digital converters is adapted to produce a digital output with a first specified bit resolution. An interpolator is adapted to receive an output thus produced from an analog to digital converter and produce a digital output with a second specific bit resolution.

Abstract: A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

Abstract: The invention relates to an analog to digital converter computing all the bits in parallel or sequentially, without using decoding logic having an analog input and a digital output, wherein given the analog signal x, each bit can be computed by applying a formula containing a non linear periodic function which may be sine shaped or pulse shaped.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.

Abstract: An interpolation circuit for generating interpolation and extrapolation differential voltages to a first and second differential input voltages, comprises a first and second differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal and their respective non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the non-inverted output terminals of the first and second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array.

Abstract: This invention provides an AD converter circuit and an AD conversion method capable of executing AD conversion up to the lowest bit properly even under a high-speed operation. The AD converter circuit 1 comprises high-order-comparators D1-D3, low-order comparator D0 and a comparison reference voltage source 10 having seven reference voltage output points V1-V3, Va-Vd. The reference voltage output points V1-V3 are connected to the reference voltage terminals of the high-order-comparators D1-D3. The reference voltage output points Va-Vd are connected to a point A having parasitic capacitance through analog switches SWA-SWD. The point A is connected to the reference voltage terminal of the low-order comparator D0 through an analog switch SW2 and an input voltage VIN through an analog switch SWE.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to output a held signal, a buffer circuit to buffer the held signal to output a buffered signal, and a comparator circuit to compare the buffered signal with a reference voltage.

Abstract: The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages, inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

Abstract: A tunable analog-to-digital converter which generates samples having M-bits for use with an operating circuit. The operating circuit generates a first enable signal to instruct the analog-to-digital converter to turn on. Additionally, a sensor generates an analog signal in response to a condition. The tunable analog-to-digital converter includes a primary analog-to-digital converter which receives the analog signal and converts the analog signal to a primary digital signal upon receipt of the first enable signal. The tunable analog-to-digital converter also includes a comparator and a secondary analog-to-digital converter. The comparator compares the value of the primary digital signal to a predetermined value and generates a second enable signal depending on the value of the primary digital signal and the predetermined value. The secondary analog-to-digital converter receives the analog signal and converts the analog signal to a secondary digital signal upon receipt of the second enable signal.

Abstract: The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

Abstract: There is provided an A/D converter circuit capable of high-speed operation without fluctuation of reference voltage due to comparison operation by high-order comparators influencing voltage level of reference voltage of voltage comparison by low-order comparators. First switches SW11A, SW12A, and SW13A and second switches SW11B, SW12B, and SW13B are arranged between reference voltage terminals (REF) of high-order comparators COMP 11, 12, and 13 and voltage-divided terminals (N1), (N2), and (N3) of ladder-resistance-element array, respectively. Voltage holding capacitance elements C11, C12, and C13 are connected to connection points between the first switches SW11A, SW12A, and SW13A and the second switches SW11B, SW12B, and SW13B. When input voltage VAIN is fetched, the first switches SW11A, SW12A, and SW13A are turned on so as to fetch high-order reference voltage VN1, VN2, and VN3 to the voltage holding capacitance elements C11, C12, and C13.

Abstract: An apparatus comprising a reference generation circuit and a modulator. The reference generation circuit, may be configured to generate a first one or more reference voltages and a second one or more reference voltages. The modulator may be configured to present an output signal in response to an input signal, the first reference voltages and the second reference voltages. A gain between the output signal and the input signal may be set by a capacitor ratio in said modulator.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A machine used for analog-to-digital (A/D) conversion in which an analog input is compared to a piece-wise non-linear analog reference waveform. A digital count is recorded indicative of when the difference between the two becomes zero. Alternative mappings such a linear correspondence between analog input values and digital output values can be implemented via digital processing of each recorded count. The invention is particularly intended for use with sinusoidal reference waveforms to enable low-cost, high-precision A/D conversion at speeds much higher than are possible with piece-wise linear analog reference waveforms such as saw-tooth or triangle waveforms. The invention can be implemented with multiple A/D converters sharing a piece-wise non-linear analog reference waveform, with conversion cycles using increasing or decreasing waveform segments, and with compensation of comparator-induced errors.

Abstract: A flash analog to digital converter includes a reference ladder, consisting primarily of resistors, a plurality of comparators, each coupled to a different reference voltage on the reference ladder (the comparators compare a received voltage with a reference voltage level developed across corresponding resistor or group of resistors), and a variable power source coupled to the reference ladder for varying the reference levels generated from the ladder. The structure includes a fixed (or variable) gain driver supplying the received signal voltage to the bank of comparators. The variable power source can be an adjustable current source or an adjustable voltage source. The comparators can be single-ended comparators or differential comparators.

Abstract: A machine used for multi-stage analog-to-digital (A/D) conversion accepts as a stage input an unknown analog input signal and produces as a stage output a residue signal which is negatively scaled with respect to the unknown analog input signal. Combination of the unknown analog input signal and adjustment signals and scaling are accomplished using a circuit requiring only a single op-amp and corresponding output settling delay. The negatively scaled residue signal is passed as input to the following stage. The effects of negative scaling are compensated for in the following stage with proper connection of desired pre-generated reference signals to the second stage's comparators. The invention has a much lower implementation cost than full flash A/D conversion, particularly for high-precision conversions. The invention is also faster than successive approximation (SA) A/D conversion. With proper design, the implementation cost of the present invention can be less than that of prior art SA A/D converters.

Abstract: Method and apparatus for equalizing the digital performance of multiple ADCs includes structure and/or steps for coupling at least one global line between the ADC's resistor ladders to allow current to flow therebetween to balance the reference voltages applied to the comparators of the ADCs. Preferably, the reference voltages are applied equally between the resistor ladders. Even more preferably, the ADC's comparators are located close to each other on a monolithic CMOS circuit.

Abstract: An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to output a held signal, a buffer circuit to buffer the held signal to output a buffered signal, and a comparator circuit to compare the buffered signal with a reference voltage.

Abstract: LVDS drivers and analog-to-digital (ADC) systems are provided which facilitate easy alteration (e.g., replacement of a selectable resistor Rsel) of differential current levels and differential voltages in response to altered loads. These drivers and systems maintain common-mode levels in the loads which are unaffected by alterations in the loads and their associated differential current and voltage levels.

Abstract: An electronic circuit that converts an analog input to a digital signal includes a series “string” of resistors that provides reference signals with ascending values across the string. The reference signals are organized in banks of reference signals, with each adjacent set sharing a major code boundary. A coarse bank of comparators compare the analog input to the major code boundary reference signals and provide a coarse logic output. Each bank of reference signals has a corresponding bank of switches, with each switch associated with a particular reference signal in the bank. All of the switches in a particular bank are closed or opened in unison when selected. A particular bank is selected based on the coarse logic output signal. The reference values corresponding to the selected bank are coupled to a fine bank of comparators, each fine bank comparator comparing the analog input signal to one of the selected reference values.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: An electronic trip device including an analog measuring for measuring electrical signals, analog-to-digital conversion having an input connected to the analog measuring an output having a first output signal, a digital processing means connected to the conversion for performing protection functions, and an offset correction. The offset corrections means are connected to the output of the conversion, and include high-pass digital filtering for computing an output signal value for each sample signal supplied by the conversion, according to an equation.

Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &psgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &psgr;1 and &psgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &psgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &psgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input s

Abstract: A method and apparatus are provided for calibrating first and second analog-to-digital converters (ADCs). The apparatus applies a test signal to the first and second ADCs. A first correction value is applied to an output of the first ADC to produce a first corrected output. A second correction value is applied to an output of the second ADC to produce a second corrected output. The first and second corrected outputs are then compared to identify a greater one and a lesser one of the first and second corrected outputs. At least one of the first and second correction values are adjusted relative to the other until the first or second corrected output that was identified as the lesser one exceeds the other.

Abstract: The successive comparison analog-to-digital (A-D) converter includes a plurality of capacitors, a plurality of first analog switches, a plurality of second analog switches, a plurality of third analog switches, a voltage comparator, and a state controller. Each of the plurality of capacitors has a capacitance weighted with a prescribed weighting factor. Each of the plurality of first analog switches has an on-state resistance weighted with a prescribed weighting factor. In the successive comparison A-D converter, a first analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor has an on-state resistance weighted with a smaller weighting factor, whereby a time constant for this capacitor can be reduced. As a result, the difference in time constant between the capacitors is reduced. This enables reduction in time required to precharge (sample and hold) an analog input, improving the A-D conversion speed.

Abstract: There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.

Abstract: A method and device automatically convert a plurality of analog input channels using a single analog to digital conversion circuit. The device includes a multiplexer, an analog to digital conversion circuit and a configurable channel controller. The multiplexer has at least two analog input channels. The multiplexer also has control inputs and an output. The analog to digital conversion circuit is coupled to the output of the multiplexer and a clock signal. The analog to digital conversion circuit outputs a conversion value based on a voltage associated with the output of the multiplexer in successive clock cycles. The configurable channel controller outputs a control signal to the control inputs of the multiplexer to automatically select successive ones of the at least two analog input channels for conveying to the analog to digital conversion circuit.

Abstract: An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero.

Abstract: The invention uses basic pipeline/subranging architecture to provide a circuit for analogue to digital conversion comprising: a sample and hold circuit (1); a coarse analogue to digital converter (2); a digital to analogue converter (3); combining logic circuitry; a fine analogue to digital converter (6); and also a voltage to current converter (7; R1); means for subtracting in the current domain, preferably comprising a means for summing at a virtual earth node (9); and means for converting current to voltage (10; R2) at the input to the fine analogue to digital converter (6).

Abstract: An analog to digital converting device has a photo-coupled switching device that is composed of a plurality of input channels, and each input channel is composed of a pair of photo relays, wherein each photo relay is controlled by an A/D converting module to be turned on/off. Since the photo relay has high impedance, the isolation between two adjacent channels is enhanced, and possible damage from an interference voltage that occurs across two adjacent channels is avoided.

Abstract: A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.

Abstract: An analog-to-digital converter with a gamma correction function includes a gamma correction unit for generating a plurality of reference voltages corrected according to a gamma function and a decoding unit for selecting at least one corrected reference voltage in response to an input signal and performing analog-to-digital conversion of the selected reference voltage.

Abstract: An analog-to-digital converter 16 includes first and second analog-to-digital converters 22 and 24 both of which receive an input signal. The first analog-to-digital converter 22 is configured to be centered around a first signal level point while the second analog-to-digital converter 24 is configured to be centered around a second signal level point. A decoder 26 receives inputs from the two analog-to-digital converters 22 and 24 and selects between the first analog-to-digital converter 22 output and the second analog-to-digital converter 24 output.

Abstract: A reference buffer circuit having a first reference voltage circuit to provide a first reference voltage at a first port to sink a first current at the first port; a second reference voltage circuit to provide a second reference voltage at a second port to sink a second current at the second port; and a current source circuit to source a source current at an output port, where the output port is connected to the second port. In one application, the first and second ports are connected to a resistor ladder network of a flash analog-to-digital converter.

Abstract: An analog-to-digital converter including a first module of the type having a series of processor stages, each of the stages performing two conversions of the signal output by the preceding stage, firstly an analog-to-digital conversion and secondly a digital-to-analog conversion, followed by subtracting the signal obtained from the output signal of the preceding stage to provide the analog output signal of the stage. The first module further assembles together the signals digitized by each stage (S1, . . . , Si) so as to provide an assembled digital signal (SN(nT) which represents the input signal (e(nT) of the converter in digital form.

Abstract: An analog-to-digital converter includes a plurality of comparators that each have an output, two analog data inputs coupled to a differential analog data input, and two reference voltage inputs. The two reference voltage inputs are each coupled to a resistor ladder that contains a plurality of resistors coupled in series. Importantly, the two reference voltage inputs of each comparator are positively biased, meaning that the positive reference voltage input is coupled to a point on the resistor ladder at a relatively higher potential than the negative reference voltage input. The outputs of the comparators are coupled to an encoder that encodes signals at the outputs into a digital signal. By positively biasing the differential reference voltage inputs of the comparators in this manner, the differential gain, dynamic voltage range, and voltage symmetry of the comparators are advantageously improved.

Abstract: A transceiver includes a receiver and a transmitter. The receiver includes an analog-to-digital conversion device for converting a received analog signal to digital form, and the transmitter includes a digital-to-analog conversion device for converting a digital signal into analog form for transmission. A selector selects the resolutions of the conversion devices. The resolution of the analog-to-digital conversion device is selected based on a received signal quality, e.g., the signal-to-noise ratio or the signal-to interference ratio. The resolution of the digital-to-analog conversion device is selected based on a crest factor of the transmitted signal, the crest factor depending, e.g., on the modulation format of the signal being transmitted. The higher the crest factor, the higher the resolution selected.

Abstract: A pipeline analog to digital converter that includes a main pipeline including a plurality of analog to digital converter stages and a shadow pipeline for compensating the output of the main pipeline. Each of the analog to digital converter stages in the main pipeline provides a digital output and an analog residue signal. The shadow pipeline includes one or more stages that receive at least one gain error signal from one of the analog to digital converter stages in the main pipeline. The shadow pipeline is configured and arranged to processes the gain error signal to form a compensation signal. The compensation signal is combined with the analog residue signal to provide a compensated residue signal in which the finite error gain has been substantially removed.

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different “bit-layers”, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract: A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

Abstract: A non-uniform analog-to-digital converter (ADC) produces digital output data representing the magnitude of an analog input signal having a non-uniform magnitude probability distribution. The digital output data represents the analog input signal with relatively high resolution for the input signal's more frequently occurring magnitudes and with relatively lower resolution for the input signals less frequently occurring magnitudes.

Abstract: An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.