Abstract: A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1-N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.

Abstract: A signal processing system includes an analog-to-digital delta sigma modulator with a duty cycle modulator and a finite impulse response (FIR) filter in a main loop feedback path of the delta sigma modulator. The duty cycle modulator and FIR filter can provide high performance filtering in the main loop feedback path. To prevent instability in the main loop caused by the duty cycle modulator and FIR filter, the delta sigma modulator also includes a stabilizer loop. Transfer functions of the main loop and the stabilizer loop combine to achieve a target transfer function for the analog-to-digital delta sigma modulator that provides for stable operation of the analog-to-digital delta sigma modulator. In at least one embodiment, the stabilizer loop includes a stabilizer path that provides output data directly to an integrator of the main loop filter.

Abstract: A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

Abstract: A solid-state image sensor includes a pixel array, and an analog to digital converter for converting a voltage signal read from the pixel array from analog to digital form, wherein the analog to digital converter includes a counter counting a first clock signal for a period depending on a voltage value of the voltage signal, and wherein a least significant bit of a count value of the counter is determined based on an exclusive OR of outputs of two 1-bit counters operating at a frequency of the first clock signal.

Abstract: A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.

Abstract: A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1?N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.

Abstract: This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.

Abstract: A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Abstract: An analog front end for a multi-channel signal processor is provided. The analog front end includes a first stage that is operable to receive a plurality of channel inputs. The first stage includes a ping/pong capacitor array corresponding to each of the channel inputs and an operational amplifier that may be coupled successively to each of the ping/pong capacitor arrays.

Abstract: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter.

Abstract: A method of analog-to-digital conversion over n bits of an analog signal, including the steps of: comparing the amplitude of the analog signal with a threshold representing the amplitude of the full-scale analog signal divided by 2k, where k is an integer smaller than n; performing an analog-to-digital conversion of the analog signal over n-k bits to obtain the n-k most significant bits of a binary word over n bits if the result of the comparison step indicates that the amplitude of the input signal is greater than the threshold, and the n-k least significant bits of this binary word otherwise. An analog-to-digital converter and its application to image sensors.

Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

Abstract: The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . .

Abstract: A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a different pair formed of a plurality of sets of cascade-connected transistors, and has a first switch for short-circuiting respective cascade connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair.

Abstract: Disclosed are a circuit and a method for an analog-to-digital conversion with programmable resolution. The circuit includes a resistor ladder comprising a plurality of resistors coupled to a plurality of comparators; wherein the resistor ladder is further coupled to a switch logic circuit and a plurality of current sources; and wherein the switch logic circuit is configured to control an operation of a plurality of switches to alter conversion resolution of the ADC, and an error correction circuit coupled to the outputs of the plurality of comparators, wherein the ADC is configured to perform a first conversion step and a second conversion step, and wherein the ADC is configured to perform only the first conversion step when programmed for lower conversion accuracy and higher conversion speed.

Abstract: An A/D converter circuit has a first ring delay line and a second ring delay line configured to vary respective characteristics in the same manner relative to a change in the ambient temperature. A reference voltage, which is free from a change in temperature, is fed as a power supply voltage to the second ring delay line. Digital data produced by the first ring delay line is temperature-compensated by digital data produced by the second ring delay line.

Abstract: Disclosed herein is a data processing method wherein an analog processing object signal is compared with a reference signal and used to convert the processing object signal into digital data and a counting process is carried out and then a count value at a point of time at which the counting process is completed is retailed to acquire digital data of N bits of the processing object signal, including the steps of: carrying out counting operations using the first and second count clocks, whose frequencies are different by an amount corresponding to a weight of the bits from each other, independently of each other; and compensating for an excess or deficiency of data of the higher order N-M bits counted using the second count clock with respect to the count value counted using the first count clock within the counting operation enabled period.

Abstract: A method of digitizing an analog quantity from an electromagnetic radiation detector including a matrix of juxtaposed elementary sensors, including, for each line or column of the matrix, the steps of: integrating the analog quantity using an integrator stage; converting the integrated analog quantity to a first numerical value via a binary counter and a memory element connected to the output of a comparator stage; converting the first numerical value to an analog signal via an analog-to-digital converter; subtracting the analog signal from the analog quantity to be digitized; amplifying the signal resulting from the subtraction with a gain representing the first numerical value; integrating to produce a second numerical value proportional to the analog signal thereby amplified and forming a second binary number representing the least significant bits; and adding said first and second numerical values to form a number representative of the analog quantity to be integrated.

Abstract: Various different approaches are provided for conversion of analog signals to digital signals. For example, various partially clocked, multi-step analog to digital converters are discussed. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range. The clock circuit selectably asserts one of the first clock and the second clock based at least in part on an output of the second conversion stage.

Abstract: In one aspect, provided is an A/D converter including: a plurality of capacitor networks each including a first switch group a capacitor group; a second switch group; and a plurality of reference voltage selectors; a sampling unit grounded at one end thereof; a plurality of A/D converters; and converting means; and a plurality of switch networks each of which connects a corresponding one of the plurality of the capacitor networks to any one of the sampling unit and the plurality of A/D converters in one-to-one correspondence, and in which converter the switch networks change the connections between the plurality of capacitor networks, the sampling unit and the plurality of A/D converters, at each predetermined time intervals, so that a pipeline operation is performed.

Abstract: A method and apparatus are provided for sigma-delta (??) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least One low-order bit.

Abstract: There is provided an A/D converter that outputs a digital output signal obtained by digitalizing an analog input signal. The A/D converter includes a bit selecting section that selects a conversion object bit from a high-order bit to a low-order bit of the digital output signal in order, a threshold-value controlling section that determines a threshold data expressing a boundary value between zero and one of the conversion object bit, a D/A converting section that digital-to-analog converts the threshold data and generates an analog threshold value, a comparing section that compares, at a plurality of different timings in a conversion time interval determining a value of the conversion object bit, the analog input signal and the analog threshold value and outputs a plurality of comparison results at the timings, and a bit determining section that determines the value of the conversion object bit.

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Abstract: An A/D converter compares one or more analog voltages to be converted with a reference voltage given by a voltage change value of ramp voltage whose voltage value changes monotonically for a certain period or a voltage proportional to the voltage change value, converts each analog voltage to a digital value corresponding to the reference voltage, and outputs it, the A/D converter comprising an arithmetic unit for comparison between the analog voltage and reference voltage with respect to each analog voltage, the arithmetic unit having a first power supply line for receiving a power supply voltage, wherein the first power supply line is provided as another power supply line not affected by voltage fluctuation of a second power supply line for supplying a system power supply voltage by providing a MOS transistor whose gate terminal is connected to a stabilized voltage source between the first and second power supply lines.

Abstract: A solid-state imaging device includes: pixel circuits arranged in a matrix which perform photoelectric conversion on received light; and an AD conversion unit converting the resultant signal voltage of the photoelectric conversion. The AD conversion unit includes: a reference voltage generation unit generating plural reference voltages which are different from each other within a possible range for a signal voltage; a most significant bit conversion unit that identifies a voltage section including the signal voltage from among the voltage sections each having a corresponding one of the reference voltages as a base point and determines the identified result as the value of the most significant bit of the digital signal; and a least significant bit conversion unit that converts, into the least significant bit of the digital signal, the difference voltage between the signal voltage and the reference voltage as the base point of the identified voltage section.

Abstract: A digitizer for a digital receiver system includes an input terminal to receive a modulated analog input voltage signal, and an output terminal to provide an output voltage signal being a digital conversion of the input voltage signal. A comparator circuit has an output coupled to the output terminal and includes an operational amplifier having a first input terminal coupled to the input terminal. A threshold generator circuit is between the input terminal and a second input terminal of the at least one operational amplifier, to provide a tunable voltage reference signal thereto. The threshold generator circuit includes a thresholding circuit to determine a threshold voltage value of the modulated analog input voltage signal, and a tunable voltage reference circuit coupled to the thresholding circuit to generate the tunable voltage reference signal as a function of the threshold voltage value of the modulated analog input voltage signal.

Abstract: An analog-digital (A-D) converter for outputting a digital signal corresponding to an analog input signal includes: an upper bit A-D converting section for conducting A-D conversion of the analog input signal and outputting an upper bit portion of the digital signal; a lower bit A-D converting section for conducting A-D conversion of the analog input signal and outputting a lower bit portion of the digital signal; and a majority circuit for sampling an A-D conversion result of the lower bit A-D converting section a plurality of times and determining a value of each of the lower bits by majority operation.

Abstract: A successive approximation analog/digital converter is provided, which includes a successive approximation register supplying a digital/analog converter, first means of comparing an input signal of the analog/digital converter to an output signal of the digital/analog converter delivering a first comparison signal, said successive approximation analog/digital converter being synchronised by a clock signal coming from a conversion clock. A method such as this includes dynamic adaptation of the conversion clock period based on at least one parameter.

Abstract: An electronic circuit includes a transmission circuit transmitting an input signal of a first node as an output signal of a second node in response to a control signal and a discharge circuit selectively discharging the input signal of the first node in response to the control signal.

Abstract: Various different approaches are provided for conversion of analog signals to digital signals. For example, various analog to digital converter circuits capable of converting an input voltage to a digital representation thereof are discussed. Such analog to digital converter circuits include at least a first comparator and a second comparator. An input of the first comparator is electrically coupled to a first storage device, and another input of the first comparator is electrically coupled to the input voltage. An input of the second comparator is electrically coupled to a second storage device, and another input of the second comparator is electrically coupled to the input voltage. The analog to digital converter circuits further include a reference voltage generation circuit that provides the first reference voltage to the first storage device, and subsequently provides the second reference voltage to the second storage device.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide partially clocked, multi-step analog to digital converters. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range.

Abstract: The present invention provides a solid-state imaging device including: a pixel array block; a row scanning device; and an analogue-digital conversion device, the analogue-digital conversion device including: a comparing device having a reset device; a counting device that counts a comparison period from initiation to completion of comparison performed by the comparing device; and a changing device that changes a voltage at the other input terminal to a predetermined voltage after a resetting operation performed by the reset device.

Abstract: An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m?1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N?m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract: An analog-to-digital conversion method includes the steps of outputting an upper-bit conversion reference signal, obtaining a digital value of upper bits on the basis of a period of time from a set time to the time when a magnitude relation between the analog signal and the upper-bit conversion reference signal is determined to be changed, generating and outputting a lower-bit conversion reference signal, obtaining a digital value of lower bits on the basis of a period of time from a set time to the time when a magnitude relation between the analog signal and the lower-bit conversion reference signal is determined to be changed, and determining a digital value of digital data converted from the analog signal on the basis of the digital value of the upper bits and the digital value of the lower bits.

Abstract: The present invention discloses a time-interleaved analog-to-digital converter (ADC), which includes a first and a second sub-ADC and a calibration module. The calibration module includes a switch module and a calibration engine. The switch module selectively provides one of a set of reference voltage levels, which are provided by a resistor series of the first sub-ADC, onto an input signal line, which is shared by the first and the second sub-ADCs. The calibration engine calibrates pre-amplifying units of the first and the second sub-ADCs according to digital signals generated by the first and the second sub-ADCs.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals.

Abstract: Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n?m?2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier.

Abstract: A coder-decoder simultaneously processing a plurality of first analog signals with only one analog-to-digital converter is provided. In an exemplary embodiment, the coder-decoder comprises a multiple access modulator, the analog-to-digital converter, and a multiple access demodulator. The multiple access modulator combines the first analog signals according to a multiple access algorithm to obtain a first multiple access signal comprising the first analog signals. The analog-to-digital converter then converts the first multiple access signal from analog to digital to obtain a second multiple access signal. The multiple access demodulator then separates the second multiple access signal according to the multiple access algorithm to obtain a plurality of first digital signals respectively corresponding to the first analog signals.

Abstract: Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.

Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

Abstract: A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Abstract: An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.

Abstract: Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.

Abstract: In an analog-to-digital converter, an analog-to-digital conversion stage comprising a comparator and an analog residual signal generator. The comparator is operable to compare an analog input signal or a sample of the analog input signal with a threshold to generate a bit signal. The analog residual signal generator is operable to generate an analog residual signal from signals comprising the sample of the analog input signal and the bit signal such that, at a level of the analog input signal equal to the threshold of the comparator, the analog residual signal has a level independent of the state of the bit signal. The analog residual signal generator comprises a summing element, a selective inverter and an amplifier in series. The summing element is operable to sum a signal input to it with a reference signal.