Abstract: The present invention provides a widely general-purpose A/D converting device. The A/D converting device comprises multiple signal conversion units each of which include: an A/D converter for converting an input analog signal into a digital signal with a predetermined number of bits; a D/A converter for converting the output from the A/D converter into an analog signal; a subtracter for subtracting the output signal from the D/A converter, from the input analog signal; and an amplifier for amplifying the output signal from the subtracter. The A/D converting device has a configuration wherein the signal conversion units are arrayed in multiple rows and columns. This allows the user to realize an A/D converting device having various types and levels of performance by making various combinations of the signal conversion units without change of the layout of the signal conversion units.

Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Abstract: A disclosed semiconductor integrated circuit device includes a digital circuit and an analog circuit formed on one semiconductor substrate; a guard band configured to prevent noise generated in the digital circuit from being transmitted to the analog circuit; a first power supply terminal configured to supply a power-supply voltage to the analog circuit; a first ground terminal configured to supply a ground potential to the analog circuit; a second power supply terminal configured to supply the power-supply voltage to the digital circuit; a second ground terminal configured to supply the ground potential to the digital circuit; and a filter circuit positioned between the second power supply terminal, the second ground terminal, and the digital circuit and configured to remove the noise transmitted from the digital circuit.

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: Systems and techniques for converting an analog input signal to a digital code are described. A system includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.

Abstract: A voltage subtracting circuit includes a conversion circuit, a holding circuit, and a differential voltage generator. The conversion circuit converts a first voltage input during a first period into a first current proportional to the first voltage. The conversion circuit further converts a second voltage input during a second period following the first period into a second current proportional to the second voltage. The holding circuit holds the first current during the first period as a third voltage. The holding circuit further outputs the first current during the second period on the basis of the third voltage. The differential voltage generator outputs a differential voltage between the second voltage and the first voltage during the second period on the basis of the second current output by the conversion circuit and the first current output by the holding circuit.

Abstract: A column analog-to-digital conversion apparatus includes a first correlated double sampling (CDS) and comparison unit of a CDS and comparison circuit for generating a first comparison result signal in response to a first pixel output signal and a ramp signal, a second CDS and comparison unit of the CDS and comparison circuit for generating a second comparison result signal in response to the first pixel output signal and the ramp signal in a sub-sampling mode, and a data buffer for determining a code value of a most significant bit (MSB) based on the second comparison result signal, determining code values of remaining lower bits based on a counting value outputted from a counter, and generating a digital code including the MSB and the remaining lower bits.

Abstract: In a conventional CMOS image sensor, an A/D converter for performing A/D conversion at high-speed arranges the A/D converter elements in columns so as to operate in parallel, and has low resolution in the order of 9 or so bits. The present invention provides an A/D converter for an image sensor, which performs a part of the A/D conversion functions by using a noise cancellation circuit in columns and performs amplification simultaneously with this, thereby obtaining a high signal noise ratio (SNR) and implementing an A/D converter with a high resolution along with the A/D conversion section in a subsequent stage.

Abstract: A first amplifier circuit samples an input analog signal and holds the sampled signal for a predetermined period of time. A first analog-to-digital converter circuit samples the input analog signal and converts the sampled signal into a digital value of a predetermined number of bits. A first digital-to-analog converter circuit converts an output signal from the first analog-to-digital converter circuit into an analog signal.

Abstract: A system (10) and method that generate bit-streams that result in higher compression gains. The system is akin to a normal 1-bit SDM. Internally, the system (10) tries to find the best possible bit sequence by tracing N possible solutions at every time instant. In an implementation, the system has N>I trellis path structures (20). Every path is used to track a possible output bitstream. The quality of a bitstream is determined by measuring the (frequency weighted) difference between input and output; it is this measure that is reduced or minimized.

Abstract: Multi-step sub-ranging analog-to-digital converters (ADCs) utilize a plurality of converter modules to generate sub-ranges of bits for a digital output signal during a multi-phase conversion cycle. Each subsequent converter utilizes reference voltage levels corresponding to conversions performed by prior converters during the timing phases of the conversion cycle. Settling time for these reference voltages, which limits the speed and/or accuracy of each conversion, may be reduced by pre-charging the reference input nodes of the subsequent converters using the analog input signal during a timing phase in which a prior converter is converting the analog input signal to generate one of the sub-ranges for the digital output signal.

Abstract: A pipelined analog to digital converter (ADC) that is arranged to dynamically adapt its resolution and sampling frequency based on at least a determined mode of communication and the strength of a received wireless signal. Since standby mode data is typically communicated with a relatively low number of bits (low resolution), the ADC provides for disabling at least a portion of its pipelined stages that provide the higher resolution bits if the standby communication mode is detected. By lowering the ADC's resolution for standby mode communication, it can conserve a considerable amount of power associated with the operation of the higher resolution bits. Similarly, relatively high resolution communication such as receiving and transmitting data and/or voice is process by the ADC by enabling sufficient pipelined stages to provide a higher number of bits.

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract: A current supply circuit supplies a bias current to operational amplifiers which constitute a pipelined AD converter. A current switching circuit switches between output currents in response to a current control signal from current control means, thereby switching between currents to be supplied from a bias circuit to the operational amplifiers via transistors. A sufficiently large current enough for the amplifiers to operate at a high frequency is supplied, while the current is switched to a lower supply current for the amplifier to operate at lower frequencies.

Abstract: An A/D conversion apparatus for converting an analog signal into a digital signal includes a successive approximation A/D converter receiving the analog signal and outputting high-order data of the digital signal, a flash A/D converter receiving the analog signal and outputting low-order data of the digital signal, and a coupling circuit coupling the high-order data and the low-order data and outputting the digital signal.

Abstract: Techniques for designing high-speed integrated circuits are disclosed. According to one aspect of the present invention, an interpolation circuit is disclosed. A method for designing such an interpolation circuit comprises determining an initial value for all resistors in the interpolation circuit, examining whether outputs from the interpolation circuit are evenly spaced across a predefined range of input signals, and when the outputs are not evenly spaced across a predefined range of input signals, adjusting each of the resistors in reference to the outputs so that the outputs are evenly spaced across a predefined range of input signals.

Abstract: A delta-sigma converter has coarse and fine ADCs, wherein an integrated error signal is coupled to the coarse ADC whose output drives a DAC to create feedback that achieves loop balance. The coarse ADC provides the most significant bits of the result. The integrated error signal is also applied to a fine ADC whose output bits are not incorporated into the feedback, but which are combined with those of the coarse ADC and the combination applied to a filter that averages the hunting that represents loop balance. A DC feed forward circuit shunts the integrator with a replica of the applied input signal to apply it to the coarse ADC through a summer, allowing its output to be just the integrated error signal without including the applied input. If continuous integration is used, an AC feed forward circuit provides a compensatory voltage that is removed from the integrator output (or alternatively, is added to its input) and that corrects for a frequency dependent error.

Abstract: A reference signal generator for generating an output reference signal having a target duty cycle. The reference signal generator comprises a sawtooth generator for receiving an input reference signal having a reference frequency and generating a sawtooth waveform having the reference frequency. Comparison circuitry compares the sawtooth waveform to a reference voltage and generates the output reference signal. The output reference signal is Logic 1 when the sawtooth waveform is greater than the reference voltage and is Logic 0 when the sawtooth waveform is less than the reference voltage. Feedback circuitry determines a duty cycle of the output reference signal by comparing a first time period when the output reference signal is Logic 1 to a second time period when the output reference signal is Logic 0. The feedback circuitry adjusts a value of the reference voltage to cause the output reference signal to achieve the target duty cycle.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: A system-on-a-chip (SOC) in CMOS technology capable to support high voltage applications has been achieved. The single chip system of the present invention comprises high-voltage circuitry, a complete micro-controller system including all timing control, interrupt logic, flash EEPROM program memory, RAM, flash EEPROM data memory and I/O necessary to implement dedicated control functions, and a core and system peripheral bus. A preferred embodiment of the invention is shown driving a DC-motor in a H-bridge configuration, having an AMR-position detection and control. A pulse width modulation (PWM) is applied to high-voltage (30 to 60 Volts or in lower ranges less than 30 Volts) CMOS buffers for steering CMOS-FETs or relays of the motor H-bridge.

Abstract: A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation barrier without requiring a phase locked loop (PLL) based clock recovery procedure. In this way, the lead-time needed by the receiving circuit to recover the data clock signal may be reduced and the polarity (or 180° phase) ambiguities often associated with PLL-based methods may be avoided.

Abstract: A method for slicing a differential input signal formed of first and second analog signals, including: receiving the first and second analog signals; adjusting direct current (DC) levels of the first and second analog signals according to a first voltage; comparing voltage difference between the first and second analog signals to generate an output signal; generating an output voltage according to the output signal; and respectively providing first and second currents applied to the first and second analog signals according to the output voltage.

Abstract: An analog-to-digital conversion arrangement for converting an analog input signal into a digital output signal with a most significant part and a least significant part comprises sample means for sampling the analog input signal, a plurality of coarse resolution analog-to-digital converters for converting the sampled analog input signal into a coarse digital signal representing the most significant part of the digital output signal, whereby the coarse resolution analog-to-digital converters are operated in an interleaved way. The analog-to-digital conversion arrangement further comprises a fine resolution analog-to-digital converter for converting the sampled analog input signal into a fine digital signal representing the least significant part of the digital output signal, based upon the coarse digital signal generated by any of said coarse resolution analog-to-digital converters.

Abstract: An image processing method and analog front end circuit are described. An analog signal is converted to digital form to obtain a digital signal by increasing a conversion resolution value of an analog-to-digital converter module. The digital signal is subsequently amplified to obtain an amplified digital output signal.

Abstract: A current mode A/D converter for reducing current consumption while enhancing resolution. The A/D converter includes a V/I conversion circuit for sampling and converting an input voltage to a current, an I/V conversion circuit for converting the current supplied from the V/I conversion circuit to a comparison voltage, a comparator for comparing the current based on the comparison voltage and a reference current, and an encoder for generating a digital output signal based on the output signal of the comparator.

Abstract: An AD converter includes therein a plurality of amplifier circuits such as first to fourth amplifier circuits. Among the plurality of amplifier circuits an amplifier circuit that requires higher accuracy is placed nearer to a power source. An amplifier circuit that receives the first input of an input analog signal is placed nearest to the power source. That is, the first amplifier circuit in the embodiment is disposed closest to the power source. The amplifier circuit that receives the first input of an input analog signal is disposed closest to the power source compared to the other amplifier circuits. The first amplifier circuit, the second amplifier circuit, the third amplifier circuit and the fourth amplifier circuit in the embodiment are placed in this order of how close to the power source.

Abstract: A circuit for calibrating a coarse channel circuit in a folding analog-to-digital converter circuit. A reference value is input to the coarse channel circuit and an output of the coarse channel circuit is sensed. A parameter of the coarse channel circuit is adjusted until the coarse channel circuit is successfully calibrated.

Abstract: A cyclic AD converter having a conversion processing speed or conversion accuracy designed no higher than necessary. In the AD converter, an input analog signal is held by a sample-and-hold circuit, and converted into a digital value by an AD conversion circuit. A DA conversion circuit converts the digital value output from the AD conversion circuit into an analog value. A subtractor circuit outputs the difference between the analog value output from the AD conversion circuit and the analog value held in the sample-and-hold circuit. An amplifier circuit amplifies the output of the subtractor circuit, and feeds back the resultant to the sample-and-hold circuit and the AD conversion circuit. In the course of this feedback-based cyclic processing, an amplification control circuit changes the gain of the amplifier circuit in accordance with the progress of the circulation.

Abstract: A system and method for programmable high precision quantization of analog variable is provided. A signal conversion circuit includes a digital switch subtractor, an ADC, and a counter/adder. During the ADC's first sampling stage, the digital switch subtractor activates a bypass switch that allows the ADC to sample an original analog input signal and generate a first digital value using the original analog input signal. During the ADC's second sampling stage, the digital switch subtractor configures resistor network switches based upon the first digital value, thereby creating a voltage drop across the resistor network when the original analog input signal is applied. As a result, the digital switch subtractor's output is a modified analog signal, which the ADC samples and generates a second digital value. The counter/adder combines the first digital value and the second digital value to produce a digital output that a computer system processes.

Abstract: A first amplifier circuit amplifies an input signal by a factor of ?. A first AD converter circuit is configured at an LSB voltage of VA and converts an input analog signal into a digital value of arbitrary N1 bits. A first DA converter circuit converts the digital value output from the first AD converter circuit into an analog signal. A subtracter circuit subtracts an output of the first DA converter circuit from an output of the first subtracter circuit. A second amplifier circuit amplifies an output of the subtracter circuit by a factor of ?. A second AD converter is configured at an LSB voltage of VB and converts an input analog signal into a digital value of arbitrary N2 bits. In this circuit, the relation VA*?*?=VB*2N2 holds.

Abstract: An analog-to-digital converter has one or more first stage comparators for generating a set of first stage comparator digital outputs, and a set of first stage comparator analog outputs upon comparing a voltage input with a set of voltage references, a switch network for selectively controlling the first stage comparator analog outputs to pass, a ratio capacitor network shared by the first stage comparators for receiving the first stage comparator analog outputs and providing a second set of intermediate analog outputs for identifying a level of the voltage input among a set of intermediate voltage levels between two voltage references, a number of second stage comparators for outputting the number of second stage comparator digital outputs, and a decoder subsystem for receiving the second stage comparator digital outputs to produce a bits of least significant bits. The ratio capacitor network is shared by more than two first stage comparators.

Abstract: An analog-to-digital (A/D) converting device according to the idea of the vernier caliper is provided. First, an analog signal is input into a primary A/D converting circuit to obtain a most significant bits (MSBs) of the digital signal. Then, the MSBs are input into a secondary A/D converting circuit to obtain a least significant bits (LSBs) of digital signal. Finally, the digital signal is obtained by merging the MSBs with the LSBs. Compared with the conventional flash A/D converting device, the present invention significantly reduces the quantity of the required components (for example, the amount of resistors and comparators), such that cost and power consumption are reduced. Compared with the conventional two-step A/D converting device, the present invention effectively eliminates the loading effect and provides a faster speed of signal conversion.

Abstract: An A/D converter 11 is provided with analog input terminals 12, input terminal selection circuit 13, preset registers 15, preset data registers 16, preset data selection circuit 17, and sampling capacitor C. Input terminal selection circuit 13 selects one of analog input terminals 12. Preset registers 15 are correspondingly provided for analog input terminals 12. Preset data selection circuit 17 selects preset digital data which preset data registers 16 stores. Preset data stored at preset registers 15 corresponding to input terminals 12 designated by input terminal selection circuit 13 are converted into analog signals as pre-charge voltages. One of the preset data is selected for each analog input terminal 12 in response to kinds of the input voltages. It is supplied to sampling capacitor C as a pre-charge voltage for a sampling duration of a sampling period for the A/D conversion.

Abstract: A method and apparatus for sampling an analog input signal and storing digital values in a memory, wherein a sequence of clock pulses is generated at a predetermined frequency and a pseudo-random integer is generated at every sampling pulse. The sequence of clock pulses is divided by the integer to select one last pulse from every series of clock pulses. A sequence of sampling pulses is formed by generating a second pseudo-random integer and delaying the selected clock pulse. An analog input signal at the delayed clock pulse is sampled and converted to a predetermined digital format. The current signal sample value is stored in a memory.

Abstract: A differential amplifier device is disclosed wherein the device comprises a differential amplifier circuit, a load circuit connected to the differential amplifier circuit; and a change-over switch connected to the load circuit for changing a gain of the differential amplifier circuit by switching between a full load where a whole of the load circuit is set to be the load of the differential amplifier circuit and a partial load where a part of the load circuit is set to be the load of the differential amplifier circuit, wherein the load circuit is configured to amplify an input signal and an output signal of the differential amplifier circuit in the full load.

Abstract: An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. Reducing power consumption of a SAR system can be readily accomplished by reducing comparator supply voltage. For a SAR converter architecture using a CAPDAC array or CAPDAC (capacitor array DAC), fairly large variations in comparator input voltage can be expected under these circumstances.

Abstract: A current steering folding circuit is provided. The current steering folding circuit includes a load and at least one current source for drawing a current from the load. The current steering folding circuit also includes a first output signal terminal for providing a first output signal, and a second output signal terminal for providing a second output signal. A current steering section is also provided. The current steering section steers the current between the first output signal terminal and the second output signal terminal based on an input signal. The first output signal is substantially equal to the second output signal for N values of the input signal. Advantageously, the number of current sources does not exceed N.

Abstract: Devices for performing analog-to-digital conversion with reduced noise. In one implementation, an analog-to-digital converter includes at least one internal digital-to-analog converter (DAC) that comprises a plurality of analog components and converts an intermediate digital signal into an associated intermediate analog signal, a dynamic element matching (DEM) circuit coupled to the DAC to permute configurations of the analog components within the DAC, a noise cancellation circuit and a digital subtractor block. The noise cancellation circuit is coupled to receive a first digital sequence comprising a component of a digitized representation of an analog output of the DAC, and a second digital sequence representing a state of the DEM circuitry. The noise cancellation circuit is operable to combine the first and the second digital sequences so as to estimate a digital representation of a DAC noise caused by error sequence introduced mismatches among the analog components within the DAC.

Abstract: A need exists to provide an AD converter which is well balanced between an increase in processing speed and a decrease in circuit area. The AD converter performs an analog-to-digital conversion separately in four steps, while performing pipelined processing on an AD conversion of the first stage by a first AD conversion circuit and AD conversions of the second to fourth steps by a second AD conversion circuit. A DA conversion circuit, a subtractor circuit, and an amplifier circuit are utilized in a DA conversion, subtraction, and amplification in the first step as well as in DA conversions, subtractions, and amplifications in the second to fourth steps, thus shared in all the steps.

Abstract: A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.

Abstract: An error correction circuit and a folding ADC are provided. In the folding ADC, the range of the input voltage to an upper ADC circuit and to a lower ADC circuit is shifted by a predetermined voltage toward higher and lower electric potential sides. The error correction circuit outputs the conversion result of the upper bits as is, or corrects the conversion result of the upper bits by either subtracting or adding 1 from or to the conversion result of the upper bits in accordance with the least significant bit within the conversion result of the upper bits and in accordance with the polarity of a code having different polarities between a period in which the voltage level of one folding signal among a plurality of folding signals output from the folding circuit is higher than the center level and a period in which the voltage level is lower.

Abstract: An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.

Abstract: A method for determining analog error of a signal includes receiving an input signal and sampling the input signal to generate a first sampled signal. The method also includes communicating the first sampled signal using a first communication path and a second communication path and sampling the first sampled signal from the first communication path to generate a second sampled signal. The method further includes converting the first sampled signal from the second communication path into a digital signal, storing the digital signal using a digital memory, comparing the second sampled signal to the digital signal, and determining an analog error of the input signal based on the comparison.

Abstract: An AD converter which uses no buffer for receiving the input signals or uses the buffer having relaxed requirements concerning the range of input signals and the output impedance. Voltage at the connection points of a resistor ladder in which a plurality of resistor elements are connected in series, are compared with a reference voltage by a plurality of voltage comparators, a first current circuit is provided on the high potential side of the resistor ladder, a second current circuit is provided on the low potential side thereof, and analog input voltages are fed by providing an input terminal at any place of the resistor ladder except both ends thereof.

Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.

Abstract: An improved segmented digital to analog converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract: Provided is a pipelined folding analog-digital converter, the pipelined folding analog-digital converter comprising: a first sample-and-hold unit that samples and outputs a number of analog input voltages; a reference voltage generator that generates a number of reference voltages; a pre-amplifier that amplifies and outputs a number of values subtracting each reference voltage from the outputs of the first sample-and-hold unit, wherein an offset effect due to asymmetry of the amplifier is eliminated; a first folder that folds and outputs a number of outputs of the pre-amplifier; a second sample-and-hold unit that samples and outputs a number of outputs of the first folder; a second folder that folds and outputs a number of outputs of the second sample-and-hold unit; and a comparator that performs a comparison operation between the outputs of the pre-amplifier and the output values of the second folder to find a digital output value, whereby the offset caused by the device mismatch is removed, so that it is po

Abstract: A current supply circuit supplies a bias current to operational amplifiers which constitute a pipelined AD converter. A current switching circuit switches between output currents in response to a current control signal from current control means, thereby switching between currents to be supplied from a bias circuit to the operational amplifiers via transistors. A sufficiently large current enough for the amplifiers to operate at a high frequency is supplied, while the current is switched to a lower supply current for the amplifier to operate at lower frequencies.