Abstract: A chirp waveform generator for producing a chirp waveform ƒ(t)=sin (t2 modulus m) where modulus m is represented by n submoduli and/or factored submoduli m1-mn. Sequence generators generate digital sequence values representative of sequences of quadratic residues for each submoduli and/or factored submoduli m1-mn. Sine and cosine digital-to-analog converters (DACs) connected to the sequence generators receive the digital sequence values for each submoduli and/or factored submoduli m1-mn and produce sequences of corresponding analog sine and cosine signals. An analog processor including adders and multipliers connected to the DACs combines the sine and cosine signals to produce the chirp waveform. The argument (t2 modulus m) is an implemented phase argument that approximates a desired phase argument (?rt2). Programmable inputs on the sequence generators enable control over waveform parameters including starting phase, ramp rate and frequency.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: A configurable analog to digital converter (ADC) includes a plurality of analog units to integrate an input signal. The analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal and are further coupled to a plurality of bus segments via a plurality of interconnect circuits. Each interconnect circuit is configured to selectively couple the analog units to any of the bus segments.

Abstract: An A-D converter includes a plurality of comparators, each of which compares an analog input signal to analog threshold values; an upper field determination section which, during an upper determination phase, supplies in parallel to each of the plurality of comparators the plurality of analog threshold values expressing boundaries of ranges corresponding to each data value acquired from the upper field of a number of bits previously designated in the digital output signal, detects whether the analog input signal is associated with one of the ranges based on comparison results by the plurality of comparators, and narrows data values of the upper field to data values corresponding to a range between the largest analog threshold value less than or equal to the analog input signal and the smallest analog threshold value greater than or equal to the analog input signal; and a lower field determination section which, during the lower determination phase, determines values of conversion target bits based on a plural

Abstract: An A-D converter that outputs a digital output signal obtained by digitalizing an analog input signal includes a plurality of comparators that each compare the analog input signal and an analog threshold value based on designated digital threshold data, a high-order field determining section that narrows down a data value corresponding to a high-order field of a predetermined bit number in the digital output signal based on a plurality of comparison results obtained by supplying threshold data different from one another to the plurality of comparators, a low-order field computing section that computes a plurality of candidate values for a data value corresponding to a low-order field of a predetermined bit number located at a side lower than the high-order field, and a low-order field determining section that determines a data value corresponding to the low-order field based on the plurality of candidate values.

Abstract: Memory systems include an array of storage cells arranged in a row and column arrangement. A plurality of data write lines coupled to the array are configured to supply data into a selected row of the array. A plurality of data read lines coupled to the array are configured to receive data from a selected column of the array in a single read operation. An arithmetic operation circuit coupled to the plurality of data read lines is configured to generate a result value based on data read from the storage cells of a selected column of the array. Methods of detecting a pattern, such as a color code pattern, are also provided.

Abstract: An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.

Abstract: A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.

Abstract: A pipeline analog-to-digital converter including: a first conversion module, a second conversion module, at least a comparator, a first switch module and a second switch module. The first conversion module includes a first storage unit and a first multiplying digital-to-analog converter (MDAC). An input end of the second conversion module is coupled in series with an output end of the first conversion module. The second conversion module includes a second storage unit and a second MDAC. The first switch module is utilized for coupling the input end of the first conversion module or the second conversion module to an input end of the comparator; and the second switch module is utilized for coupling an output end of the comparator to the first or the second storage unit.

Abstract: A digital to analog waveform converter featuring a DSP, discrete output devices, and Multi Input Multi Output (MIMO) device, wherein the MIMO device includes low accuracy components featuring high speed and low power.

Abstract: A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (?Vbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (?Vbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue?Vref or 2×Vresidue+Vref.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals.

Abstract: Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.

Abstract: A method and a system are disclosed for transmitting an N-bit digital signal at a source. The N-bit digital signal representing a binary value is used to modulate an electrical current by using N discrete voltages representing each bit. The N discrete voltages are coupled to N corresponding switches to control the switches. The switches conduct a corresponding electrical current if the value of the corresponding discrete voltage is the binary value of 1. The currents from each of the closed switches are summed to form a current-encoded data signal in a single physical conductor representing the original N-bit digital signal. The current-encoded data signal is transmitted through the single physical conductor to a current decoder for decoding the current-encoded data signal and extracting the original N-bit digital signal at a destination.

Abstract: A digitizer arrangement for converting an analogue signal into a digital signal, including a first A/D converter, said first A/D converter being arranged to convert said analogue signal into a first digital signal with a first sampling rate, the first sampling rate being lower than the frequency of the analogue signal, a second A/D converter, said second A/D converter being arranged to convert said high frequency analogue signal into a second digital signal with a second sampling rate, the second sampling rate being lower than the frequency of the analogue signal, means for combining said first and second digital signals into a third digital signal with a third sampling rate that is at least a multiple of said first and second sampling rates.

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m?1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N?m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract: Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal to thereby provide fairly good guesses.

Abstract: An A-D converter includes a first amplifier circuit, an A-D converter circuit, a D-A converter circuit, a subtraction circuit, a second amplifier circuit, a timing control circuit, a type control unit, an output unit. The type control unit sets the type of the A-D converter circuit at the time of conversion to the higher 4 bits, to a type in which either one of an analog signal or a reference voltage is inputted selectively to a comparator via a capacitor. The type control unit performs a control so that the type of the A-D converter circuit at the time of conversion to values of the higher 5th to 7th bits and the higher 8th to 10th bits from the most significant bit, to a type in which an analog signal and a reference voltage are inputted fixedly to a comparator without involving a capacitor.

Abstract: A folding and interpolating analog,-to-digital converter (ADC) includes a preamp unit, a first folding stage, a second folding stage, a comparison unit and an encoder. The preamp unit receives an analog input signal and reference voltages to generate reference signals. The first folding stage generates a first group of folding signals based on the reference signals. The second folding stage generates a second group of folding signals based the first group. The comparison unit generates a digital code based on the folding signals in the second group. The encoder encodes the digital code. Therefore, the ADC can increase a resolution and a conversion speed, but reduce interpolating errors.

Abstract: A system includes a continual process for detecting specific data patterns and changes according to a configuration of re-definable and process generated variables. A coarse sample reference, a fine sample reference, and a data array reference are applied to provide independent control over the number of observable signal elements, the level of change that must be observed before detection can occur, and a memory array reference for data probing. A methodology provides near real-time access to specific information portraying the electrical behavior of raw data patterns from signal detector and/or converter circuits independent of a decompression process.

Abstract: An analog-to-digital conversion method includes the steps of outputting an upper-bit conversion reference signal, obtaining a digital value of upper bits on the basis of a period of time from a set time to the time when a magnitude relation between the analog signal and the upper-bit conversion reference signal is determined to be changed, generating and outputting a lower-bit conversion reference signal, obtaining a digital value of lower bits on the basis of a period of time from a set time to the time when a magnitude relation between the analog signal and the lower-bit conversion reference signal is determined to be changed, and determining a digital value of digital data converted from the analog signal on the basis of the digital value of the upper bits and the digital value of the lower bits.

Abstract: A device (10) for use in the verification of handwriting, comprising: a body (12) having a surface (11) over which a writing instrument (8) is moved during the generation of a piece of handwriting; a transducer (14) for transducing stress-wave activity in the body (12) to an analogue time varying signal (15); and digitizing means (22) for converting the analogue time varying signal (15) into a digital signal (27, 31, 11), the digitizing means (22) comprising a sampler (22) arranged to under-sample the analogue time varying signal (15).

Abstract: A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.

Abstract: An analog-to-digital converter (ADC) system is disclosed and includes a programmable control register and a plurality of channels, each channel having an associated request bit within the programmable control register. The ADC system also includes a scheduler responsive to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the request bits are set. A method of scheduling analog-to-digital conversion is disclosed and includes receiving a request to schedule an analog-to-digital conversion for a channel of a plurality of channels. The method also includes scheduling an analog-to-digital conversion in response to receiving the request and performing the analog-to-digital conversion based on the request, where data that indicates the request is stored in a programmable control register.

Abstract: A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.

Abstract: The present invention provides a signal converting apparatus with built-in self test, including a first signal converting circuit, a second signal converting circuit, a comparing apparatus, a control logic apparatus and a voltage divider. The first and the second signal converting circuit take a first and a second reference voltage and are respectively controlled by a first and second set of control signals from the control logic apparatus for the comparing apparatus to generate a comparing result.

Abstract: The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Io and the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The resistor network is supplied by a variable reference voltage originating from a servoloop circuit which locks the voltage level of the middle of the resistor network at a voltage equal to the common mode voltage (VS?VSN)/2 present at the output of the sample-and-hold module.

Abstract: An A-D converter utilizing V-F conversion is realized that is capable of performing A-D conversion with high precision without increasing conversion frequency. Two VCOs are provided to find a V-F conversion value that is less than a period of the main VCO by making use of a period difference between the two VCOs. By counting the number of pulses in a pulse signal that is output from a BASE-VCO with a counter, a high order bit of a digital signal is generated. A low order bit, on the other hand, is generated by calculating, for each sampling period, a phase difference from the beginning of a sampling period until a first pulse generation in the sampling period for the output of the BASE-VCO by a third register and second and third subtracters, based on the number of pulses in the output of the BASE-VCO contained in a period from a current activation time point of sampling signal Ps to a time point at which phases of outputs of the BASE-VCO and JAW-VCO match.

Abstract: There is provided an A-D converter that outputs a digital output signal obtained by digitalizing an analog input signal. The converter includes a plurality of comparators that each compares the analog input signal and an analog threshold value according to designated digital threshold data, a high-order field determining section that narrows down a data value corresponding to a high-order field of a predetermined bit number in the digital output signal based on a plurality of comparison results obtained by supplying threshold data different from one another to the plurality of comparators, a low-order field computing section that computes a plurality of candidate values for a data value corresponding to a low-order field of a predetermined bit number located at a side lower than the high-order field by means of the plurality of comparators, and a low-order field determining section that determines a data value corresponding to the low-order field based on the plurality of candidate values.

Abstract: A method of calibrating an input of a digital-to-analog (D/A) converter based on an output of an analog-to-digital (A/D) converter in an analog encoding apparatus including the D/A converter and the A/D converter, the method including inputting a certain range of input values to the D/A converter while the output of the D/A converter is connected to the input of the A/D converter, thereby producing corresponding output values from the A/D converter; generating a calibration table representing a relationship between input values of the D/A converter and output values of the A/D converter based on the input values in the certain range of input values inputted to the D/A converter and the corresponding output values produced from the A/D converter; and adjusting an input value of the D/A converter based on the calibration table while the output of the D/A converter is disconnected from the input of the A/D converter.

Abstract: An A/D converter has a first voltage generation circuit, a second voltage generation circuit, a comparator, first and second switch circuits connected in series between an input terminal of an analog input voltage and an output terminal of the first voltage generation circuit, a first capacitor inserted between a connection node between the first and second switch circuits and the first input terminal, a second capacitor inserted between an output terminal of the second voltage generation circuit and the second input terminal, a third switch circuit, a fourth switch circuit, an A/D converter which generates a digital signal in accordance with signal level of the first output terminal, and a voltage setting circuit which sets a voltage to be outputted from the first and second voltage generation circuits based on the digital signal.

Abstract: An AD converter includes: a reference voltage generator circuit having a plurality of resistors connected in series with predetermined reference voltage applied to both ends thereof, the reference voltage being divided at connecting points between the individual resistors to generate a plurality of reference voltages; a voltage comparator circuit configured to compare the plurality of reference voltages and analog input signals for conversion into predetermined comparison output signals; and a variable voltage circuit connected to the connecting points of the reference voltage generator circuit and provided with a control signal input terminal inputted with control signals, configured to set an output voltage to be outputted to the connecting points at a predetermined value based on the control signals.

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract: Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n<m<2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.

Abstract: A universal input/output module may be tailored to enable or disable a pull-up or pull-down function such that distinct type digital signals reaching the digital signal processor may be changed such that the distinct digital signals are similar in nature when processed. The digital signal processor is able to enable or disable a pull-down or a pull-up function to provide the ability to universally handle these distinct digital signal types. In other features, a plurality of the modules may be associated with a common power supply, board controller and central communication bus. The input/output modules have applications such as in processing a switch or sensor signal, and outputting a control signal to an associated component.

Abstract: Circuits and methods for detecting the presence of a powered device in a powered network connection and removing power from the powered network connection when no powered device is present are disclosed. The circuits and methods involve applying a time-varying voltage signal into an analog amplifier circuit that converts the voltage into a current indicative of the impedance of the connection. The analog amplifier circuit may be implemented with a dual-output trans-conductance amplifier that provides a digital voltage to indicate the removal of the powered device from the powered network connection.

Abstract: A receiving device includes a receiver; a frequency converter; an A/D converter; and a digital signal processor, wherein the A/D converter includes a variable gain amplifier adjusting a signal level of the analog signal from the frequency converter; an A/D converting portion converting an analog signal from the variable gain amplifier into an m-bit digital signal and an n-bit digital signal and outputting the m-bit digital signal and the n-bit digital signal, the n-bit digital signal serving as an output signal to the digital signal processor; and a gain controller calculating a coarse adjustment gain of the variable gain amplifier on the basis of a power of the m-bit digital signal to control the gain of the variable gain amplifier and calculating a fine adjustment gain on the basis of a power of the n-bit digital signal to control the gain of the variable gain amplifier.

Abstract: A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: A circuit has a first amplifier having first positive and negative inputs and a second amplifier having second positive and negative inputs. A first unit is connectable to the first and second inputs of the amplifiers and a second unit is connectable to the first and second inputs of the amplifiers. In a first phase, the first unit is connected to the amplifiers, wherein the positive input of the first amplifier is coupled to the positive input of the second amplifier and the negative input of the first amplifier is coupled to the negative input of the second amplifier. In a second phase, the second unit is connected to the amplifiers, wherein the positive input of the first amplifier is coupled to the negative input of the second amplifier and the negative input of the first amplifier is coupled to the positive input of the second amplifier.

Abstract: A receiving device includes a receiver; a frequency converter; an A/D converter; and a digital signal processor, wherein the A/D converter includes a variable gain amplifier adjusting a signal level of the analog signal from the frequency converter; an A/D converting portion converting an analog signal from the variable gain amplifier into an m-bit digital signal and an n-bit digital signal and outputting the m-bit digital signal and the n-bit digital signal, the n-bit digital signal serving as an output signal to the digital signal processor; and a gain controller calculating a coarse adjustment gain of the variable gain amplifier on the basis of a power of the m-bit digital signal to control the gain of the variable gain amplifier and calculating a fine adjustment gain on the basis of a power of the n-bit digital signal to control the gain of the variable gain amplifier.

Abstract: Methods and systems for implementing high-performance data converters remove analog technology bottlenecks and provide higher converter resolution and higher speed using lower-performance converters and processing in the frequency domain. The method comprises transforming a time domain input signal into a frequency domain signal in a digital form, processing the frequency domain signal and the input signal using at least two lower-performance data converters in order to obtain at least two processed signals, and recombining the at least two processed signals to obtain a final output signal from the high-performance converter. The processing may include dividing the frequency domain into at least two frequency domain parts, one related to a low-resolution signal to noise ratio (SNR) and the other related to a high-resolution SNR, and using frequency information resulting from the division to obtain the at least two processed signals.

Abstract: Each of plural sigma-delta modulators having a sampling capacitor, an integrator, and a quantizer are connected to each other in parallel. Each of the sigma-delta modulators conducts parallel oversampling in which an analog input signal is sampled by a sampling capacitor, and the sampling result is quantized by the integrator and the quantizer. Then, the quantized values of the sigma-delta modulators are added to obtain MSBs, the residue values of the integrators after quantizing in the respective sigma-delta modulators are added, and the addition result of the residue values is converted analog-to-digital to obtain LSBs.

Abstract: Knob-type operator provided on an operation section is provided with a switch mechanism that switches between ON and OFF states in response to depressing operation of the operator along the rotation axis of the operator. Operator operation detection circuit outputs, to a CPU, a rotated amount and direction corresponding to rotating operation of the operator. The rotated amount corresponding to rotating operation of the operator is converted into a variation amount of a setting of a parameter to be controlled. Resolution with which to associate the rotated amount with the variation amount can be set to any one of two types of resolution, coarse resolution and fine resolution. The rotated amount is converted into the variation amount in accordance with the currently-set type of resolution, and the parameter setting is changed on the basis of the variation amount.

Abstract: A method for converting an analog input signal into a digital value with successive approximation. A first comparison operation is provided before a first approximation, which subdivides a predefined input voltage interval into five partial intervals according to four reference potentials. During the comparison operation, a partial voltage interval determined is used in the ensuing approximation for the selection of a new reference potential pair to be used. This method enables higher sampling rates. At the same time, the range of the input signal is increased.

Abstract: Disclosed is a serial-to-parallel conversion circuit that detects phase difference between a timing of receiving serial receive data and reconstituting parallel data for each symbol and a timing of outputting the reconstituted parallel data to an inside of an LSI, and outputs the detected phase difference as delay time information.

Abstract: A cross coupled folding circuit comprises a reference voltage circuit to supply m reference voltages, an amplifier circuit to provide control signals, in response to an input signal and to the reference voltages and 2n?I three times cross coupled folding circuits, each of which comprising three differential transistor pairs, said differential transistors pairs being controlled by said control signals and active in a voltage range around a respective one of said reference voltages, with m=3(2??1). In cascade with said 2n?I folding circuits, there are differential transistor pairs in n?1 successive steps 2n?1, 2n—2, 20. To obtain complete folding, switching circuits are provided, cooperating with the transistor pairs in the last 2n?2 steps of the cascade configuration, to supply the respective control signals to those transistors of the respective differential transistor pairs that provide complete folding.

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.