Abstract: Disclosed is a circuit and method for reducing output swing in a sigma delta modulator. The quantizer output swing reduction circuit and method of the present invention advantageously enables the modulator to have a larger input/output swing range without degrading the SNR and SFDR performance. One embodiment of the present invention comprises a conventional sigma-delta modulation circuit (100) and a quantizer swing reduction block (210). The quantizer swing reduction block (210) comprises an input signal Vx (216), a signal processing block (214) with transfer function H3 and another signal processing block (215) with transfer function H2*H3.

Abstract: A pipelined analog-to-digital converter with unequal work timing comprising several transfer circuits and a decoder is provided. Each transfer circuit includes an analog-to-digital sub-converter, a multiply digital-to-analog converter, a subtractor and an amplifier. The operation time of the analog-to-digital sub-converter is in a sampling time and the operation time of the multiply digital-to-analog converter, the subtractor and the amplifier is in an amplifying time. The amplifying time is longer than the sampling time. The decoder receives the digital bit signals produced by the analog-to-digital sub-converter of the transfer circuit to produce digital signals.

Abstract: An analog-to-digital converter includes a sample and hold tree having a first level and at least one additional level. Each level includes one or more sample and hold circuits operable to sample an input voltage and produce a corresponding output voltage. The input voltage sampled by the one or more sample and hold circuits in each additional level represents the output voltage from the one or more sample and hold circuits in a preceding level. The analog-to-digital converter also includes a plurality of comparators. Each comparator is operable to compare the output voltage from one of the sample and hold circuits with one of a plurality of reference voltages. In addition, the analog-to-digital converter includes a state machine operable to receive outputs from the comparators and generate a digital output value.

Abstract: A digitizer having a dual exposure technique is combined with an associated LUT for each exposure. Each LUT may have a transfer function including a logarithmic operator resulting in a digitized image with improved photometric resolution and increased dynamic range. A digitizer utilizing multiple exposures at approximately equal exposure time intervals provides a noise reduction for lower optical density portions of the data medium further contributing to increased dynamic range. Associated methods are also provided.

Abstract: A cell array has a plurality of cell elements integrated in a wafer in a bidimensional cell matrix, wherein each integrated cell element comprises a mismatch between its actual physical property and a nominal property value. The mismatch of each cell element is a function of the distance of the respective cell element to a center of the cell array having a bidimensional mismatch distribution which is circular symmetric. The cell elements are connected in series in a wiring pattern along the circular symmetric mismatch distribution of the cell array to reduce an accumulated mismatch.

Abstract: Encoded data is decoded by a receiver for an analogue input signal that is converted into a digital signal. A detector produces a sequence of data representative of the analogue signal, a decoder for the sequence of data outputs data indicating that a sequence includes an error. An event detector detects an event which substantially alters or destroys the analogue input signal. The decoder outputs data corresponding to the or each sequence resulting from the altered or destroyed analogue input signal indicating that the sequence is incorrect.

Abstract: An improved analog to digital converter is disclosed incorporating a flash converter and a charge-sharing pipelined chain converter. The invention incorporates three important circuits including a novel voltage reference steering circuit, a novel high performance low power comparator circuit and a novel digital calibration for compensation circuit. The low power is accomplished by turning on compare circuits only when comparing (controlled by timing circuits that are common to all comparators) and by a low power RAM that properly aligns the converted data. The converter operates in a pipelined manor and requires multiple sample and hold circuits for the compare circuits. The improved analog to digital converter incorporates test and calibration to compensate for variations experience during operation and manufacture of the improved analog to digital converter.

Abstract: To enhance analog to digital conversion performance by obtaining a digital angle output using a negative feedback system including a resolver within a closed loop. The present invention provides a method of converting an analog signal into a digital signal, including inputting a two-phase sinusoidal signal an R/D conversion portion and converting an input rotational angle (?) into a digital angle output (?), in which the method includes obtaining the digital angle output (?) using a negative feedback control system including the resolver within a closed loop.

Abstract: An A/D converter includes a plurality of comparators, each of which samples an analog input potential during a first period, and compares the analog input potential with a reference potential during a second period, an encoder which encodes comparison results obtained by the comparators, and a control signal supply unit which generates one or more control signals that define the first period and the second period such as to make a duration of the first period different from a duration of the send period, and supplies the one or more control signals to the plurality of comparators.

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.

Abstract: An analog-to-digital converter (ADC) includes a resistor network for generating multiple reference voltages. The resistor network includes multiple resistors connected in series to form a resistor string. A first portion of the resistors between either one of two end nodes and a central node of the string have substantially equal electrical resistances. A second portion of the resistors are refinements of at least part of the first portion resistors and are arranged further from the central node than the resistors of the first portion. Resistances of the second portion resistors are greater than resistances of the first portion resistors. When an electrical potential is applied between the two end nodes, the multiple reference voltages are produced between adjacent resistors. An ADC is also described including first and second capacitor arrays and a comparator. An apparatus and method are disclosed for generating a binary value corresponding to an analog input voltage.

Abstract: A chopper comparator has inverters in input and output stages including NMOS transistors to control connection and disconnection of an inverter circuit of each inverter. During a non-operation period of the chopper comparator, parts of the inverters are disconnected form the ground based on a signal supplied to gates of the NMOS transistors.

Abstract: An operational amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a first stage circuit operate in response to a clock signal. An operation amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a second stage circuit operate in response to a clock signal having a frequency three times as high as that of the first clock signal. An analog signal output from the operational amplifier in the first stage is applied to an input node in the second stage circuit through a switch. An analog signal output from an operational amplifier in the second stage circuit is applied to an input node in the second stage circuit through a switch.

Abstract: Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.

Abstract: The present invention provide an CMOS comparator outputting one bit digital signal after comparing two analog input signals through alternately performing a track mode operation and latch mode operation decided by a clock signal having a constant period, including: a latching unit having the main/sub input terminal; a first switching transistor having the clock signal as a gate input and having one end coupled to main input terminal; a first load transistor diode-connected to the other end of the first switching transistor and a ground end; a second switching transistor having a gate receiving the clock signal as a gate input and one end coupled to the sub input terminal; and a second load transistor diode-connected to the second switching transistor and to the other end of the ground terminal.

Abstract: In a converter which operates in a serial-parallel manner and performs analog-to-digital (A/D) conversion, the number of high bits is made more than half the entire number of bits, with the number of low bits is given by half the entire number of bits, thereby acquiring high-bit and low-bit data. When no match exists between the high-bit data and the low-bit data, the high-bit data can be modified by means of the low-bit data.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Abstract: A first AD converting part of an AD converter converts an input voltage into a digital value of a predetermined number of bits and output the digital value to a digital output circuit and a DA converting part. The DA converting part converts the digital value into an analog value. A subtracting part outputs a difference between the analog value output from the DA converting part and the original input voltage. An amplifying part amplifies the difference output from the subtracting part. An output from the amplifying part is input to the first AD converting part via a feedback path. A subsequent output from the amplifying part is input to the second AD converting part via a branch path so as to produce a digital value of a predetermined number of bits. While the second AD converting part performs conversion, a subsequent input voltage is subjected in parallel to AD conversion by the first AD converting part.

Abstract: In a converter which operates in a serial-parallel manner and performs analog-to-digital (A/D) conversion, the number of high bits is made more than half the entire number of bits, with the number of low bits is given by half the entire number of bits, thereby acquiring high-bit and low-bit data. When no match exists between the high-bit data and the low-bit data, the high-bit data can be modified by means of the low-bit data.

Abstract: This circuit and method provides an analog-to-digital A/D converter with minimal power and minimal integrated circuit area. A circuit and a method for A/D conversion are provided which maintains performance, but which uses fewer comparators than the prior art. This is achieved by a semi-flash analog-to-digital, A/D, converter circuit with minimal comparator count. The design does not use any subtraction or multiplication operation. It utilizes fewer comparators than the prior art semi-flash A/D converters. The prior art designs use 30 comparators for an 8-bit semi-flash A/D converter while this invention uses 8 comparators. This circuit and method does not require any external Sample and Hold, S/H circuits. It is a hybrid between flash A/Ds and successive approximation A/Ds.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal coupled to receive a first reference signal having a number of levels, a second input terminal coupled to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexor coupling the multiple number of analog input signals to a multiple number of corresponding differential pairs. The multiplexor selects one of the multiple number of differential pairs based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an imput voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential imput shifted one tap from the neighboring amplifier, and an encoder that converts outputs the array to an N-bit output.

Abstract: A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

Abstract: An analog-to-digital converter system for sampling an input signal includes at least one offset channel. Each channel includes a differential amplifier with a signal input coupled to the input signal, an offset input for receiving an offset signal and an amplified difference output, an analog-to-digital converter having a signal input coupled to the amplified difference output and having a signal output, and an offset index signal source coupled to the differential amplifier offset input. The system further includes an offset controller having at least one output coupled to a corresponding at least one offset index signal source and at least one input coupled to a corresponding at least one analog-to-digital converter signal output. The system also includes a signal constructor having at least one input coupled to a corresponding at least one analog-to-digital converter signal output and operable to provide a relatively high resolution digital output signal.

Abstract: An A/D converter calibration apparatus of the “skip-and-fill” type includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameter are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds or falls below a predetermined change threshold. A calibration control signal CTRL_SKIP_RT is passed to a calibration control unit (104), which sets the background calibration skip rate to a high value if the measure exceeds the threshold an to a low value if it does not exceed the threshold.

Abstract: Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract: An improved analog to digital converter is disclosed incorporating a flash converter and a charge-sharing pipelined chain converter. The invention incorporates three important circuits including a novel voltage reference steering circuit, a novel high performance low power comparator circuit and a novel digital calibration for compensation circuit. The low power is accomplished by turning on compare circuits only when comparing (controlled by timing circuits that are common to all comparators) and by a low power RAM that properly aligns the converted data. The converter operates in a pipelined manor and requires multiple sample and hold circuits for the compare circuits. The improved analog to digital converter incorporates test and calibration to compensate for variations experience during operation and manufacture of the improved analog to digital converter.

Abstract: An A/D converter includes a calibration apparatus handling occurrences of thermometer code bubbles in an A/D sub-converter in at least one A/D converter stage. The calibration apparatus includes means (30) for detecting two A/D sub-converter comparators causing a bubble, means (32, 34, 36) for increasing the threshold of the bubble causing comparator having the lowest threshold by a first predetermined voltage and means (32, 34, 36) for decreasing the threshold of the bubble causing comparator having the highest threshold by a second predetermined voltage.

Abstract: A successive approximation analog-to-digital converter is used for converting an analog input signal into a corresponding digital output signal. The successive approximation analog-to-digital converter has a successive approximation register for storing a first digital bit stream and a second digital bit stream that are related to the analog input signal, and a digital-to-analog converter for generating a first reference voltage and a second reference voltage according to the first and second digital bit streams. The digital-to-analog converter has a first voltage divider and a second voltage divider. The first voltage divider drives the first reference voltage approaching the analog input signal to establish the first digital bit stream, and the second voltage divider drives the second reference voltage approaching the analog input signal to establish the second digital bit stream. Finally, the first and second digital bit streams are averaged to generate the digital output signal.

Abstract: The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23.

Abstract: Briefly, a stage amplifier comprises a differential amplifier having stages and a switch to connect a first differential output of a stage with a second differential output of the stage at a beginning of a conversion cycle.

Abstract: A sigma-delta analog-to-digital converter includes an integrator and a dither signal generator for generating a digital dither signal, and a plurality of comparators for converting an analog signal received from the integrator into an output digital value. A digital logic unit is in data communication with the digital dither signal and the comparators. The digital logic unit is configured to change the output digital value on the basis of the digital dither signal.

Abstract: A pipeline/subranging architecture is used to provide a circuit for analog to a digital conversion. A course analog to digital converter, a fine analog to digital to converter, combining logic circuitry and a digital to analog converter are used, together with a voltage to current converter and a current to voltage converter. A residual signal is formed as the difference between the input signal and an output signal of the coarse analog to digital conversion, the latter output signal having been converted to analog form by the analog to digital converter. The residual signal is then scaled appropriately and applied to the fine analog to digital converter. A final output signal is based on the output signals of the coarse digital to analog converter and the fine digital to analog converter.

Abstract: A method is provided for analog/digital converting of at least one analog low-frequency signal with an analog/digital converter which can detect only an analog signal with a frequency above a predetermined border frequency value, wherein at least one analog low-frequency signal and at least one analog high-frequency signal are provided. An analog intermediate signal is generated from said analog low-frequency signal(s) and said analog high-frequency signal(s) and is input to the analog/digital converter. The analog intermediate signal is converted into a digital intermediate signal, and a digital low-frequency signal corresponding to said analog low-frequency signal is determined from the digital intermediate signal.

Abstract: A method and apparatus are arranged to provide an early comparison scheme for a pipelined ADC stage with a delay circuit. The pipelined ADC includes an amplifier that is biased by a precision bias circuit. The delay circuit includes inverting stages, where each inverting stage includes one or more current sources. The delay circuit is configured to provide a latch signal in response to a clocking signal for the pipelined ADC stage. The latch signal is utilized by one or more comparators for early evaluation of the output of the pipelined ADC stage. The current sources in the delay circuit may also be biased by the precision bias circuit such that variations in amplifier performance are tracked by variations in the performance of the delay circuit. Process, temperature, and power supply related variations in the timing may be minimized by the biasing arrangement of the amplifiers and the delay circuit.

Abstract: An interpolation circuit for generating interpolation and extrapolation differential voltages to a first and second differential input voltages, comprises a first and second differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal and their respective non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the non-inverted output terminals of the first and second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array.

Abstract: A method and apparatus precondition an analog signal and convert the preconditioned signal into a digital representation. The method includes preconditioning the analog signal, generating a quantity N of reference signals, comparing an amplitude of the preconditioned signal to an amplitude of the reference signals to determine whether the preconditioned signal amplitude is greater than, less than or equal to reference signal amplitudes, and producing a timestamp at a time that the preconditioned signal and reference signal amplitudes are equal. The apparatus includes a preconditioner, a reference signal generator and a quantity N of comparators. A comparator of the quantity N of comparators receives the preconditioned signal from the preconditioner, separately receives a reference signal, and produces a digital signal. The preconditioned signal or the analog signal may be reconstructed from the digital representation.

Abstract: The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data.

Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter (12) provides dynamic element matching. This is accomplished by forcing (24) the comparators (COMP1-COMP7) of the A/D sub-converter to generate a scrambled thermometer code.

Abstract: There is provided an A/D converter circuit capable of high-speed operation without fluctuation of reference voltage due to comparison operation by high-order comparators influencing voltage level of reference voltage of voltage comparison by low-order comparators. First switches SW11A, SW12A, and SW13A and second switches SW11B, SW12B, and SW13B are arranged between reference voltage terminals (REF) of high-order comparators COMP 11, 12, and 13 and voltage-divided terminals (N1), (N2), and (N3) of ladder-resistance-element array, respectively. Voltage holding capacitance elements C11, C12, and C13 are connected to connection points between the first switches SW11A, SW12A, and SW13A and the second switches SW11B, SW12B, and SW13B. When input voltage VAIN is fetched, the first switches SW11A, SW12A, and SW13A are turned on so as to fetch high-order reference voltage VN1, VN2, and VN3 to the voltage holding capacitance elements C11, C12, and C13.

Abstract: Disclosed herein is an analog-to-digital converter having first and second comparator stages, a voltage reference stage, a switching stage, and an encoder. The first comparator stage receives an analog signal and a threshold and outputs a control signal. The voltage reference stage receives the control signal and outputs one of two or more sets of reference voltages. The second comparator stage receives the analog signal, as well as the set of reference voltages output from the voltage reference stage, and outputs a thermometer code in response to comparisons of the analog signal to the reference voltages. The switching stage receives the control signal, and in response thereto, variously couples inputs of the encoder to: bits of the thermometer code output from the second comparator stage, a first potential, or a second potential. Methods for converting analog signals to digital signals are also disclosed.

Abstract: Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract: A sigma delta modulator having an integrator with a first input for coupling to an analog signal and a second input for coupling to a reference voltage. A comparator is provided having a first input coupled to an output of the integrator and a second input for coupling to the reference voltage. The comparator produces signal having a logic state in accordance with the relative magnitude of signals at the first and second inputs thereof. The logic state is latched at the output of such comparator during latching transitions in a series of latching pulses fed to the comparator. A one-bit quantizer is provided for storing the logic state of at the output of the comparator at sampling transitions of a series of clock pulses fed to the one-bit quantizer. The series of clock pulses and the series of latching pulses are synchronized one with the other. Each one of the latching transitions occurs prior to a corresponding one of the sampling transitions.

Abstract: A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout.

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.