Parallel Type Patents (Class 341/159)
  • Patent number: 11316505
    Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rishi Soundararajan, Visvesvaraya Pentakota
  • Patent number: 11265006
    Abstract: In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Peter Bogner, Herwig Wappis
  • Patent number: 11112450
    Abstract: A method and apparatus for controlling a tester, related medium and electronic device are provided. The apparatus includes a vibration data collector attached on a side wall of the tester to collect vibration data from the tester during operation thereof. The method includes: receiving the vibration data collected by the vibration data collector; comparing the vibration data with a predetermined threshold to generate a comparison result; and controlling an operating state of the tester based on the comparison result. This method may timely identify any instability of the tester and prompt for repair if necessary. It substantially reduces the time and material costs associated with a test, and thus reduces the non-chip-attributable defect rate.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: September 7, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Yubin Lu
  • Patent number: 10944415
    Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 9, 2021
    Assignee: Massachusetts Institute of Technology
    Inventor: Robert J. Murphy
  • Patent number: 10914807
    Abstract: A point stick module has a sensing device, a rank unit and a signal processing device. The sensing device outputs multiple sensing signals in response to operations done by a user. The rank unit provides a rank signal to represent a rank of the sensing device. The signal processing device is coupled to the sensing device and the rank unit to receive the multiple sensing signals and the rank signal, wherein the signal processing device selects a parameter according to the rank signal.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 9, 2021
    Assignee: Elan Microelectronics Corporation
    Inventor: Chun-Chieh Huang
  • Patent number: 10911707
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 2, 2021
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Patent number: 10903844
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10897265
    Abstract: An analog-to-digital conversion device of the embodiment includes a comparator and a logic circuit including a switch unit and a logic gate unit that receives a signal output from a comparator. The logic gate unit and the switch unit are connected to each other in series between a power supply node and a ground node.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: January 19, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuhiro Saito, Hideo Kobayashi, Tetsuya Itano
  • Patent number: 10855298
    Abstract: Methods and systems 10 are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: December 1, 2020
    Inventor: Frank R. Dropps
  • Patent number: 10848186
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Vivek Asthana, Jitendra Dasani, Amit Chhabra
  • Patent number: 10809282
    Abstract: A multi-level logic analyzer for analyzing multi-level digital signals comprises a plurality of signal inputs, each signal input being configured to receive a multi-level digital signal, a plurality of comparison units, each comparison unit comprising a first comparator input and a second comparator input and being configured to compare a signal received at the first comparator input with a signal received at the second comparator input, and first switching means configured to couple at least one of the signal inputs with the first comparator inputs of at least two of the comparison units.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 20, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Martin Peschke
  • Patent number: 10673447
    Abstract: An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 2, 2020
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventor: Laurent Vaccariello
  • Patent number: 10638079
    Abstract: An A/D converter includes a reference voltage generating circuit that generates a reference voltage of a ramp waveform in which a voltage value changes with time, a gray code generating circuit that outputs a gray code based on a same reference clock as the reference voltage generating circuit, a comparison circuit that compares the reference voltage with an input voltage, a latch circuit that holds a count value of the gray code based on an output signal of the comparison circuit, a code conversion circuit that serially converts the count value of the gray code held in the latch circuit into a binary code, and a calculation processing circuit that stores a count value of the binary code output from the code conversion circuit, and performs calculation processing based on the stored count value of the binary code and a next input count value of the binary code.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 28, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Yusaku Koyama
  • Patent number: 10601432
    Abstract: Methods and systems are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 24, 2020
    Inventor: Frank R. Dropps
  • Patent number: 10581448
    Abstract: A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity.
    Type: Grant
    Filed: February 3, 2019
    Date of Patent: March 3, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10477132
    Abstract: A successive approximation register (SAR) analog-digital converter (ADC) may include a comparison circuit coupled to an array of pixels arranged in rows and columns to receive a first pixel signal and a second pixel signal from a first column and a second column, respectively, and structured to compare each of the first and second pixel signals with a reference voltage and output comparison signals; an analog-digital conversion mode decision circuit located to receive the comparison signals from the comparison circuit and structure to provide a mode decision value which decides an analog-digital conversion mode out of different analog-digital conversion modes based on the comparison signals from the comparison circuit; and a shared circuit shared by the first and second columns, and structured to generate the reference voltage based on the comparison signals from the comparison circuit and the mode decision value from the analog-digital conversion mode decision circuit, the shared circuit outputting the refer
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyeon-June Kim
  • Patent number: 10284221
    Abstract: A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 7, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Daniel Peter Canniff, Mariana Tosheva Markova, Edward Chapin Guthrie
  • Patent number: 10222429
    Abstract: A diagnostic system for a DC-DC voltage converter is provided. The DC-DC voltage converter has a high voltage bi-directional MOSFET switch. The high voltage bi-directional MOSFET switch has a first node and a second node. The microcontroller samples a first voltage at the first node at a first sampling rate utilizing a first common channel in a first bank of channels to obtain a first predetermined number of voltage samples. The microcontroller determines a first number of voltage samples in the first predetermined number of voltage samples in which the first voltage is less than a first threshold voltage. The microcontroller sets a first voltage diagnostic flag equal to a first fault value if the first number of voltage samples is greater than a first threshold number of voltage samples indicating a voltage out of range low fault condition for the analog-to-digital converter.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 5, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Kerfegar K. Katrak, Mehdi Rexha, Kunal Tipnis
  • Patent number: 10015429
    Abstract: A method of reducing noise in an image sensor using a parallel multi-ramps merged comparator analog-to-digital converter (ADC) starts with a pixel array capturing image data. The pixel array includes pixels to generate pixel data signals, respectively. An ADC circuitry acquires the pixel data signals. The ADC circuitry includes ADC circuits. Each of the ADC circuits includes a comparator and latches. The comparator includes a multi-input first stage. The comparator in each ADC circuit compares one of the pixel data signals to ramp signals received from a logic circuitry to generate comparator output signals. The latches in each ADC circuit latches the counter based on the comparator output signals, respectively, to generate ADC outputs. Other embodiments are described.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 3, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventor: Olivier Bulteel
  • Patent number: 9935644
    Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 3, 2018
    Assignee: MAXLINEAR, INC.
    Inventor: Curtis Ling
  • Patent number: 9865633
    Abstract: A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 9, 2018
    Assignee: Sony Corporation
    Inventors: Keiji Mabuchi, Toshifumi Wakano, Ken Koseki
  • Patent number: 9691164
    Abstract: A method and system for symbol-space based pattern compression. The method includes identifying a plurality of basic image symbols in an input sequence; assigning, to each of the plurality of basic image symbols, at least one connecting port; generating an output sequence by replacing each identified basic image symbol with an identification symbol, wherein the output sequence indicates connections between pairs of the plurality of basic image symbols based on the connecting ports, wherein each identification symbol is not a previously used symbol; and storing the output sequence as a data layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 27, 2017
    Assignee: Cortica, Ltd.
    Inventors: Igal Raichelgauz, Karina Odinaev, Yehoshua Y Zeevi
  • Patent number: 9467160
    Abstract: An ADC is provided. The ADC includes a plurality of pre-amplifiers, dynamic comparators coupled to the pre-amplifiers, interpolators and an encoder. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog signals and a first reference voltage and a second reference voltage different from the first reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier. Each interpolator provides an interpolating signal according to the first and second comparing signals of two of the dynamic comparators. The encoder provides a digital output according to the interpolating signals. The first and second comparing signals are the same in a reset phase, and the first and second comparing signals are complementary according to the pair of differential outputs of the corresponding pre-amplifier in an evaluation phase.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: October 11, 2016
    Assignee: MEDIATEK INC.
    Inventor: Wen-Hua Chang
  • Patent number: 9449719
    Abstract: A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: September 20, 2016
    Assignee: Seagate Technology LLC
    Inventor: Nicholas P. Mati
  • Patent number: 9374050
    Abstract: A differential amplifier may, when connected to a positive or negative supply voltage and to a ground voltage, provide a differential pair of outputs signals at a differential output that are an amplification of a differential pair of input signals at a differential input. A differential input stage may receive the differential pair of input signals from the differential input and may include a first transistor associated with one of the input signals and a second transistor associated with the other input signal. A differential output stage may generate the differential pair of output signals at the differential output and may include a third transistor associated with one of the output signals and a fourth transistor associated with the other output signal. The first, second, third, and fourth transistors may be all P type or all N type.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 21, 2016
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Joseph Adut, John Perry Myers
  • Patent number: 9276597
    Abstract: An analog-to-digital converter is provided. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog input signals and a first reference voltage and a second reference voltage from a resistor chain, wherein the first reference voltage is different from the second reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the pre-amplifier. Each pre-amplifier includes a first calibration unit for calibrating a first offset voltage from the pre-amplifier at the pair of differential outputs at a specific temperature, and a second calibration unit for calibrating a second offset voltage from the corresponding dynamic comparator at the pair of differential outputs.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 1, 2016
    Assignee: MEDIATEK INC.
    Inventor: Wen-Hua Chang
  • Patent number: 9257422
    Abstract: A memory element capable of operating at high speed and reducing power consumption and a signal processing circuit including the memory element are provided. As a writing transistor, a transistor which is formed using an oxide semiconductor and has significantly high off-state resistance is used. In a memory element in which a source of the writing transistor is connected to an input terminal of an inverter, a control terminal of a transfer gate, or the like, the threshold voltage of the writing transistor is lower than a low-level potential. The highest potential of a gate of the writing transistor can be a high-level potential. When the potential of data is the high-level potential, there is no potential difference between a channel and the gate; thus, even when the writing transistor is subsequently turned off, a potential on the source side hardly changes.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yasuhiko Takemura
  • Patent number: 9245650
    Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kei Takahashi, Tatsuya Onuki
  • Patent number: 9214889
    Abstract: There is provided a motor drive control apparatus that includes a resistor, which directly or indirectly detects a driving current supplied to a motor and generates a voltage corresponding to the driving current, converts, with an AD converter, the voltage corresponding to the motor driving current detected by the resistor into a numerical value, and reflects the motor driving current converted into the numerical value on driving control for the motor, wherein a plurality of the resistors is connected in series to form a resistor string, and voltage between arbitrary two points of the resistor string is AD-converted.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: December 15, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuya Sano, Kiyonari Kawajiri, Toshiki Tanaka
  • Patent number: 9191551
    Abstract: Methods and apparatuses for performing lossless normalization of input pixel component values. The apparatus includes a normalization unit for converting pixel values from a range of 0 to (2N?1) to a normalized range from 0.0 to 1.0. The step size between adjacent values of the normalized range is 1/(2N?1), and a maximum input value of (2N?1) corresponds to a normalized value of 1. The normalization unit divides each input pixel component value by (2N?1) in order to preserve the fidelity of the color information contained in the input pixel component value.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 17, 2015
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Nitin Bhargava, Craig M. Okruhlica
  • Patent number: 9118795
    Abstract: Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-jung Kim, U-in Chung, Jai-kwang Shin, Sun-il Kim, I-hun Song, Chang-jung Kim, Sang-hun Jeon
  • Patent number: 9106849
    Abstract: An image sensor includes an analog-to-digital converter receiving a pixel signal output. The converter includes a first inverting amplifier circuit having an input and an output, the first inverting amplifier circuit including a first bias circuit having a control node and configured to source current for first inverting amplifier circuit operation. The converter further includes a second inverting amplifier circuit having an input and an output, the second inverting amplifier circuit including a second bias circuit having a control node and configured to source current for second inverting amplifier circuit operation. The output of the first inverting amplifier circuit is coupled to the input of the second inverting amplifier circuit. A positive feedback circuit couples the output of the second inverting amplifier circuit to the control node of the first bias circuit.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: August 11, 2015
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Amar Duggal, John Kevin Moore
  • Patent number: 9041581
    Abstract: An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: May 26, 2015
    Assignee: CMOSIS BVBA
    Inventor: Bram Wolfs
  • Patent number: 9030341
    Abstract: Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 12, 2015
    Assignee: Broadcom Corporation
    Inventors: Loke Tan, Steven Jaffe, Hong Liu, Lin He, Randall Perlow, Peter Cangiane, Ramon Gomez, Giuseppe Cusmai
  • Publication number: 20150109160
    Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.
    Type: Application
    Filed: April 29, 2014
    Publication date: April 23, 2015
    Applicant: NOVATEK Microelectronics Corp.
    Inventor: Jer-Hao Hsu
  • Patent number: 8981986
    Abstract: Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Broadcom Corporation
    Inventors: Pauli Mikael Seppinen, Markus Nentwig, Sami Seppo Antero Kallioinen, Kim Kaltiokallio
  • Patent number: 8970419
    Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Xilinx, Inc.
    Inventors: Brendan Farley, James Hudner, Ivan Bogue, Declan Carey, Darragh Walsh, Marc Erett
  • Patent number: 8957801
    Abstract: The subject matter discloses a flash analog to digital converter arranged in a tree of signal amendment units, each comprises an amplifier and an offset adder. The output signals of the tree are even partitioned and compared to comparators, to reduce the level of accuracy required from the comparators. The subject matter also discloses a cascade of amplifiers connected in series and operate in delay one relative to the other, each amplifier comprises a reset unit to reset the amplifier responsive to receipt of a signal.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: February 17, 2015
    Inventor: Dan Raphaeli
  • Patent number: 8952836
    Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: February 10, 2015
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Hongwei Zhu, Yuwei Zhao
  • Publication number: 20150015229
    Abstract: A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value.
    Type: Application
    Filed: January 21, 2014
    Publication date: January 15, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Chen Kong Teh
  • Patent number: 8928508
    Abstract: An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Shi Jordan Lai, Kuo-Ming Wang, Hsu-Feng Hsueh, Cheng Yen Weng, Yung-Fu Lin
  • Patent number: 8922414
    Abstract: A method and apparatus for symbol-space based compression of patterns are provided. The method comprises receiving an input sequence, the input sequence being of a first length and comprising a plurality of symbols; extracting all common patterns within the input sequence, wherein a common pattern includes at least two symbols; generating an output sequence responsive of the extraction of all common patterns, wherein the output sequence has a second length that is shorter than the first length; and storing in a memory the output sequence as a data layer, wherein the output sequence is provided as a new input sequence for a subsequent generation of a data layer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 30, 2014
    Assignee: Cortica, Ltd.
    Inventors: Igal Raichelgauz, Karina Ordinaev, Yehoshua Y. Zeevi
  • Patent number: 8917198
    Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The continuous-time quantization-noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: December 23, 2014
    Assignee: Syntropy Systems, LLC
    Inventor: Christopher Pagnanelli
  • Patent number: 8890740
    Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 18, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Masanori Hoshino, Takumi Danjo
  • Patent number: 8890739
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8878712
    Abstract: A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 4, 2014
    Assignee: Analog Devices Technology
    Inventors: John Cullinane, Frederick Carnegie Thompson
  • Patent number: 8878713
    Abstract: A system includes an array of comparators configured to convert an analog input to a digital output, a switch configured to adjust output bits of the digital output, and a control logic; the control logic is configured to initialize the switch and a direct-current source coupled to the analog input; the control logic is configured to increase the direct-current source in incremental steps of a minimal voltage value corresponding to the least significant bit of the digital output; and the control input is also configured to cause the switch to adjust one or more output bits of the digital output based at least in part on a value of the output bit corresponding to the current incremental step.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Pradip Thachile, Magnus O. Wiklund, William Warren Walker
  • Patent number: 8866658
    Abstract: A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Hirai
  • Patent number: 8860591
    Abstract: An ADC which samples an analog input signal at a sampling frequency and converts the analog input signal to a digital output signal, has N analog digital converter (ADC) channels which convert the analog input signal into the digital output signal by time interleaving, a channel synthesizer which synthesizes channel digital signals output respectively by the ADC channels to generate the digital output signal, an adaptive filter provided at at least one output of the ADC channels, and a correction circuit which generates a coefficient of the adaptive filter in accordance with the digital output signal. The correction circuit calculates a DC component of an image signal component, from among an analog input signal component and the image signal component corresponding to error, both being included in the digital output signal, and calculates the coefficient such that the DC component is suppressed on the basis of the DC component.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takeshi Nozaki
  • Patent number: 8860592
    Abstract: A signal generating circuit, may include an analog signal generator having an output and a control input, the analog signal generator configured to generate at the output an analog output signal in accordance with a timing parameter; an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the analog signal generator, the ADC configured to generate a sequence of signal values dependent on the analog signal received at the input; a configurable digital signal generator comprising an output and a control input, the digital signal generator configured to generate a digital output signal in accordance with signal parameters received at the control input; and a control circuit having an input coupled to the output of the ADC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Heinz Mattes, Ralf Arnold, Hermann Obermeir