Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

Abstract: Methods and apparatus to perform audio watermarking and watermark detection and extraction are disclosed. Example apparatus disclosed herein to embed a code into an audio signal include means for selecting frequency components to be used to represent the code, different sets of frequency components to represent respectively different information, respective ones of the frequency components in the sets of frequency components located in respective code bands, there being multiple code bands and spacing between adjacent code bands being equal to or less than the spacing between adjacent frequency components in the code bands. Disclosed example apparatus further include means for synthesizing the frequency components to be used to represent the code and means for combining the synthesized frequency components with an audio block of the audio signal.

Abstract: A linear feedback equalizer includes comparators that digitize incoming analog signals. The equalizer further includes digital-to-analog converters (“DACs”) that transform a current digitized signal into one or more feedback analog signals. The equalizer further includes a subtractor that subtracts the feedback analog signals from the output of a continuous-time linear equalizer (“CTLE”) and provides the difference to the comparators as incoming analog signals.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.

Abstract: A digital low drop-out regulator circuit includes transistor switches that are selectively actuated in response to a comparison of an output voltage at an output node to corresponding tap reference voltages. A dynamic reference voltage correction circuit operates to shift voltage levels of the tap reference voltages in response to a difference between the output voltage at the output node and an input reference voltage.

Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: The invention is in the field of in vitro diagnostics and relates to a method for ascertaining a transmission value for a light signal that is pulsed at a frequency through a specimen in an automatic analysis appliance. It also relates to a transmission measurement apparatus for an automatic analysis appliance, comprising a light source that is pulsed at a frequency and a photodetector having a downstream A/D converter.

Abstract: A neuromorphic system includes: an unsupervised learning hardware device configured to perform learning in an unsupervised manner, the unsupervised learning hardware device performing grouping on input signals; and a supervised learning hardware device configured to perform learning in a supervised manner with labeled values, the supervised learning hardware device performing clustering on input signals.

Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.

Abstract: The present disclosure is directed to a system and method for adjusting a conversion speed of an asynchronous SAR ADC based on a margin of time between when a conversion of a sample of an analog signal completes and a next sample of the analog signal is taken, referred to as a “conversion time margin.” The system and method reduce the conversion speed of an asynchronous SAR ADC when the conversion time margin permits to reduce the amount of power consumed and/or noise produced by the asynchronous SAR ADC.

Abstract: A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder.

Abstract: A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.

Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.

Abstract: Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal.

Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: A time domain switching analog-to-digital converter apparatus and methods of utilizing the same. In one implementation, the converter apparatus comprises a carrier signal source, and at least one reference source. The carrier signal is summed with the input signal and the summed modulated signal is fed to a comparator circuit. The comparator is configured detects crossings of the reference level by the modulated waveform thereby generating trigger events. The time period between consecutive trigger events is used to obtain modulated signal deviation due to the input signal thus enabling input signal measurement. Control of the carrier oscillation amplitude and frequency enables real time adjustment of the converter dynamic range and resolution. The use of additional reference signal levels increases sensor frequency response and accuracy. A dual channel converter apparatus enables estimation and removal of common mode noise, thereby improving signal conversion accuracy.

Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N?1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.

Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract: Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.

Abstract: A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.

Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.

Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.

Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.

Abstract: Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: To provide a semiconductor device including an A/D converter circuit that is capable of performing A/D conversion with high accuracy and high resolution and that can be reduced in size. One loop resistance wiring is shared by a plurality of power supply switches and a plurality of output circuits, and a reference voltage having a triangular (step-like) wave generated using the resistance wiring and the plurality of power supply switches is utilized. Thus, high-accuracy digital signals can be obtained using such an A/D converter circuit that can be reduced in size as an output circuit, without using a complicated circuit structure. Further, the number of constituent elements of the A/D converter circuit is small, whereby in the case of providing A/D converter circuits in parallel, variation between the A/D converter circuits can be made small.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing.

Abstract: Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

Abstract: An analog-to-digital converter including a comparator, a control module, a voltage adjusting module, and an evaluating module is provided. The comparator compares an analog input voltage with a feedback voltage and generates a comparison result. Based on the comparison result, the control module generates a control signal. The voltage adjusting module increases or decreases the feedback voltage toward the analog input voltage according to the control signal. The voltage increase amount and decrease amount provided by the voltage adjusting module are corresponding to a first digital value and a second digital value, respectively. The evaluating module generates the first digital value and the second digital value based on the control signal. According to the first digital value and the second digital value, a digital signal corresponding to the analog input voltage is generated.

Abstract: A thermometer coded line is configured to convert a time interval to a digital code for subsequent processing in order to output a value representative of said time interval. A digital peak detector is coupled to receive output from the thermometer coded line, the detector operating for correction of an undesired code of said digital code in order to ensure a valid output of said value. A majority logic circuit is coupled between the thermometer coded line and the digital peak detector, the logic circuit operating for correction of undesired code of said digital code in order to ensure the valid output of said value. The detector functions to correct any undesired code not corrected by, or introduced by, the logic circuit.

Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A CMOS image sensor converts successive analog signals, representing at least a portion of an image, into successive digital signals using an analog to digital circuit block. Multiple clock cycles may be used by the circuit block to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal by the circuit block may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal by the circuit block.