Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter provides dynamic element matching. This is accomplished by forcing comparators of the A/D sub-converter to generate a scrambled thermometer code.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A majority circuit for reduce a size thereof is provided. The majority circuit is composed of a D/A converter converting a plurality of binary signals to an analogue signal, a majority determining circuit responsive to said analogue signal to achieve a majority operation on said plurality of binary signals to produce a result signal representative of a result of said majority operation.

Abstract: An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

Abstract: The present invention discloses a flash type analog to digital converting method, comprising: (a) receiving an analog signal and generating 128-bit digital thermometer code based on the analog signal; (b) 3rd-compressing the 128-bit thermometer code to generate a 16-bit thermometer code and a 3-bit carry; and (c) encoding the 128-bit thermometer code to generate a 7-bit digital signal. Therefore, a layout area can be reduced because, after a 2n-bit thermometer code is compressed, the compressed digital signal is encoded to generate an n-bit digital signal.

Abstract: Disclosed herein is an analog-to-digital converter having first and second comparator stages, a voltage reference stage, a switching stage, and an encoder. The first comparator stage receives an analog signal and a threshold and outputs a control signal. The voltage reference stage receives the control signal and outputs one of two or more sets of reference voltages. The second comparator stage receives the analog signal, as well as the set of reference voltages output from the voltage reference stage, and outputs a thermometer code in response to comparisons of the analog signal to the reference voltages. The switching stage receives the control signal, and in response thereto, variously couples inputs of the encoder to: bits of the thermometer code output from the second comparator stage, a first potential, or a second potential. Methods for converting analog signals to digital signals are also disclosed.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

Abstract: A binary encoder which has a fast conversion speed, occupies a small area, and consumes a small amount of power is provided. The binary encoder includes first and second latch transistors, first and second charge transistors, first and second control transistors, first and second discharge transistors, and first and second inverters. The first charge transistor charges a first output node to a level of a power voltage in response to a clock signal. The second charge transistor charges a second output node to the level of the power voltage in response to the clock signal. The first discharge transistor discharges a first control node to a level of a ground voltage in response to a first input signal. The second discharge transistor discharges a second control node to the level of the ground voltage in response to a second input signal.

Abstract: An array of transistor circuits is fabricated so that each transistor circuit in an array of transistor circuits has a switching threshold determined by intrinsic switching thresholds of at least one sensing transistor in a corresponding transistor circuit. The sensing transistors in a set of transistor circuits of the array can be fabricated to have common physical dimensions even though corresponding intrinsic switching thresholds of the transistor circuits can vary. Switching thresholds of the transistor circuits can vary based on an applied well bias voltage. Alternatively, the switching threshold of each transistor circuit can be set to a common value and a tapped delay line can be coupled to the transistor circuits. Consequently, an A/D converter device can be fabricated by coupling an encoder, and a calibration circuit if necessary, to the output of the array of transistor circuits.

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Abstract: A positioning system in which a absolute sensor detection signals are communicated to a controller, which is a personal computer, via a PC card. The PC card is provided with sensor connection terminals, a converter for converting sensor detection signals to digital position signals, PC connection terminals, a sensor drive circuit, and a switching circuit. The sensor switching circuit switches sensor connection terminals in accordance with commands from the personal computer, whereby one absolute sensor is excited or driven by the drive circuit, and detection signals from that sensor are converted to digital position signals that are fed to the personal computer. Using a PC card thus configured makes it possible to readily configure a positioning system having a plurality of absolute sensors.

Abstract: Analog input selection circuits comprising an input terminal, an output terminal, a transmission path extending between the input terminal and the output terminal, transmission switches that open or close the transmission path, an over-voltage protection switch which connects or does not connect the transmission path to the ground, a PMOS transistor provided between the input terminal and a power supply, and an NMOS transistor provided between the input terminal and the ground are formed on an identical semiconductor substrate. If the semiconductor substrate is P-type, then a region in which the NMOS transistor is formed is surrounded by an N-well region.

Abstract: A method and device automatically convert a plurality of analog input channels using a single analog to digital conversion circuit. The device includes a multiplexer, an analog to digital conversion circuit and a configurable channel controller. The multiplexer has at least two analog input channels. The multiplexer also has control inputs and an output. The analog to digital conversion circuit is coupled to the output of the multiplexer and a clock signal. The analog to digital conversion circuit outputs a conversion value based on a voltage associated with the output of the multiplexer in successive clock cycles. The configurable channel controller outputs a control signal to the control inputs of the multiplexer to automatically select successive ones of the at least two analog input channels for conveying to the analog to digital conversion circuit.

Abstract: An improved thermometer-to-binary coder in which the bits of the thermometer code are used to directly generate the binary code without using an intermediate one-hot code.

Abstract: A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract: An A/D converter comprises: a differential amplifier row for amplifying differential voltages between an analog input voltage and reference voltages; a first sample/hold circuit row for sampling/holding the individual differential voltages amplified; a second sample/hold circuit having a pair of second and third sample/hold circuits connected in parallel to each output of the first sample/hold circuit row, thereby performing alternate sampling; a plurality of comparators for determining whether the individual differential voltages held by the first sample/hold circuit row are positive or negative; and an encoder for outputting digital code corresponding to the outputs of the comparators.

Abstract: A multi-function type absolute converter comprises a sensor I/O port having a plurality of sensor connection terminals that can be connected to a plurality of absolute sensors, a conversion circuit for converting absolute sensor detection signals input via the sensor connection terminals to digital position signals, a PLD that can perform prescribed processing on the digital position signals thus generated, a host I/O port having output terminals for outputting the digital position signals and signals generated by the programmable logic device, a switching circuit for switching sensor connection terminals, and a control circuit for controlling each part, the control circuit comprising mainly a CPU, ROM and RAM. The inclusion of a PLD enables the multi-function type absolute converter to be flexibly adapted to user specification.

Abstract: A priority encoding technique is provided which outputs a code corresponding to the highest-priority input line among input lines having a true value when true values are input to more than one of the input lines, which are prioritized and given codes. The technique includes performing higher-order-bit encoding by outputting higher-order bits corresponding to the group having its highest priority among those groups distinguished by the higher-order bits to which true values are input; and performing lower-order-bit encoding to output lower-order bits corresponding to the input line having the highest priority among input lines to which the true values are input. Further, the lower-order-bit encoding includes invalidating the input of true values into the input lines to groups having lower priorities than the highest-priority group distinguished by the higher-order bits.

Abstract: A power level determination device provides an output voltage usable as a specific reference power level corresponding to each RF input power level. The device includes a peak detector, which detects a pulse-type signal at its input and provides a non-pulse-type signal at its output. N comparators are provided, where N is an integer. Each of the N comparators has an output, a first input coupled to the output of the peak detector, and a second input coupled to a respectively different threshold voltage. The first one of the N comparators has a maximum threshold voltage. The threshold voltages decrease monotonically from No. 1 to No. N. N exclusive-OR components are provided. A first one of the N exclusive-OR components is coupled to ground and to the output of a first one of the N comparators.

Abstract: A high-speed and low-power encoder and an encoding method, wherein the encoder includes a switching unit for receiving a thermal code of a predetermined number of bits received in series, and outputting one bit among the received bits as a most significant bit and the other bits in parallel, and an encoder for dividing the bits received from the switching unit in parallel into groups having a predetermined number of bits, encoding the bits in each group into a predetermined number of bits, selecting one group of encoded bits using bits not used by the groups, and outputting least significant bits together with the most significant bit output from the switching unit.

Abstract: A method of converting a thermometer code in an analog-to-digital converter to a binary code. The method involves counting the ones in the thermometer code and using the parity of the count as bit 0 of the binary code; downsampling the thermometer code by dropping every other bit to form a downsampled code; counting the ones in the downsampled code, and using the parity of that count as bit 1 of the binary code; and repeating the procedure until the binary code is completed. A circuit carrying out this method in a single clock cycle without computations is disclosed.

Abstract: The present invention provides a digital-analogue transformer that can include a voltage divider, a decoder, a switch, a voltage adder and an output voltage controller. A digital-analogue transformer according to the present invention can increase resolution by inserting an interpolation voltage between the divided voltages generated from a resistor string, can modify a swing width of an output voltage by placing an amplifier using a feedback RC parallel circuit on an output stage, can protect a circuit from ‘glitch’ according to a switching operation by connecting a capacitor to a resistor string and voltage input terminals, and can reduce an offset difference generated from respective channels by having each of the respective digital-analogue transforming channels share a reference voltage generator and a bias voltage generator. The present invention can be applied to a digital-analogue transformer of a resistor string type.

Abstract: A method and apparatus converts an analog signal into a digital representation. The method comprises the steps of generating a quantity N of time-varying reference signals, where N is an integer greater than or equal to one, comparing an amplitude of the analog signal to an amplitude of each of the reference signals to determine whether the analog signal amplitude is greater than, less than or equal to reference signal amplitudes, and producing a timestamp each time the analog signal and reference signal amplitudes are equal. The apparatus comprises a reference signal generator and a quantity N of comparators, each of the comparators being connected to receive the analog signal, separately to receive a different one of the reference signals, and to produce a digital signal. The analog signal may be reconstructed from the digital representation.

Abstract: A combinational encoder (100) according to one embodiment is disclosed. The combinational encoder (100) can be used with an address encoder (300) to provide a compact priority encoder. The combinational encoder (300) receives a number of input signals (MATCH_IN0-MATCH_IN3) and provides a like number of output signals (MATCH_OUT0-MATCH_OUT3). Unlike a conventional priority encoder, which activates a single output signal in response to various input signal combinations, the combinational encoder (100) provides multiple active output signals in response to particular combinations of input signals. When applied to an appropriate address encoder (300), the multiple active output signals generate address values reflecting the desired priority of the input signals.

Abstract: A folding circuit is provided for outputting a periodic function representative of an analog input signal. The circuit includes at least two preamplifiers and a third differential amplifier circuit coupled to the preamplifier circuits for providing a bias current such that the flow of current is regulated through one of the preamplifier circuits at any given time, thereby providing a periodic function representative of an analog input signal.

Abstract: An encoding circuit for use with a comparator, includes a plurality of logic elements for receiving an input from a comparator, and a Gray code encoder for receiving an output from the plurality of logic elements. Both first and second type comparator errors (e.g., meta-stability errors and bubble-errors) are substantially eliminated simultaneously by the logic elements.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: A flash A/D conversion system and method with a reduced number of comparators. The voltage range applied by the comparators is moved or adjusted to provide an A/D converter with a much greater voltage range. The system comprises a reduced plurality of comparators each coupled to receive an analog input signal, and a decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective comparator reference signal for comparison with the analog input signal, and outputs a digital value indicative of the comparison between the analog input signal and the respective comparator reference signal. In one embodiment, a dynamic reference controller dynamically outputs one or more dynamic reference voltages to the plurality of comparators, wherein the comparators may receive different comparator reference voltages for comparing with the analog input signal.

Abstract: An OTA circuit is disposed between a differential pair composed of NMOS transistors and an NMOS follower transistor that composes an output buffer circuit. The OTA circuit generates a compensation current that is equal to a current that flows in a capacitance formed between the gate and the drain of each of the differential pair transistors and that flows in the reverse direction thereof. The compensation current cancels the current that flows in the capacitance formed between the gate and the drain of each of the differential pair transistors. Thus, a differential amplifier that has a high accuracy and, high gain, and a wide frequency band and that operates at a low power voltage can be accomplished. Using a differential amplifier having a high gain and a wide frequency band, a comparator that operates at high speed and an A/D converter using such a comparator can be accomplished.

Abstract: To minimize the number of positions to be altered in a transition from one output data word to the next in a scrambler for scrambling successive, thermometer coded binary input data words comprising N bits into corresponding successive output data words also comprising N bits, the scrambler is adapted, if the number of bits of one binary value has increased from one input data word to the next, to maintain bits of said one binary value in positions in the corresponding output data word where the previous output data word had bits of said one binary value, and to randomize the remaining bits of said one binary value to positions in the corresponding output data word where the previous output data word had bits of the other binary value.

Abstract: A thermometric-binary code conversion circuit 201 including an input unit 202 that outputs an encode input signal upon receiving a thermometric input signal. An encoder unit 204 outputs an encoded output signal upon receiving an encode input signal. An output unit 203 outputs a binary output signal upon receiving the encoded output signal. The encoder unit directly converts the code in accordance with a thermometric-binary code conversion equation expressed by Boolean algebra without forming intermediate code and without having dependence among bits of the binary output signal.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: In a resistor ladder circuit for supplying reference voltages to sub-A/D converter circuits constituting a pipeline type A/D converter, the circuit is configured in such a way that main resistors are connected in series with auxiliary resistors in order to produce a plurality of reference voltages so that the reference voltages which are supplied to an MDAC in the first stage differ from those which are supplied to the MDACs in and after the second stage.

Abstract: A method and apparatus for converting digital input signal to analog voltage are disclosed herein. The converting apparatus includes the following devices device. One of the pair of reference voltage selecting means is used to select a first voltage level as a first power source. Similarly, a second voltage level is selected as a second power source. The pair of controlled selectively coupling devices couples the first power source or the second power source as the charge power source responding to voltage level of every bit of the second portion of the digital input signal. The voltage cumulating device is used to generate the analog voltage by alternatively charging and redistributing the output capacitor with the first and the second capacitor. The foregoing method includes the following steps. At first, divide reference voltage levels into a first set and a second set of reference voltage levels.

Abstract: An A/D converter includes a resistor ladder for generating a plurality of reference potentials, a comparing section for comparing each of the reference potentials against an input analog signal to output a thermometric code, and a dynamic encoder composed of a combinational circuit to encode the thermometric code to a binary code by responding a clock signal. The A/D conversion is finished in a single clock cycle at a high speed, with a reduced number of elements and reduced power dissipation.

Abstract: A differential decoder has a wide output dynamic range and reduced area consumption. The decoder includes a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitters while the input signals are fed to their bases. The decoder also includes a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines through their emitter terminals, and are connected to the base and collector terminals of the bipolar transistors that drive the output lines, through their base and collector terminals.

Abstract: Analog-to-digital conversion with reduce sparkle codes. An analog-to-digital converter includes a plurality of comparators each coupled to receive an analog input signal, and an adder decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective reference signal for comparison with the analog input signal. Each comparator outputs a digital value indicative of the comparison between the analog input signal and the respective reference signal. The adder decoder adds the digital output signals generated by the comparators and outputs a digital representation of the analog input signal based on the result. This system may advantageously provide for a more efficient way to convert analog signals to digital signals without the generation of sparkle codes. The adder decoder may be a pyramid of adders. A sigma-delta converter may include the comparators in the analog-to-digital portion in the feedback loop and the adder decoder outside of the feedback loop.

Abstract: An encoder is divided into plural decoders, and one of the plural decoders is selected in accordance with a level of a thermometric data which is dependent on a level of an analog signal to be converted to a digital signal. The digital signal is determined by bit signals supplied from the selected encoder. For this structure, the non-selected decoders are not necessary to be pre-charged.

Abstract: To provide a method of searching a CAM which enables to search an address of matching contents cyclically recorded in a memory array of the CAM with a priority at once, the method of searching a CAM array (2) having first address lines (20), whereof certain are made active when the CAM array (2) is searched with a search key, comprises steps of: obtaining restricted search results by making address lines of the first address lines (20) having addresses lower than a restriction address inactive; selecting logic of third address lines (70) from logic of the restricted search results when any of the restricted search results is active, and from logic of the first address lines (20) as it is, when none of the restricted search results is active; and outputting a searched address by encoding a lowest active address line of the third address lines (70).

Abstract: There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more enhanced majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal.

Abstract: An analog to digital converter, which, by comparing utput signals of a first comparator group with a reference voltage by a second comparator group and setting this reference voltage to a level lower than an intermediate level of output signals of the first comparator group, generation of the intermediate level signal in the output signals of the second comparator group is prevented, therefore a malfunction of the analog to digital converter can be avoided.

Abstract: Flash analog-to-digital (A/D) conversion is performed with an n-bit converter using a resistive-divider string in which tap points are taken between each pair of adjacent resistors of the string as one input to each of a respective plurality of 2.sup.n -1 comparators. Each of the comparators has a second input in common with all of the other comparators at which an analog input voltage to be converted to digital form is applied. A transition point occurs at one of the tap points at which immediately adjacent ones of the comparators exhibit outputs of different binary states for a given a sample of the analog input voltage, signifying the transition point is occurring at the highest-order digital output at which the sampled analog input voltage exceeds a reference voltage. The transition point is detected during each sample, at a location within a group of consecutive ones of the comparators of preselected number considerably less than the total number of comparators in the converter.

Abstract: An electronic circuit can eliminate bubble errors by means of transferring a thermal code from spatial domain to time domain, and then from the time domain to the spatial domain. In accordance with the present invention, a rotator and a shift register are used to implement the circuit. The rotator is utilized to convert the data bits of the thermal code available in parallel into a serial thermal code. In other words, the data bits can be read serially at the output of the rotator. However, the serial thermal code is applied to the shift register for removing the bubble errors in response to the logic state in the serial thermal code and converting the serial thermal code into a corrected thermal code in parallel form. Accordingly, the electronic circuit for removing bubble errors according to the present can eliminate bubble errors occurring in the thermal code even if the bubbles occur randomly.

Abstract: There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more pseudo-majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal. There may be more than one stage of pseudo-majority gate correction.

Abstract: For certain high-speed applications, where high-precision is not required analog-to-digital conversion may be performed by employing several comparators, each having their own offset. Each such comparator with an offset may be constructed by employing a differential amplifier with an offset followed by a conventional comparator. Advantageously, the time to obtain a conversion to digital of an analog sample is reduced in comparison to prior art converters, thus enabling high-speed operation.