Abstract: A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

Abstract: The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output.

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code is disclosed. The analog to digital converter has a voltage reference generator to create a plurality of voltage references that divides the total conversion range of the input into increments equal to the smallest resolution increment. The digital output code is divided into most significant bits, intermediate significant bits and least significant bits. The most significant bits are encoded from a set of coarse digital signals that are formed in a set of coarse comparators. The coarse digital code is used to determine the selection of the sub-coarse voltage references. The intermediate significant bits are encoded from a set of subcoarse digital signals. The subcoarse digital code that and the coarse digital code are used to determine the selection of the fine voltage references.

Abstract: A priority encoder for encoding input data by scanning the input data in a predetermined direction, includes: a first voltage section for charging a plurality of output lines to a first voltage level; a plurality of switching elements connected to the plurality of the output lines, each of the plurality of switching elements being turned on in accordance with a value of the input data; and a second voltage section for charging a selected one of the plurality of output lines to a second voltage level different from the first voltage level, through the switching elements which are turned on.

Abstract: A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one-of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a V.sub.DD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, R.sub.

Abstract: This disclosure sets forth the use of input 2-bit encoders to form an encoder network capable of handling any number of encoder inputs by using the VALID output of each input 2-bit encoder as a data input to a later stage encoder and to select 2-way selector circuits using the code outputs of the input 2-bit encoders for selection of highest match.This is accomplished through the use of first and second input 2.sup.n encoders, the first being provided with the 2.sup.n high order inputs and the second being supplied with the 2.sup.n low order inputs and the outputs of the input encoders being coupled to a single 2-input encoder and n 2-way selectors to provide an encoder network with fewer circuits and better performance due to fewer stages of delay.If the number of desired inputs to the network is less than 2.sup.n but greater than 2.sup.n-1, known logic reduction techniques may be applied to the next higher 2.sup.n input encoder network to implement the desired 2.sup.n-1 encoder network.

Abstract: A flash analog-to-digital converter (8) is provided which includes a comparator array (10) which provides a thermometer code output THC1 through THC7. A binary search encoder (12) is coupled to the comparator array (8) as shown, and provides a binary code output B2 through B0.

Abstract: An analog-to-digital converter in which an analog input signal is folded by a plurality of folding circuits whose moduli, and hence half folding periods, are mutually prime with respect to one another. Each folding circuit has an associated comparator ladder having one less comparator than the modulus of the folding circuit. The collective output of the ladders, i.e. the states of the comparators in the ladders, uniquely corresponds to input signal magnitude over a dynamic range equal to the product of the folding circuits' moduli, permitting a greater dynamic range for the converter for the number of comparators used.

Abstract: The carry-line comprises a plurality of MOSFETs connected in series. MOSFETs precharge each node when they receive precharge signals /PR. In the case of high-order priority designated mode, when input signals are given for turning on MOSFETs located between one end of the high-order bit side of the carry-line, the control circuit discharges the intermediate node separately from the carry-line. In the case of low-order bit priority designated mode, when input signals are given for turning on MOSFETs located between one end of the low-order bit side of the carry-line and the intermediate node, the control circuit discharges the intermediate node separately from the carry-line.

Abstract: Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.

Abstract: A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge

Abstract: A circuit for conversion of an analog input signal to a digital representation of the analog signal. The circuit is typically employed in flash technology, since it is able to produce the digital representation of the analog signal faster and more efficiently than conventional flash converters. The circuit includes a plurality of resistors serially coupled between two reference voltages to form a plurality of nodes therebetween. A plurality of comparators, each having a first input coupled to one of the plurality of nodes and a second input coupled to the analog input signal. Accordingly each comparator compares the analog input signal to a voltage potential at one of the nodes to generate first and second complementary output signals at the outputs of the comparators. The complementary outputs are then applied to a decode circuit having a plurality of digital output lines and switches directly coupled to the digital output lines.

Abstract: A first subset of components of a first set of pairs of complementary differential electrical signals representative of a numerical value expressed in a multi-bit thermometer code, is processed in accordance with a first set of Boolean functions to produce a first set of output electrical signal components , and a second subset of components of the first set of pairs of complementary differential electrical signals is processed in accordance with a second set of Boolean functions to produce a second set of output electrical signal components. The first and second subsets and the first and second sets of Boolean functions are such that the first and second sets of output electrical signal components when combined form a second set of pairs of complementary differential electrical signals representative of the same numerical value expressed in a second multi-bit code with fewer bits than the multi-bit thermometer code.

Abstract: A thermometer-to-binary encoder includes a set of J input stage encoders E(1) through E(J) and an output encoder D, where J= 2.sup.K is an integer greater than 1. A set of digital input signals each representing a separate bit of a thermometer code T is grouped into J signal subsets representing further thermometer codes T(1) through T(J) providing inputs to a set of input stage encoders E(1) through E(J) respectively. Encoder E(J) produces an N-K+1 bit output binary code B(J) representing thermometer code T(J). Encoders E(1) through E(J-1) produce M-bit output binary codes G(1) through G(J-1), respectively, comprising the lower M bits of a binary code representing thermometer codes T(1) through T(J-1), respectively, where M is an integer greater than 1. Output encoder D processes codes G(1) through G(J-1) and B(J) to produce a set of digital output signals representing a binary code Y representing input thermometer code T.

Abstract: A method of transcoding digital data which, at the start, appear in the form of a thermometric code, the successive values of which may be represented by a first bit matrix (columns 1 to 8). The method uses an intermediate code defined by a second matrix (low significance), (columns (1), (2), (3) and (4)), and by a third matrix (high significance), (columns 4 and 8), which is extracted from the first matrix. The intermediate code delivers digital words which are shorter than the starting words and permits a later transformation into a binary code (columns [1], [2], [3], [4],) which is very simple. A decoder and a converter using this method is described where the decoder is organized so as to first produce the values of the intermediate code and then, the corresponding values in binary code. The converter employs analog gates with multiple inputs instead of the purely logic input blocks of the decoder.

Abstract: An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

Abstract: In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the number of bits that are set. If more than one bit is set, the highest priority bit is reset, the first portion is re-analyzed, and highest priority bit information and control information are again provided. If only one bit or no bit is set in the first portion, a second portion is analyzed, and highest priority bit information and control information regarding the second portion is provided. Analysis of the second portion, and of any subsequent portions, continues in similar fashion until no further bit positions are determined to be set in the data word.

Abstract: A priority encoder using a MOS array and neural network concepts is composed of an input side neuron group, an output side neuron group, a synapse group, a bias group and inverters. The encoder is simple in its construction and fast in its operating speed compared with the conventional priority encoders utilizing simple Boolean logic.

Abstract: A digital encoder (34) is partitioned into a plurality of rank ordered encoder circuits (36-39) which concurrently encodes least significant bits of an input signal from a first digital format to an output signal in a second digital format. Simultaneously, at least one bit of the input signal is used by a most significant bit encoder (42) to provide at least one most significant bit of the input signal in the second digital format. The at least one most significant bit is also used to select an output encoding of one of the plurality of rank ordered encoder circuits (36-39)as a remainder of the bits of the output signal in the second digital format.

Abstract: A flash type ADC (analog-to-digital converter) for converting analog signals to N-bit digital signals comprises 2.sup.N -1 comparators having different threshold values in a sequential order which perform full parallel-connected comparison. Buffer-amplifiers buffer the outputs of the respective comparators and a priority encoder encodes the outputs of the comparators. According to the present invention, the conventional reference resistance row is eliminated, and instead, comparators are used, resulting in simplified circuitry, improved conversion speed, and facilitated VLSI formation.

Abstract: A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval.

Abstract: In an A-D converter including a reference voltage generator, a D-A converter for outputting analog reference comparison voltage signals in response to digital signals; a comparator for comparing the voltages with an analog input voltage signal to be converted and outputting a reset signal when the voltage is substantially equal to the voltage, and a successive approximation register for successively outputting the digital signals to the D-A converter and an A-D converted signal in response to the reset signal, the D-A converter comprises in particular, at least one decoder block composed of plural array switches for coding any given function. Therefore, the analog input signal can be converted into the corresponding digital output signal in accordance with the coded function, thus providing an A-D converter suitable for use with a fuzzy controller. Further, the reference voltage generator is so configured as to easily change the coded membership function symmetrically or asymmetrically.

Abstract: The encoder is particularly for ultra fast high resolution flash analog-to-digital converters. A simple multiplexing is performed. An optional buffer memory stores selected codes prior to a final processing which can be relatively slow. An input register is unnecessary. The input code is divided into a least significant section code and at least one more significant section code each having a least significant bit. A multiplexer selects the least significant section code or a portion of one of the more significant section codes excluding the least significant bit thereof, in response to the least significant bits. The multiplexer includes a plurality of buffers for separately receiving the section codes and having outputs coupled in parallel. A decoder converts the least significant bits and selected code into the binary output code.

Abstract: A full flash analog-to-digital converter has a plurality of comparators for comparing an analog input voltage with respective reference voltages, a first-stage encoder for generating low-order bits based on output signals from the comparators, and a second-stage encoder for generating high-order bits based on the low-order bits generated by the first-stage encoder. The first-stage encoder generates a complement bit of the highest-order bit of the low-order bits generated by the first-stage encoder. The second-stage encoder generates the high-order bits based on the highest-order bit and the complement bit. Alternatively, the full flash analog-to-digital converter has an encoder for generating a plurality of bits based on output signals from the comparators. The encoder generates an additional bit by ORing the AND logical product of complement bits of second and third low-order bits of the plurality of bits, and a complement bit of a first low-order bit of the plurality of bits.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

Abstract: First and second comparator groups compare first and second analogue signals applied thereto, respectively, with reference voltages and convert the results of the comparison to binary signals to output the binary signals to an encoding circuit. The encoding circuit converts the binary signals supplied from the first and second comparator groups to digital data of a binary code corresponding to the product of the first and second analogue signals to output the digital data.

Abstract: In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

Abstract: The invention comprises an n-bit analog-to-digital flash converter comprising 2.sup.n /2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two output, OUT and an inverted version thereof, OUT. 2.sup.n -1 consecutive latches are provided. Every other latch receives at its inputs the OUT and OUT signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the OUT signal of an adjacent input comparator.

Abstract: A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.

Abstract: An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

Abstract: A high speed comparator unit for a flash A/D converter in which a bank of comparator units compare simultaneously an analog input voltage with equally spaced reference voltages, and an encoder ROM produces digital signals based on the comparator unit's outputs. The comparator unit includes a two-stage cascode configuration and a level shifter configuration which effectively reduces the miller-effect of the comparator unit.

Abstract: A parallel analog to digital converter and a method of processing at least two independnet signals therein are disclosed in accordance with the teachings of the present invention. The analog to digital converter has an improved sample and hold stage which, in addition to quantizing the analog signals, also multiplexes them. The sample and hold stage comprises at least two differential amplifier circuits, a latch stage, and a timing stage. Each differential amplifier circuit converts one analog input by comparing it to a reference voltage. The discrete output of the differential amplifier circuit is stored in the latch stage and outputted to an encoder. The timing circuit stage first selects one differential amplifier circuit to output its discrete signal, and then selects the latch stage to output its stored results. By sequencing through each differential amplifier circuit, the present invention effectively multiplexes the analog inputs.

Abstract: A priority encoder having MxN input lines and M output lines included M N-bit input priority encoder units, a precharging device, and a zero detecting device. Each N-bit input priority encoder unit includes an N-bit priority detecting device, a memory, a selector, a carry signal generating device, and a control device. The control device controls the output of the N-bit input prioroity encoder in accordance with the outputs of the N-bit priority detecting device and the carry signal generating device.

Abstract: There is provided an image display apparatus which imputs image information and displays it on a large display surface. This apparatus comprises: a photo sensitive material belt; rollers to support and drive the belt and a motor to rotate the drive roller; an image exposing apparatus of the laser beam scanning method; a toner developer; a pulse generator for continuously generating pulses in association with the rotation of the drive roller; a counter to count the pulses; and a controller to control the stop timing of the drive roller in order to stop the movement of the belt in accordance with the count value of the counter. The movement of the belt is controlled at the accurate timing synchronized with the pulses from the pulse generator. Thus, it is prevented that a joint of the belt appears in the display section, and the image information is displayed at the proper location in the display surface.