Input Signal Compared With Linear Ramp Patents (Class 341/169)
  • Patent number: 10859434
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger Panicacci
  • Patent number: 10798329
    Abstract: In an image pickup apparatus including first circuits, second circuits, and conversion units, an operation period of the second circuit is shorter than an operation period of the first circuit, and a number of the first circuit arranged in each unit cell is greater than a number of the second circuit arranged in each unit cell.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 6, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Daisuke Kobayashi, Tomoya Onishi, Takeru Ohya
  • Patent number: 10707264
    Abstract: To prevent a decline in image quality by reducing a fluctuation in an image signal that is based on a fluctuation in a voltage of a negative voltage power source. An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 7, 2020
    Assignee: SONY CORPORATION
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 10573679
    Abstract: A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Doo-won Kwon
  • Patent number: 10566375
    Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: February 18, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Raminda Madurawe, Richard Mauritzson
  • Patent number: 10484637
    Abstract: In a pixel section of an image sensor, pixels are arranged two-dimensionally, each of the pixels including an amplifier transistor that is connected to a power voltage and has a gate into which a voltage of a signal charge generated by a photoelectric conversion area is input and a selection transistor that is connected to the amplifier transistor and a signal line. The image sensor includes an AD conversion circuit having a reference transistor having a gate into which a ramp signal is input and a constant current source that is connected to the reference transistor and the signal line. The voltage of the ramp signal or a driving ability of the reference transistor changes depending on whether one selection transistor or a plurality of selection transistors is/are turned on per signal line to obtain a signal charge to be AD-converted.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 19, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hirokazu Kobayashi, Nobuhiro Takeda
  • Patent number: 10404934
    Abstract: An analog-to-digital signal processing method applied for an image sensor includes: providing a global analog-to-digital converter (ADC) capable of converting analog signals of all pixels of a pixel array into digital signals; providing a column-parallel ADC capable of respectively converting a plurality of analog signals of a plurality of pixels on different columns of the pixel array into a plurality of digital signals by using a plurality of ADC circuits; and, dynamically selecting and switching to enable one of the global ADC and column-parallel ADC to perform analog-to-digital conversion for analog data/signals of pixels on the pixel array.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: September 3, 2019
    Assignee: PixArt Imaging Inc.
    Inventors: Cheng-Seng Hsu, Jui-Te Chiu
  • Patent number: 10291869
    Abstract: In a pixel section of an image sensor, pixels are arranged two-dimensionally, each of the pixels including an amplifier transistor that is connected to a power voltage and has a gate into which a voltage of a signal charge generated by a photoelectric conversion area is input and a selection transistor that is connected to the amplifier transistor and a signal line. The image sensor includes an AD conversion circuit having a reference transistor having a gate into which a ramp signal is input and a constant current source that is connected to the reference transistor and the signal line. The voltage of the ramp signal or a driving ability of the reference transistor changes depending on whether one selection transistor or a plurality of selection transistors is/are turned on per signal line to obtain a signal charge to be AD-converted.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 14, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hirokazu Kobayashi, Nobuhiro Takeda
  • Patent number: 10097196
    Abstract: The present technology relates to an imaging element, a processing method, and an electronic device which are capable of reducing deterioration in an image quality of a captured image caused by power fluctuation. A counting unit includes a counting operation unit that performs a counting operation of counting the count value and a dummy operation unit that performs a dummy counting operation at a timing complementary to the counting operation of the counting operation unit. The present technology can be applied to, for example, an imaging element that counts a count value and performs AD conversion.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 9, 2018
    Assignee: SONY CORPORATION
    Inventor: Mamoru Sato
  • Patent number: 10057516
    Abstract: The present disclosure illustrates an image sensor. The image sensor includes an image sensing array and a voltage supply array. The image sensing array and the voltage supply array are coupled to an analog-to-digital converter array. The image sensing array captures image data. The image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to setting. The voltage supply array includes a plurality of voltage supply circuits to supply dummy voltage. During an auto-zero period, the voltage supply array provides the dummy voltage to the analog-to-digital converter array. Pluralities of comparators of the analog-to-digital converter array execute an auto-zero function based on the dummy voltage. After finishing the auto-zero function, the image sensing array outputs the image data to the analog-to-digital converter array. The analog-to-digital converter array makes the image data be digital.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 21, 2018
    Assignee: PIXART IMAGING INC.
    Inventor: Mei-Chao Yeh
  • Patent number: 9967493
    Abstract: An image sensing device includes: a pixel suitable for generating a pixel signal based on a first driving voltage; a ramp signal generation block based on a variable resistance, the ramp signal generation block being suitable for generating a ramp signal whose slope is controlled by a resistance value varied according to an analog gain; a noise compensation block based on a fixed resistance suitable for sensing a noise component included in the first driving voltage to generate a noise signal and reflecting the noise signal in the ramp signal; and a digital processing block suitable for generating a digital signal based on the pixel signal and the ramp signal.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 8, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jung-Eun Song, Si-Wook Yoo
  • Patent number: 9723179
    Abstract: According to one aspect, embodiments herein provide a TDI image sensor comprising an array of light sensing elements, at least one clock, and an image processor, wherein the at least one clock is configured to operate a first plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a first phase and to operate a second plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a second phase, and wherein the image processor is configured to read out a first signal from the first plurality of light sensing elements corresponding to a total charge accumulated at the first phase, to read out a second signal from the second plurality of light sensing elements corresponding to a total charge accumulated at the second phase, and to combine the first signal and the second signal to generate an image.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 1, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Stephen P. Shaffer, Stephen M. Palik, Hector A. Quevedo
  • Patent number: 9716510
    Abstract: Comparator circuits suitable for use in a column-parallel single-slope ADC comprise a comparator, an input voltage sampling switch connected between an input voltage Vin and a first node, and a sampling capacitor connected between the first and second nodes and which stores a voltage which varies with Vin when the sampling switch is closed. A first reset switch is connected between the second node and a reset voltage, an isolation buffer is coupled between the second node and a comparator input, and a voltage ramp switch applies a voltage ramp Vramp to the first node when closed. The comparator output toggles when Vramp exceeds Vin, with the isolation buffer maintaining a nearly constant capacitive load on Vramp. A ‘ramp disconnect’ feature can be used to increase the circuit's input range, and a dummy capacitor can be employed to maintain a constant capacitance on Vramp.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 25, 2017
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventor: Mihail Milkov
  • Patent number: 9692434
    Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: June 27, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dinesh Jain
  • Patent number: 9609257
    Abstract: A solid-state imaging device includes: a first substrate; a second substrate; a pixel unit in which pixels are disposed in a matrix; and an A/D conversion unit that is disposed for every columns of the pixels and counts a count clock for only a period according to a magnitude of the pixel signal. The A/D conversion unit includes: counter units that is provided in one of the first substrate and the second substrate and generates n-bit count signals; memory units that is provided in the other of the first substrate and the second substrate and holds the count signals and outputs the held count signals to horizontal signal transfer lines; and a connection unit that connects each counter unit to a corresponding one of the memory units and simultaneously transfer the count signals from at least two counter units to at least two memory units.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 28, 2017
    Assignee: OLYMPUS CORPORATION
    Inventor: Takanori Tanaka
  • Patent number: 9521344
    Abstract: A method of operating an image sensor includes generating a plurality of ramping up/down signals, and comparing a correlated double sampled pixel signal produced from an output of a pixel with a correlated double sampled first ramping up/down signal among the plurality of ramping up/down signals in a reset interval. The method further includes comparing the correlated double sampled pixel signal with the correlated double sampled first ramping up/down signal at one sampling time or more in an image interval, and a step of outputting a selected ramping up/down signal among the plurality of ramping up/down signals based on a result of the comparison.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Lee, Jin Woo Kim, Beom Soo Park, Jae Cheol Yun
  • Patent number: 9385735
    Abstract: One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Wei Lun Tao
  • Patent number: 9357151
    Abstract: A shared counter circuit for a column-parallel single-slope ADC includes an n-bit counter; n low-voltage (LV) drivers connected to receive respective counter output bits and to provide a logic high or logic low output signal which tracks the received bit, the voltage difference between the logic high and logic low output signals being less than Vdd; and a plurality of sets of regenerative latches powered by a supply voltage Vdd, each of which receives an output from a respective LV driver and latches and regenerates the received output as a rail-to-rail CMOS signal upon the occurrence of a trigger event. One typical trigger event occurs when a periodic ramp voltage exceeds an input voltage provided to the ADC which may originate, for example, from the columns of a photodetector array.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 31, 2016
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventor: Mihail Milkov
  • Patent number: 9232165
    Abstract: A solid-state imaging apparatus includes: a ramp signal generator for generating first and second time-changing ramp signals during first and second analog-to-digital conversion periods, respectively; comparators for comparing a reset signal of a pixel with the first ramp signal during the first analog-to-digital conversion period, and comparing a pixel signal with the second ramp signal during the second analog-to-digital conversion period; and memories for storing, as first and second digital data, count values of counting from a start of changing the first and second ramp signals until an inversion of outputs of the comparators, during the first and second analog-to-digital conversion periods, wherein the ramp signal generator supplies a current from a current generator to a first capacitor element by a sampling and holding operation of a switch, and generates the first and second ramp signals based on the same bias voltage held by the first capacitor element.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
  • Patent number: 9166614
    Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: October 20, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Higuchi, Kazuko Nishimura, Yuusuke Yamaoka, Yutaka Abe, Hiroshi Fujinaka
  • Patent number: 9124177
    Abstract: Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weidong Zhu, Xuening Li, Hal Chen, Wenkai Wu
  • Patent number: 9113101
    Abstract: An image sensor in which a plurality of pixels are arrayed in a row direction and a column direction, and an A/D converter is provided on each column of the plurality of pixels. The A/D converter performs one of charge and discharge from an initial value which is a voltage corresponding to an output signal from a pixel, outputs, as a digital value of the output signal, a value corresponding to a time taken for the voltage to become higher or lower than a predetermined reference voltage, and changes one of an amount of charge and an amount of discharge per unit time according to a possible value of the output signal.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 18, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Norio Negishi
  • Patent number: 9041579
    Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
    Type: Grant
    Filed: January 18, 2014
    Date of Patent: May 26, 2015
    Assignee: CMOSIS BVBA
    Inventors: Guy Meynants, Bram Wolfs, Jan Bogaerts
  • Patent number: 9041583
    Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 26, 2015
    Assignee: Sony Corporation
    Inventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
  • Patent number: 9019409
    Abstract: An image sensing device includes, inter alia, a ramp signal generation unit generating a ramp signal that decreases during first and second periods for finding data values corresponding to a pixel signal and an offset value, respectively. The image sensing device also includes a comparison unit compares the pixel signal with the ramp signal during the first period, and compares the ramp signal with an internally generated offset value during the second period. A first counting unit is configured to perform a counting operation during the first period, and a second counting unit configured to latch a count value of the first counting unit as a data value in response to the result of the first comparison operation during the first period, perform a down-count operation from the latched data value in response to the result of the second comparison operation during the second period, and latch a counting result.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventor: Eun Jun Kim
  • Patent number: 9019138
    Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 28, 2015
    Assignee: Sony Corporation
    Inventor: Hiroyuki Iwaki
  • Patent number: 9019142
    Abstract: In a solid-state imaging device which includes column analog-to-digital conversion circuits (ADCs) for converting pixel signals output from pixels into digital signals, each of the column ADCs includes a comparator which outputs a result of voltage comparison (comparison result signal) between the voltage of the pixel signal and an analog ramp voltage; a column counter which counts a column counter clock signal, which is either a clock signal or a phase-shifted clock signal, and stores a value represented by upper bits of a count value at a time of change in the comparison result signal; and a first latch unit which stores a value represented by lower bits of the count value. A second latch unit stores the value stored in the first latch unit.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiaki Hiraoka, Kenichi Shimomura, Yutaka Abe, Yusuke Shimizu
  • Patent number: 8994575
    Abstract: A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 31, 2015
    Assignee: Olympus Corporation
    Inventor: Yoshio Hagihara
  • Patent number: 8994866
    Abstract: A photoelectric conversion device includes a counter circuit configured to count a first clock signal to output a count signal thereof, a second clock signal generation unit configured to generate a second clock signal based on the first clock signal, and a clock synchronization unit configured to output a count start signal in synchronization with the second clock signal, wherein the counter circuit performs a counting operation in response to the count start signal synchronized with the second clock signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Yu Maehashi, Koichiro Iwata
  • Patent number: 8981983
    Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventor: Yasuaki Hisamatsu
  • Patent number: 8981987
    Abstract: An imaging device includes a comparator that compares a noise signal with each of a first reference signal and a second reference signal having potentials with different changing quantities per unit time, and that compares a photoelectric conversion signal with each of the first reference signal and the second reference signal. Also, the imaging device AD-converts signals obtained by amplifying the noise signal by a first gain and a second gain having different gains, and AD-converts a signal obtained by amplifying the photoelectric conversion signal by one of a first gain and a second gain.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hashimoto, Takashi Muto, Daisuke Yoshida, Hirofumi Totsuka, Yasushi Matsuno
  • Patent number: 8963694
    Abstract: A system and method are provided for selecting a remote controlled device to be controlled from among a plurality of remote controllable devices. The system includes an electronic device having a registration interface configured to register device data corresponding to the plurality of remote controllable devices, a position locator configured to determine position data corresponding to a position of the electronic device, and an orientation interface configured to receive orientation data corresponding to an orientation of a user. A controller is configured to select the remote controlled device based on the device data, the position data, and the orientation data. The plurality of remote controllable devices each may include a respective data source configured to provide the device data, and a headset may be configured to generate the orientation data.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 24, 2015
    Assignees: Sony Corporation, Sony Mobile Communications AB
    Inventors: Martin Nystrom, Erik Ahlgren
  • Patent number: 8941527
    Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: January 27, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Zheng Yang, Guangbin Zhang, Yuanbao Gu
  • Patent number: 8941528
    Abstract: An analog-to-digital conversion circuit includes a reference current generating unit suitable for generating a reference current varied by a given level in a sampling stage, a ramp voltage generating unit suitable for generating a ramp voltage corresponding to the reference current, and a comparison unit suitable for comparing the ramp voltage with a voltage level of a pixel signal to output a comparison signal.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Gun-Hee Yun
  • Publication number: 20150014517
    Abstract: The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.
    Type: Application
    Filed: February 15, 2013
    Publication date: January 15, 2015
    Applicant: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventor: Masayuki Ikebe
  • Patent number: 8890742
    Abstract: A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Erik Tao, Calvin Yi-Ping Chao
  • Patent number: 8890730
    Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventors: Donnacha Lowney, Christophe Erdmann, Edward Cullen
  • Patent number: 8878954
    Abstract: When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hashimoto, Takeru Suzuki, Yasushi Matsuno, Takashi Muto
  • Patent number: 8866650
    Abstract: A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Stephen J. Spinks, Andrew Talbot, Colin Mair
  • Patent number: 8854244
    Abstract: An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Hong-Joo Park, Sanghoon Lim, Hee-Cheol Choi, Hai Yan
  • Patent number: 8847809
    Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 30, 2014
    Assignee: Round Rock Research, LLC
    Inventor: Alexander I. Krymski
  • Patent number: 8836840
    Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Sony Corporation
    Inventor: Manabu Kukita
  • Patent number: 8830106
    Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Udayan Dasgupta, Ganesan Thiagarajan, Venugopal Gopinathan
  • Patent number: 8823575
    Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: September 2, 2014
    Assignee: Olympus Corporation
    Inventor: Yoshio Hagihara
  • Patent number: 8816893
    Abstract: An example ramp analog-to-digital converter (ADC) for generating at least one bit of a digital signal includes a modified ramp signal generator, a comparator, and a control circuit. The modified ramp signal generator receives a ramp signal and generates a modified ramp signal in response thereto. The comparator compares an analog input with the modified ramp signal. The control circuit controls the modified ramp signal generator, such that the analog input is converted a variable M number of times for each period of the ramp signal. The number M is dependent on a magnitude of the analog input. In one example, the number M is greater for analog inputs of a lower magnitude, such that the analog inputs of the lower magnitude are converted more times than analog inputs of a higher magnitude.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: August 26, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventor: Zheng Yang
  • Patent number: 8803725
    Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Yuji Osaki, Tetsuya Hirose
  • Patent number: 8773191
    Abstract: One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu Jin Park, Han Yang, Sin-Hwan Lim, Kyo Jin Choo, Seog Heon Ham
  • Patent number: 8773544
    Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Min Koh, Seog-Heon Ham, Yong Lim
  • Patent number: 8766843
    Abstract: A comparator includes a first amplifier and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors serve as a comparison part that receives a reference voltage, a signal level of which changes with a slope, at a gate of one of the differential-pair transistors, receives an input signal at a gate of the other of the differential-pair transistors, and compares the reference voltage with a potential of the input signal. The level holding part holds a level of the first output node such that the other transistor having an output part thereof connected to the first output node out of the differential-pair transistors of the first amplifier does not fall into a level at which a saturated operation condition is not satisfied.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventor: Yosuke Ueno
  • Patent number: 8760213
    Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura