Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information.

Abstract: In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages.

Abstract: A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.

Abstract: A universal game console controller that has an LCD presenting, depending on what type of game console a user has input, a controller key layout for a first type of game console or a controller key layout for a second type of game console.

Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.

Abstract: According to one embodiment, an A/D converter includes a determination circuit configured to determine whether a first analog signal is greater than a second analog signal or not, the first analog signal being a present A/D conversion target, the second analog signal being an immediately preceding A/D conversion target, a calculation circuit configured to add a reference voltage to a difference obtained by subtracting the second analog signal from the first analog signal, a generation circuit configured to generate a comparison voltage, a comparator configured to compare a calculated value of the calculation circuit with the comparison voltage, and a conversion circuit configured to convert a period into a digital signal, the period being required until the calculated value is identical with the comparison voltage by the comparator.

Abstract: An apparatus and method for calibrating a ramp slope value of a ramp signal to increase the accuracy of the slope of the ramp signal used within CMOS image sensors. An image sensor includes an active pixel sensor (APS) array, a ramp signal generator and an analog-to-digital converter (ADC). The APS array is configured to generate a reset signal and an image signal for a pixel of a selected row of the APS array. The ramp signal generator is configured to generate a ramp signal, a ramp slope value of the ramp signal being adjusted based on a slope control signal. The ADC is configured to generate a digital code based on the ramp signal and a difference between the reset signal and the image signal.

Abstract: A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparator matrix or Vernier ring TDCs with comparator matrix comprise two rings or chains of delay stages with slightly different propagation delays per stage and a plurality of comparators for comparing two signals propagation along two rings or chains and determining when the lag signal passes the lead signal. The lead and lag signal are initiated by two events and are each fed into a separate one the first stages of one of the specified rings or chains. The comparators are able to be organized in a comparator matrix in order to occupy less space and permit reuse.

Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract: An image pickup circuit includes a plurality of circuit blocks. Each of the plurality of circuit blocks includes a plurality of comparing elements, a single counter, and a plurality of storage units. Each of the comparing elements compares a pixel signal supplied through a vertical signal line connected to vertically aligned pixels in a plurality of pixels arranged in a matrix, and a slope signal whose voltage is changed from an initial voltage at a constant slope. The counter counts an elapsed time since a voltage of the slope signal starts to change from the initial voltage. Each of the storage units stores a count value obtained by the counter in accordance with a comparison result of the comparator, the count value corresponding to an elapsed time until the voltage of the slope signal is changed from the initial voltage to a voltage coinciding with the pixel signal.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: A solid-state imaging device and an imaging apparatus are provided. The solid-state imaging device performs an AD conversion in a column parallel for an analog pixel signal outputted from each of pixels disposed in a two-dimensional matrix shape. The solid-state imaging device includes: an AD conversion unit including a plurality of pixel signal accumulating units; a first switching unit for disconnecting parallel connection of a second pixel signal accumulating unit other than a first pixel signal accumulating unit which is one of the plurality of pixel signal accumulating units; and a second switching unit for connecting the second pixel signal accumulating unit to a pixel signal line of a second pixel adjacent to the first pixel in a row direction, when parallel connection of the second pixel signal accumulating unit is disconnected by the first switching unit.

Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.

Abstract: An image sensor includes a pixel array, and a correlated double sample circuit coupled to one of the pixels in the pixel array. The correlated double sample circuit includes first and second inputs, and first and second sample capacitors respectively coupled to the first and second inputs. The first input is for receiving an analog signal from a pixel, and the second input is for receiving a time varying reference signal. The analog signal varies during a pixel readout period, and has a first level during a first reset period and a second-level during a second read period. A comparator circuit compares the time varying reference signal and the analog signal. The analog signal and the time varying reference signal are constantly read onto one of the first and second sample capacitors during both the first reset period and the second read period.

Abstract: An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: A handheld electronic device includes a reduced QWERTY keyboard and is enabled with disambiguation software. The device provides output in the form of a default output and a number of variants. The output is based largely upon the frequency, i.e., the likelihood that a user intended a particular output, but various features of the device provide additional variants that are not based solely on frequency and rather are provided by various logic structures resident on the device. The device enables editing during text entry and also provides a learning function that allows the disambiguation function to adapt to provide a customized experience for the user. The disambiguation function can be selectively disabled and an alternate keystroke interpretation system provided. During text entry, a user is able to delimit a language entry session, such the entering of a word, by actuating a multiple-axis input device or another input device.

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Abstract: A duty correction circuit includes: a C-element including a first input and a second input; and an inverter connected to the second input of the C-element, wherein the C-element obtains an output of a logic “1” when both inputs are the logic “1”, obtains an output of a logic “0” when both inputs are the logic “0”, and maintains the output to a previous state in other conditions, and complementary clocks having a phase difference of an approximately half cycle are inputted to the first input of the C-element and the inverter respectively.

Abstract: An electronic apparatus includes: an AD conversion section that has a comparing section, which receives a reference signal whose level changes gradually from a reference signal generating section that generates the reference signal and which compares the reference signal with an analog signal to be processed, and a counter section, which receives a count clock for AD conversion and performs a count operation on the basis of a comparison result of the comparing section, and that acquires digital data of the signal to be processed on the basis of output data of the counter section; a count operation period control section that controls an operation period of the counter section in each processing period on the basis of the comparison result of the comparing section; and a driving control section that controls the reference signal generating section and the AD conversion section.

Abstract: It is an object of the present invention to provide a solid-state imaging device for enhancing accuracy of AD conversion and active switching of up-counting and down-counting in the asynchronous counter without limiting the AD conversion frequency. The solid-state imaging device according to the present invention includes an asynchronous counter having an up-counting mode in which up-counting is performed, a down-counting mode in which down-counting is performed, and a holding mode for switching operation settings between the up-counting and the down-counting while maintaining a count value held in the asynchronous counter.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: An analog-to-digital converter receives first and second analog signal voltages, and first and second comparison voltages. The first and second comparison voltages decrease by the same fixed inclination from a first reference voltage to below the first signal voltage and from a second reference voltage to below the second signal voltage, respectively. The converter counts cumulatively over first periods to acquire a first result, counts cumulatively over second periods to acquire a second result, and outputs a difference between the first and second results as a digital quantity. Each first period is time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first signal voltage. Each second period is time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second signal voltage.

Abstract: A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.

Abstract: A method for operating a single slope analog-to-digital converter (ADC) includes providing a ramp generator to provide at least one voltage-ramp segment; applying delta-sigma modulation to the voltage-ramp generator to generate a delta-sigma modulated voltage ramp; operating a digital counter synchronously with the voltage-ramp generator; comparing the delta-sigma modulated voltage-ramp to an input voltage; and latching a count from the digital counter in response to the output of the comparator.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: A solid-state image sensing device includes: a pixel unit that has plural pixels and outputs analog pixel signals; a ramp signal generator unit that generates a ramp signal having a predetermined initial voltage and a fixed gradient; and an analog-digital converter unit that compares the analog pixel signals output by the pixel unit to the ramp signal generated by the ramp signal generator unit and digitally converts the analog pixel signals based on a comparison time, wherein the analog-digital converter unit can perform operation in a digital addition mode of adding the analog pixel signals output from the plural pixels of the pixel unit among plural pixels and outputting the signals as digital pixel signals, and the ramp signal generator unit can set the initial voltage of the ramp signal to an arbitrary value after resetting a potential of the ramp signal in the digital addition mode.

Abstract: The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.

Abstract: An integrated AD converter includes: a comparator comparing an input voltage with a reference voltage with a ramp waveform whose voltage value linearly changes with time; a high-bit counter triggered by inversion of an output signal of the comparator to start or stop an operation of counting for every cycle of a main clock signal; a time quantizer latching phase information at a timing at which the output signal is inverted using a plurality of clock signals including main clock signals of different phases, and decodes a value of the latched phase information to thereby output lower bits with a resolution higher than a clock cycle; and a regulating unit synchronizing the output signal with the main clock signal, and determines timings of starting and stopping the operation of the high-bit counter and a value for latching the phase information of the main clock signal using a signal resulting from the synchronization.

Abstract: Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: A solid-state imaging device comprises a pixel array; a reference signal generation unit operable to generate a reference signal that changes monotonically for a predetermined period in a horizontal period; a comparator operable to compare the level of a pixel signal with the level of a reference signal; a counter operable to count input clock pulses; a memory operable to store the number of counts counted by the counter as a digital value; and a timing control unit operable to generate a clock that is to be input into the counter, and change frequency of the clock that is to be input into the counter based on external input data.

Abstract: A solid-state imaging device including: an analog-digital converter unit in column parallel arrangement, the analog-digital converter unit having a plurality of pixels arranged to convert an incident light quantity to an electric signal, in which an analog signal obtained from the pixel is converted into a digital signal, wherein the analog-digital converter unit is configured of: a comparator operable to compare a value of a column signal line from which an analog signal obtained by the pixel is outputted with a value of a reference line, and a counter operable to measure a time period by the time when comparison done by the comparator is finished and to store the comparison result, wherein the solid-state imaging device further includes: a module for controlling an output of the comparator operable to control the output of the comparator depending on the output of the comparator.

Abstract: The invention relates to a method for the digital transmission of an analogue measuring signal (M), comprising the following steps: comparing momentary values of a triangular signal (D) with a value of the measuring signal (M) for generating a binary measurement pulse (PM); comparing momentary values of the triangular signal (D) with a predeterminable first reference variable (R1) for generating a binary reference pulse (PR) that corresponds to the measurement pulse (PM) and transmitting the measurement pulse (PM) and reference pulse (PR) at a constant phase.

Abstract: An analog-to-digital converter in an image sensor is implemented with a plurality of comparator units. Each comparator unit has a respective capacitor array and respective switches integrated therein. Such capacitors and switches across the comparator units are operated for generating ramp voltages for such comparator units for performing analog-to-digital conversion with correlated double sampling. Thus, circuit area and power consumption of the CMOS image sensor may be minimized.

Abstract: An analog-digital converter is provided. The analog-digital converter includes: a comparing section for comparing an input signal voltage and an analog ramp voltage in which a voltage level gradually increases; and a latch section for storing a digital value of a digital ramp signal, in which a digital value of a voltage level gradually increases in synchronization with the analog ramp voltage when the analog ramp voltage or a voltage corresponding to the analog ramp voltage and the input signal voltage are equal. A voltage in which part or all of a plurality of analog ramp signals are added is used as the analog ramp voltage so that a gain is selectable.

Abstract: A ramp generation circuit including, a charge supply unit which generates predetermined charges every predetermined time, an integration circuit which accumulates the charges generated from the charge supply unit and converts the charges into a voltage, and, an attenuation unit which outputs, to an output terminal, a voltage obtained by attenuating a noise value of an output voltage from the integration circuit.

Abstract: An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC) and a ramp signal generator. The APS array includes a plurality of pixels arranged in a two-dimensional matrix, wherein the APS array generates a reset signal and an image signal for each selected column of the APS array. The first ADC includes a correlated double sampling (CDS) circuit array comprising CDS circuits that are arranged for each column of the APS array, wherein the first ADC generates a digital code from a signal corresponding to the difference between the reset signal and the image signal which are generated by the CDS circuit using a ramp signal. The ramp signal generator generates the ramp signal, wherein a second ADC receives a feedback of the generated ramp signal and generates a feedback reference code, and wherein the ramp signal generator calibrates the ramp signal based on a comparison using the feedback reference code.

Abstract: A solid-state image sensing device includes: a pixel unit that has plural pixels and outputs analog pixel signals; a ramp signal generator unit that generates a ramp signal having a predetermined initial voltage and a fixed gradient; and an analog-digital converter unit that compares the analog pixel signals output by the pixel unit to the ramp signal generated by the ramp signal generator unit and digitally converts the analog pixel signals based on a comparison time, wherein the analog-digital converter unit can perform operation in a digital addition mode of adding the analog pixel signals output from the plural pixels of the pixel unit among plural pixels and outputting the signals as digital pixel signals, and the ramp signal generator unit can set the initial voltage of the ramp signal to an arbitrary value after resetting a potential of the ramp signal in the digital addition mode.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: A data processing device includes a comparing unit that compares a reference signal and respective processing object signals, a count-period control unit that determines a count period to perform count processing, a count unit that performs the count processing in the count period designated by the count-period control unit, stores a count value, applies the count processing to both a subtraction element and an addition element in an identical mode of any one of an up-count mode and a down-count mode, and starts the count processing for a following processing object signal using a count value for a preceding processing object signal as an initial value, and a correcting unit that corrects digital data of a multiply-accumulate result of the plural processing object signals to digital data in which a count value is corrected.

Abstract: An A/D converter comprises a ramp voltage generation circuit, a voltage comparison circuit comprising an arithmetic unit comparing an analog voltage to be converted with a reference voltage showing the voltage change of a ramp voltage, and changing an output when the reference voltage equals the analog voltage, a counter counting and outputting a digital value corresponding to the reference voltage, a latch circuit latching and outputting the digital value when the output of the voltage comparison circuit changes, an averaging process circuit to obtain an average noise voltage, a target noise voltage setting circuit setting a target noise voltage, and a control circuit adjusting at least one of a counting start timing of the counter with respect to a control reference timing, or the criterion level of the reference voltage at the counting start timing, based on a difference between the average noise voltage and the target noise voltage.

Abstract: An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.

Abstract: An on die thermal sensor (ODTS) in a memory device includes: a band gap unit for detecting a temperature of the memory device to output a first voltage corresponding to the temperature; and an analog-to-digital converting unit for outputting a digital code having temperature information based on the first voltage, the digital code having varied resolution according to temperature ranges.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: An A/D converter compares one or more analog voltages to be converted with a reference voltage given by a voltage change value of ramp voltage whose voltage value changes monotonically for a certain period or a voltage proportional to the voltage change value, converts each analog voltage to a digital value corresponding to the reference voltage, and outputs it, the A/D converter comprising an arithmetic unit for comparison between the analog voltage and reference voltage with respect to each analog voltage, the arithmetic unit having a first power supply line for receiving a power supply voltage, wherein the first power supply line is provided as another power supply line not affected by voltage fluctuation of a second power supply line for supplying a system power supply voltage by providing a MOS transistor whose gate terminal is connected to a stabilized voltage source between the first and second power supply lines.

Abstract: It is an object of the present invention to provide a solid-state imaging device for enhancing accuracy of AD conversion and active switching of up-counting and down-counting in the asynchronous counter without limiting the AD conversion frequency. The solid-state imaging device according to the present invention includes an asynchronous counter having an up-counting mode in which up-counting is performed, a down-counting mode in which down-counting is performed, and a holding mode for switching operation settings between the up-counting and the down-counting while maintaining a count value held in the asynchronous counter.

Abstract: An analog signal is converted to a digital value having a given number of bits that define given quantization levels, by repeatedly sampling the analog signal at a resolution that is less than that which is defined by the given number of bits. Lower resolution sampling results are thereby obtained. The lower resolution sampling results are summed to obtain the digital value having the given number of bits.

Abstract: A single slope ADC using a hysteresis property includes a first comparator, a second comparator, and a code generating unit. The first comparator outputs a compared signal by receiving and comparing an input signal having a constant level with a ramp signal, the second comparator has a hysteresis property having an input terminal connected to an output terminal of the first comparator, and the code generating unit is connected to the second comparator and outputs a digital code corresponding to a time-point of a state transition of an output signal of the second comparator. The second comparator can be embodied as a Schmidt trigger or a Schmidt-trigger inverter. The single slope ADC further includes a controller that controls at least one of a rising threshold or a failing threshold of the Schmidt trigger or of the Schmidt-trigger inverter.