Abstract: A semiconductor integrated circuit includes a differential amplifier circuit receiving first and second input voltages, a latch circuit comparing a voltage received from a first output terminal of the differential amplifier circuit through a first capacitor and a voltage received from the second output terminal of the differential amplifier circuit through a second capacitor and providing a digital signal representing a result of a comparison between the first and second input voltages, and a third capacitor having a first terminal coupled to a second terminal of the first capacitor and a second terminal coupled to a second terminal of the second capacitor.

Abstract: The disclosure relates to a microelectronic image sensor device comprising: at least one detector formed by at least one photo-detector element, at least one integration capacitor associated to the photo-detector and capable of providing at least one analogue signal capable of varying at least according to a current provided by the detector, and analogue/digital conversion means for equalising charges comprising: a comparator, injector means capable of modifying the analogue signal by one or more injections, respectively of a given quantity of charge, into the capacitor, command means for charge injector means capable of modulating the given quantity of charge injected according to the intensity of said current.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.

Abstract: A dual slope A/D converter uses two opposite sense ramps added to its differential input. The value in a digital counter is latched at the time when the two ramps intersect. This enables a more consistent switching point, allowing the amplifier to the linear over a larger part of its range.

Abstract: A readout circuit is adapted for receiving a line analog image signal from an image sensor array of an image sensor. The readout circuit includes an amplifying unit, an m-bit analog-to-digital converter, and an m-to-n bit digital converting unit. The amplifying unit is adapted for amplifying and correcting amplitude of the line analog image signal, and outputs an amplified and corrected analog signal. The m-bit analog-to-digital converter is coupled to the amplifying unit, and is operable to convert the amplified and corrected analog signal into a corresponding m-bit digital signal. The m-to-n bit digital converting unit is coupled to the m-bit analog-to-digital converter, receives the m-bit digital signal from the m-bit analog-to-digital converter, and is responsive to a k-bit control signal for converting the m-bit digital signal into an n-bit digital signal, wherein m is greater than or equal to n.

Abstract: Certain embodiments of the present invention provide for an imaging system including an index value source, a transmitter, a receiver, and an image processing component. The index value source is capable of generating an index value. The index value source is part of and/or included in an imaging system detector. The transmitter is in communication with the index value source. The receiver is in communication with the transmitter. The image processing component is in communication with the receiver. The image processing component includes a lookup table. The image processing component is capable of generating a pixel value based at least in part on an index value and a lookup table. The pixel value has a bit-width greater than the index value. In an embodiment, the receiver is in wireless communication with the transmitter.

Abstract: An analogue-to-digital converter comprises a window comparator. The window comparator comprises an input for an analogue input signal and an output for a comparison result indicating a result of a comparison of the analogue input signal with an upper bound and a lower bound of a level window. The analogue-to-digital converter further comprises a level window position signal generator. The level window position signal generator comprises an output for a level window position signal adjusting a position of the level window based on an information derived from the comparison result and indicating whether the level window should be increased, decreased or maintained. The analogue-to-digital converter further comprises an output for a digital information based on the comparison result.

Abstract: An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

Abstract: An image processing circuit for reducing noise. The image processing circuit includes a CDS circuit for taking a potential difference between a pixel signal at a reset of an image pickup device and a pixel signal after exposure, and an AD conversion circuit. The AD conversion circuit includes an increment counter and AD conversion clock provided for the AD conversion of the potential difference of the image pickup device between at a reset and after exposure, and an averaging ADC control circuit for averaging a plurality of digital code values obtained through the AD conversion repeated a plurality of times.

Abstract: An internal ADC in a delta-sigma ADC is characterized using inherent delta-sigma ADC circuitry. In one embodiment, a constant DC value is applied as the input signal. The sum of the constant DC value and a feedback signal is integrated. Then, a digital approximation including the integrated sum is generated. The feedback signal is generated and allows ramping of the integrated sum.

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

Abstract: An image sensor an image sensor includes an image sensing element which converts incident light into an analogue signal, a voltage generator which includes a variable resistor circuit and which generates a ramping voltage, where a slope of the ramping voltage is variable and corresponds a resistance value of the variable resistor circuit, a converter which converts a voltage of the analogue signal into a digital signal using the ramping voltage generated by the voltage generator, and a controller which controls the resistance value of the variable resistance circuit.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor capable of performing an analog correlated double sampling method is provided. The CMOS image sensor includes an image capturing unit for capturing an analog signal corresponding to an image of a subject; an analog-digital converting unit for converting the analog signal into a digital signal by using a ramp signal decreasing in a fixed slope according to a reference clock; a ramp signal generation unit for providing the ramp signal to the analog-digital converter; and a control unit for providing said units with control signals and outputting data to the outside through an interface.

Abstract: Provided is an image pick-up semiconductor device capable of testing operating characteristics of an analog-digital converter while the image pick-up semiconductor device operates. The device includes an active pixel sensor array having a plurality of pixels converting optical signals input from an external source into electrical signals, a columnar analog-digital converter converting signals output from the active pixel sensor array into first digital data, and a test analog-digital converter receiving two external signals and converting a voltage difference between the two external signals into second digital data.

Abstract: The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.

Abstract: A CMOS image capture device includes an array of pixel elements configured to convert an image received as light at a surface thereof into analog output signals. An image processing circuit is also provided. The image processing circuit is configured to generate digital output signals from which the image can be recreated in response to the analog output signals. The image processing circuit has self-adjustable gain characteristics. The image processing circuit includes a ramp signal generator having an integration circuit therein with an adjustable RC time constant. The integration circuit includes an operational amplifier and a resistor array and/or a capacitor array electrically coupled to the operational amplifier. This resistor array and/or capacitor array enables the adjustable RC time constant.

Abstract: An analog to digital converter ADC is adapted for low power for use in an imaging array. The ADC is a digital inverter with feedback to convert an asynchronous ramp voltage to an output count at each crossing of a voltage threshold. A separate circuit generates a voltage ramp that is coupled through a capacitor to a photocurrent from a detector, generating an integrating voltage that is raised at a source follower circuit. The integrating voltage from the source follower circuit is converted to another voltage ramp and inverted at the ADC. A global count from an array of such ADCs is stored in a grey counter. The ADC is sufficiently power-efficient that each unit cell of an array of photo detectors can have its own ADC. Circuit and device-level embodiments are disclosed.

Abstract: A method for storing a result of a tuning process includes generating a first characteristic signal using a signal generator. The method also includes generating a second characteristic signal using a master circuit, wherein the master circuit generates the second characteristic signal in response to a current signal. The method further includes determining an adjustment to the current signal based at least in part upon the first and second characteristic signals, and storing a digital value representing the adjustment.

Abstract: A ramp waveform generation circuit which comprises a first reference power supply, and supplies a ramp waveform signal to an analog/digital conversion circuit further comprises a connection circuit for reflecting the amount of fluctuation of the output potential of a second reference power supply which is installed in a noise elimination circuit for eliminating the noise of an analog signal inputted to the analog/digital conversion circuit in the output potential of the first reference power supply.

Abstract: A high-speed digital-to-analog converter (DAC) measurement method acquires and quantizes an analog ramp output by the DAC corresponding to a digital ramp input to produce a quantized ramp, determines a start and end of the quantized ramp, obtains a difference between the quantized ramp and an ideal ramp to produce a quantized periodic signal (triangular or sinusoidal), determines a frequency for a qualified peak from an FFT of the quantized periodic signal, produces a mask filtered periodic signal from an iFFT around the qualified peak, and determines a sample window spanning a local maximum and minimum for each period of the quantized periodic signal. The ramp step levels are the averages of the samples within each sample window. From the step levels in DAC LSB's, resolution, monotonicity, differential lineary and integral linearity are determined for the DAC.

Abstract: Disclosed is an apparatus for converting an analog image data into a digital image data in a CMOS image sensor including a pixel array having M (row line)×N (column line) color pixels, wherein the color pixels include a first color pixel for sensing a first color, a second color pixel for sensing a second color and a third pixel for sensing a third color.

Abstract: A comparator is arranged to compare a series of analog voltage signal samples on a first capacitor with a voltage on a second capacitor which is linearly increased or decreased to equal the sample value. The comparator's single output freezes the count of the counter at counts which are proportional to the voltage of the respective samples. In this manner, analog to digital conversion can be accomplished using a single line between the analog and digital sides of a circuit, thereby reducing parasitic capacitance.

Abstract: A vehicle weight classification system determines the weight of a seat occupant for controlling airbag deployment. Strain gauge sensors preferably provide signals having a magnitude that is indicative of the weight of the seat occupant. A converting module converts the sensor signals into timing information. A microprocessor, which includes a timer module, receives the timing information and makes a weight determination from the timing information.

Abstract: A ramp generator includes an array of capacitors having a common top plate that provides a ramp output signal. Each of the capacitors has a bottom plate switched sequentially between a low reference voltage and a high reference voltage in response to a value in a shift register. For an upward ramp, capacitors can be switched to their high reference voltages in succession, increasing the output voltage on the common top plate; for a downward ramp, capacitors can be switched to their low reference voltages in succession, decreasing the output voltage. The capacitors can be switched by a multi-bit shift register, each bit of which controls one capacitor's voltage. Each time a clock signal is applied to the shift register, a value in the shift register shifts another capacitor between its low and high reference voltages.

Abstract: A comparator for an analog-to-digital converter comprises an input stage (in+, in−, M1, M2) for receiving an input signal; a bipolar latch stage (Q1, Q2; Q1a-b, Q2a-b) coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output (Va, Vb) to a level suitable for CMOS circuitry; and an output (out+, out−). The means for amplifying includes at least one tapping transistor (Q3, Q4) coupled to the latch stage for, depending on the latch decision, tapping a collector current (Ic2; Ic1) from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain (&bgr;) of the latch stage can be used to amplify a latch bias current (Ia, Ib) of the latch stage to thereby provide for the amplification.

Abstract: A range recognizer applies acquired data to the inputs of a plurality of boundary comparators simultaneously, treating an entire range of values for the data as a single continuum which is partitioned by a series of internal boundaries that are monitonically increasing. Each boundary comparator compares the value of the data with its unique boundary value and provides the results to a single range encoder logic to generate a single binary word as an encoded result indicative of the comparison for the entire range. An upper boundary result of one boundary comparator is combined with a lower boundary result of an adjacent higher boundary comparator prior to input to the single range encoder logic. The result is a reduction In the number of output pins required on an integrated circuit (IC) for reporting the encoded result for a corresponding plurality of range recognizers.

Abstract: A method and apparatus precondition an analog signal and convert the preconditioned signal into a digital representation. The method includes preconditioning the analog signal, generating a quantity N of reference signals, comparing an amplitude of the preconditioned signal to an amplitude of the reference signals to determine whether the preconditioned signal amplitude is greater than, less than or equal to reference signal amplitudes, and producing a timestamp at a time that the preconditioned signal and reference signal amplitudes are equal. The apparatus includes a preconditioner, a reference signal generator and a quantity N of comparators. A comparator of the quantity N of comparators receives the preconditioned signal from the preconditioner, separately receives a reference signal, and produces a digital signal. The preconditioned signal or the analog signal may be reconstructed from the digital representation.

Abstract: A digital pixel sensor architecture has a comparator located within the pixel and a frame memory located outside the pixel. The comparator is used with additional circuitry to perform analog-to-digital conversion. Replacing the analog-to-digital converter and memory of a conventional digital pixel sensor minimizes many issues associated with conventional digital pixel sensors while preserving the architecture's resistance to noise and speed.

Abstract: A signal processing circuit outputs a digital word responsive to incident light, and includes an analog integrated circuit having a first input terminal receiving a first analog signal during a first active period of a first switching signal and a second input terminal receiving a time varying reference signal; an inverter circuit inverting and amplifying an output of the analog integrated circuit responsive to an activated enable signal; and an output circuit generating the digital word. During a second active period of the first switching signal, the first input terminal is coupled to a data line for receiving a second analog signal corresponding to image charges of an image input element. The enable signal is deactivated between end points of the first and second active periods of the first switching signal.

Abstract: There is provided a chopper type voltage comparator for comparing a sampled input voltage with a ramp voltage that is changed with a time, in which a bias voltage is changed according to the ramp voltage, and then the bias voltage comes up to a predetermined voltage value that is able to bring the chopper type voltage comparator into a comparing operation state when the ramp voltage becomes substantially equal to the input voltage. Accordingly, a voltage comparator whose consumption power can be suppressed rather than the prior art and an analog/digital-converter using the same can be provided.

Abstract: The present invention relates to a picture display using CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a CMOS image sensor having a testing circuit embedded therein and a method for verifying operation of the CMOS image sensor using the testing circuit. The CMOS image sensor according to the present invention includes a control/interface unit for controlling its operation sensor using a state machine and for interfacing the CMOS image sensor with an external system; a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light; a converter for converting the analogue signals into digital signals to be processed in a digital logic circuit; and a testing circuit for verifying operations of the converter and the control/interface unit, by controlling the converter.

Abstract: A machine used for analog-to-digital (A/D) conversion in which an analog input is compared to a piece-wise non-linear analog reference waveform. A digital count is recorded indicative of when the difference between the two becomes zero. Alternative mappings such a linear correspondence between analog input values and digital output values can be implemented via digital processing of each recorded count. The invention is particularly intended for use with sinusoidal reference waveforms to enable low-cost, high-precision A/D conversion at speeds much higher than are possible with piece-wise linear analog reference waveforms such as saw-tooth or triangle waveforms. The invention can be implemented with multiple A/D converters sharing a piece-wise non-linear analog reference waveform, with conversion cycles using increasing or decreasing waveform segments, and with compensation of comparator-induced errors.

Abstract: An A/D converter in which a thermometer code representing an increase in analog input voltage values is asynchronously derived using a chain of buffers, the thermometer code being translated using a binary code into a ramp voltage by a D/A converter and frozen when the ramp voltage equals the amplitude of a selected analog voltage being digitized.

Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level Ss to corresponding digital representations at several sub-conversion times t=T2>T1, t=T3>T2, . . . t=TM>TM−1, where TM≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than Ss at time t=T.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: The present invention relates to a circuit configuration with an A/D converter, especially for applications that are critical in terms of safety, which is especially characterized by a ramp signal generator for generating a ramp voltage that is delivered to the input of the A/D converter, and a test circuit for activating a test cycle which comprises a first run of the ramp, by which a reference measurement of the ramp signal generator is carried out for compensating component tolerances, and comprises a second run of the ramp where an error signal is output when the value that is calculated for a transmission characteristic of the A/D converter lies outside a predetermined tolerance range of the measured value of the transmission characteristic.

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level Ss to corresponding digital representations at several sub-conversion times t=T2>T1t=T3>T2, . . . t=TM>TM−1, where TM≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than Ss at time t=T.

Abstract: A method of simultaneously providing A/D conversion and multiplication in a Bit-Serial ADCs and single slope ADCs. A bit serial ADC uses a RAMP signal and a BITX signal input to a comparator and 1-bit latch, respectively. When RAMP exceeds an analog input value, the comparator triggers the latch to output the value of BITX. The bits are output serially. The RAMP signal has a staircase shape with voltage levels and voltage steps. In the present invention, multiplication by two coefficients is possible. One coefficient is determined by properly designing RAMP, and the other coefficient is determined by properly designing BITX. Multiplication via RAMP is accomplished by changing the voltage levels by a factor of 1/X, where X is the multiplying coefficient (i.e., multiplication by a factor of 0.5 is accomplished by doubling the voltage of the voltage levels). Multiplication via BITX is accomplished by slowing the frequency of BITX by a factor of X.

Abstract: A single slope A/D converter utilizes a sub-nanosecond time digitizer to achieve increased conversion rates independent of a high frequency clock, and so is capable of being implemented in diverse applications. High conversion rates ranging from about 3 MHz to about 12 MHz and higher may be implemented on integrated circuits without using a high frequency clock.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: An image sensor (10) which can be fabricated using conventional CMOS processes uses a comparator circuit (18) at each pixel (14) having a first input coupled to a photodetector (16) and a second input coupled to a ramp signal generator (30, 32). The ramp signal generator (30, 32) is comprised of a counter (32) and a D/A conversion circuit (30) with the analog output of the D/A conversion circuit (30) forming an analog ramp input to the comparator circuit (18). A counter circuit (32) can be used to drive the digital side of the D/A conversion circuit (30) and configured to count from 0 to 2n−1 to 0, N being the resolution of the photodetector (16). The output of the D/A conversion circuit (30) causes comparator circuit (18) to flip when the ramp signal is equal to the value of the output from the photodetector (16). The comparator circuit (18), in turn, drives a load signal to a register (38) which stores the counter values 32 from pixel (14) at the instant the comparator 18 flips.

Abstract: An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

Abstract: A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

Abstract: A method for acquiring measured values in electronic analog circuits having at least one measurement point, in particular safety-relevant circuits for passenger protection systems in motor vehicles. The electrical potentials generated at the measurement points are each compared as measured quantities with a ramp voltage that rises in steps, where the number of steps required to reach the voltage value of the measured quantity at the respective measurement point is provided as a unit of measurement that is proportional to the measured quantity. This allows the comparison of all measured quantities with the ramp voltage to be performed simultaneously, the ramp voltage being selected to cover the entire range of measurement.

Abstract: A low-cost circuit processes, with high precision, the output signals of a pointing stick used for controlling a cursor on a computer display screen. A two-stage method of high precision moderate range analog-to-digital (A/D) conversion is combined with a known method of A/D conversion by sweeping a reference voltage across the range of the voltage to be measured at a known rate and noting the time of coincidence. Operational amplifiers of moderate quality are used in an open-loop mode, so that the operational amplifier inputs are high impedance. In order to get sufficient isolation from power supply noise and variations, the analog circuitry is isolated from the supply voltage while measurements are being made.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.