Abstract: The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.

Abstract: A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract: When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

Abstract: A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.

Abstract: An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract: An example ramp analog-to-digital converter (ADC) for generating at least one bit of a digital signal includes a modified ramp signal generator, a comparator, and a control circuit. The modified ramp signal generator receives a ramp signal and generates a modified ramp signal in response thereto. The comparator compares an analog input with the modified ramp signal. The control circuit controls the modified ramp signal generator, such that the analog input is converted a variable M number of times for each period of the ramp signal. The number M is dependent on a magnitude of the analog input. In one example, the number M is greater for analog inputs of a lower magnitude, such that the analog inputs of the lower magnitude are converted more times than analog inputs of a higher magnitude.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.

Abstract: One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.

Abstract: A comparator includes a first amplifier and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors serve as a comparison part that receives a reference voltage, a signal level of which changes with a slope, at a gate of one of the differential-pair transistors, receives an input signal at a gate of the other of the differential-pair transistors, and compares the reference voltage with a potential of the input signal. The level holding part holds a level of the first output node such that the other transistor having an output part thereof connected to the first output node out of the differential-pair transistors of the first amplifier does not fall into a level at which a saturated operation condition is not satisfied.

Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.

Abstract: An image sensor has a pixel array and an input circuit. The input circuit includes a first input, a second input and two coupling capacitors. The first input receives an analog signal from a pixel of the pixel array which has a first level during a first calibration period and a second level during a second read period. The second input receives a reference ramp signal. A comparator circuit compares the ramp signal and the analog signal. The analog signal and the ramp signal are constantly read onto the coupling capacitors during both the first calibration period and the second read period. The ramp circuit begins providing the ramp signal during the second read period so as to determine the change in magnitude of the analog signal between the first calibration period and the second read period, the ramp circuit also begins providing the ramp signal during the first calibration period so as to compensate for any delay in the ramp circuit providing the ramp signal during the second read period.

Abstract: A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.

Abstract: A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.

Abstract: An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal.

Abstract: An analog-to-digital converter converts an analog signal into a digital signal by measuring a time period until a magnitude relation between a voltage level of a reference signal that changes along with time and a voltage level of the analog signal is inverted. The converter comprises a holding unit which holds, as a voltage level that is an analog value, an offset value of the analog-to-digital converter upon analog-to-digital converting a reference voltage level by the analog-to-digital converter, wherein the offset value of the analog-to-digital converter is corrected by changing the voltage level of the analog signal by the voltage level of the offset value held by the holding unit.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: Provided are a ramp wave generation circuit and a solid-state imaging device in which a pulse output unit includes a delay part including a plurality of delay units that delay and output an input signal, and a delay control part that controls a delay time by which the delay unit delays the signal, and outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units, a time difference between timings at which the logic states of the respective signals are changed being a time corresponding to the delay time.

Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.

Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.

Abstract: An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

Abstract: A ramp generator includes a digital-to-analog converter (DAC), a sampling capacitor, an integrator circuit, a polarity reversing switch selectively coupling first and second outputs of the DAC to a first side of the sampling capacitor, a first switch coupling a second side of the sampling capacitor to a reference voltage source, and a second switch coupling the second side of the sampling capacitor to an input of the integrator circuit.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: A dual-mode comparator may include an object voltage input unit that generates a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage, a current mirror unit that performs a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal, a bias unit that generates a bias current corresponding to a sum of the first current and the second current, and a mode switching unit that controls the current mirror unit to have a first structure in an auto-zero mode and that controls the current mirror unit to have a second structure in a comparison mode.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: A solid-state imaging apparatus includes a low-order latch circuit, a state variation detection circuit, and an encode signal latch circuit. The state variation detection circuit sequentially compares pulse signals output from two delay elements of a plurality of delay elements among pulse signals latched by the low-order latch circuit and outputs a state variation detection signal when states of the two pulse signals are different. The encode signal latch circuit latches an encode signal when the encode signal having a state corresponding to a delay element outputting a pulse signal input to the state variation detection circuit is input and the state variation detection signal is input.

Abstract: An analog-to-digital converter (ADC) includes a plurality of single slope ADCs, a ramp generator, and digital output circuitry. Each single slope ADC includes an analog input operable to receive an analog input signal, a ramp input operable to receive an analog ramp signal, a comparator operable to compare the analog input signal to the analog ramp signal, and an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs are operable to receive analog ramp signals that are out of phase with each other. The ramp generator that is operable to generate analog ramp signals for each of the plurality of single slope ADCs. The digital output circuitry is operable to receive outputs from each of the plurality of single slope ADCs and to produce a digital representation of the analog input signal based thereupon.

Abstract: A solid-state imaging device and an imaging apparatus are provided. The solid-state imaging device performs an AD conversion in a column parallel for an analog pixel signal outputted from each of pixels disposed in a two-dimensional matrix shape. The solid-state imaging device includes: an AD conversion unit including a plurality of pixel signal accumulating units; a first switching unit for disconnecting parallel connection of a second pixel signal accumulating unit other than a first pixel signal accumulating unit which is one of the plurality of pixel signal accumulating units; and a second switching unit for connecting the second pixel signal accumulating unit to a pixel signal line of a second pixel adjacent to the first pixel in a row direction, when parallel connection of the second pixel signal accumulating unit is disconnected by the first switching unit.

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Abstract: Provided is an analog-to-digital (A/D) converter that may be used in an image sensor and a ramp signal generator that is used in an A/D converter. The ramp signal generator may generate a ramp signal and a reference voltage signal that include noise that has same noise characteristics that are input into the ramp signal, such that the signal to noise ratio (SNR) is improved and the image quality is also improved.

Abstract: An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: Aspects of the invention provide a continuous ramp generator design and its calibration for CMOS image sensors using single-ramp ADCs. An embodiment of the invention comprises controlling a coarse gain, integer gain, and fine gain of the analog-to-digital converter. Gain of the analog-to-digital converter may be calibrated by tuning the integer gain based on reference voltages converted to equivalent digital values.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

Abstract: An ADC includes an analog signal input port for receiving analog signals, a reference voltage generation circuit for producing a reference voltage, a controllable switch, a control unit including a counter, an integral circuit, and a comparison circuit. The control unit outputs an on or off signal to turn on or turn off the controllable switch, the counter starts to count when the control unit outputs the off signal. The integral circuit executes an integral action to integrate the reference voltage and output a voltage enhanced gradually when the controllable switch is turned off. The comparison circuit outputs an interrupt signal to cause the counter to stop counting when comparing the voltage output by the integral circuit is higher than the voltage of the analog signals. The control unit determines a digital value corresponding to the analog signals according to a count value of counted by the counter.

Abstract: The present invention is related to an analog to digital converter circuit. The circuit comprises at least one input node for applying an analog input voltage signal (Vin), means for sampling said analog input voltage signal, a first array of capacitors arranged for receiving the sampled analog input voltage signal, a digital delay line connected to the first array of capacitors and arranged for being enabled by a clock generator and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator arranged for comparing a converted signal with a reference voltage (Vref), said converted signal being a version of said sampled analog input voltage converted according to said staircase or slope function, and for generating a stop signal based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.

Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.

Abstract: Certain embodiments provide an ADC includes a comparator, a binary counter and a control circuit. The comparator compares a first analog signal voltage with a first reference voltage, and compares a second analog signal voltage with a second reference voltage. The binary counter counts up the clock signal for a first period until the first reference voltage becomes equal to the first analog signal after the comparator starts to compare the first reference voltage with the first analog signal voltage, and inverts a logic level of the count output having a plurality of bits after the first period elapses. The binary counter counts up the clock signal for a second period until the second reference voltage becomes equal to a second analog signal after the comparator starts to compare the second reference voltage with the second analog signal voltage.

Abstract: There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.

Abstract: A multichannel digitizer and method of digitizing are provided. One digitizer includes an analog to digital convertor (ADC) having a plurality of channels receiving input analog signals; an operational amplifier in each channel and a comparator connected to the operational amplifier. The ADC further includes a logic circuit in each channel connected to the comparator and configured to generate an output based on a comparator signal received from the comparator. The ADC also includes a ramp generator connected to the plurality of channels and configured to provide a time varying reference signal.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.