Abstract: A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream.

Abstract: A method and apparatus for high speed decoding of a 20 bit wide data into 16-bit wide data in which the first ten bits and the lower ten bits are decoded simultaneously to ensure complete decoding and where the decoding of the second ten bits is dependent upon the running disparity of the first ten bits, the second ten bits are decoded twice, one assuming the decoded first ten bits will have a positive running disparity, and a second time assuming that the decoded first ten bits will have a negative running disparity.

Abstract: A digital data modulation system having, a separator for separating a consecutive binary data sequence to four-bit code-words, a four-to-nine ([4,9]) converter for converting the four-bit code-words into nine-bit modulated code-words and a code selector for selecting a code among nine-bit code-words containing minimum three bits of "0" between a preceeding bit of "1" and its following bit of "1" so that there should not be less than two consecutive bits of "0" between a selecting code and a modulated code-word which is to be converted later by the [4,9] converter.

Abstract: A method and apparatus for encoding, detecting and decoding data in a Partial Response (PR) class-IV magnetic recording storage system that does not require the conventional interleave constraint and therefore minimizes the path memory and latency of a sequence detector such as the Maximum Likelihood (ML) Viterbi detector. Rather than encoding an interleave constraint to ensure merging of path memories in the detector, the parity of the encoded codewords is utilized in selecting tile correct sequence out of the unmerged paths. The encoding technique encodes the data using two groups of codewords; the first group causes the path memories of the sequence detector to merge into one survivor sequence and the second group causes the path memories to merge into two survivor sequences different in only one bit and thus different in parity. The correct survivor sequence is thereby selected according to the parity of the codeword being detected.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: A system and method for encoding and decoding binary data for serial transmission over a physical medium provides a highly efficient and less complex coding scheme while guaranteeing clocking information and guaranteeing an NRZ(I)-disparity of no greater than one per five-bit word. The system and method of the present invention comprise a 4/5 encoder which enables each nibble to be encoded and decoded independently from one another. The coding system and method of the present invention guarantees an NRZ(I)-disparity having a magnitude of no greater than one for any word after NRZ(I) while providing at least one word with "NRZ(I) comma" property.

Abstract: To improve the reliability of reproduction by performing signal processing so that substantially (almost) all DC is eliminated when digital data is recorded on a recording medium such as a magneto-optical disk. When data is recorded on a recording medium such as a magneto-optical disk, generally the digital data is modulated and encoded before being recorded, but sometimes the modulation code is not DC free due to a recording channel code of an NRZI system, etc. According to the present invention, data is divided into parts each having a certain constant length so as to prevent the DC component from building up.

Abstract: An apparatus and method for transmitting an 8-bit binary format data word as a 6-trit ternary code word includes an encoder, a decoder, and a code assignment that produce, for each 8-bit data word value, an unique 6-trit ternary code word that is particularly optimized for transmission over twisted-pair cable. The logic circuitry of the invention is optimized to accomplish the translation using a small number of combinatorial logic gates. The present invention thus has advantages in size, speed and performance over other possible means for encoding an 8 bit data word to a 6 trit code word.

Abstract: Codewords with CDS=0 are mapped in corresponding relationship to datawords, and codewords with CDS>0 and codewords with CDS<0 are paired together and mapped in corresponding relationship to the remaining datawords, and further, codewords with CDS.noteq.0, left unmapped, are mapped in corresponding relationship to the datawords to which the codewords with CDS=0 have been mapped, thus reducing the probability of occurrence of codewords with large DSV in absolute value terms and thereby achieving a further suppression of low-frequency components. Based on the least significant bit of the codeword corresponding to the last dataword and on the current and next datawords, a codeword corresponding to the current dataword is selected, thus realizing high-density recording with good overwrite characteristics.

Abstract: A modulating method, a modulating device and a demodulating device, in which it is possible to improve the digital sum value (DSV) of the coded information, modulated for transmission or recording on the recording medium, are disclosed. An encoding circuit 11 translates a sequence of input data into a sequence of coded data suitable for transmission. A pattern generating circuit 12 generates a pattern of a pre-set length at a pre-set interval inversely proportionate to the low-range cut-off frequency of the modulated coded data. A pattern inserting circuit 13 inserts the patterns into the sequence of coded data A at the pre-set interval. A modulating circuit 14 NRZI modulates the pattern-interlaced sequence of the coded data B and outputs the resulting sequence. A timing control circuit 15 controls the pattern inserting circuit 13 an so forth.

Abstract: Apparatus for decoding an input digital signal by replacing successive n-bit groups of the input digital signal with respective ones from an ensemble of m-bit data words, each m-bit data word having an associated n-bit code word, where n is greater than m, comprises: means for determining the Hamming distance between an n-bit group of the input digital signal and each of the n-bit code words associated with the ensemble of m-bit data words; and means for replacing that n-bit group of the input digital signal with an m-bit data word from the ensemble of m-bit data words for which the Hamming distance between the n-bit code word associated with that m-bit data word and that n-bit group is the lowest.

Abstract: A modulator suppressing a low-frequency component of a recording waveform while limiting maximum and minimum recording wavelengths, comprising a margin bit generating circuit for generating a most suitable margin bit pattern based on a signal concerning a final recording waveform level of each of n channel bit patterns to be put before a margin bit pattern to be inhibited, control signals concerning a polarity of a cumulative digital sum variation, a control signal coming from a digital sum variation integrating circuit to switch between gains by detecting a magnitude of an absolute value of the digital sum variation, and a signal concerning the cumulative digital sum variation of each of the n channel bit patterns to be put after the above-mentioned margin bit pattern.

Abstract: A system and method that reduces the simultaneous switching noise of outputs and the processing delays caused by inductance by using an encoding scheme that results in a net signaling current of substantially zero at each cycle time for the fast parallel switching networks of digital integrated circuit chips and that provides multiple types of error detection.

Abstract: The present invention provides an encoding and decoding apparatus used for the compression and expansion of data. A state machine is provided having a plurality of states. Each state has at least one transition pair. Each element of the transition pair comprises zero or more bits representative of the compact code to be output and the identification of the next state to proceed to. The transition pair reflects an output for a yes and no response associated with the probability of the data to be compacted and whether the data falls within that probability.

Abstract: In a data modulation method, m-bit data is modulated to n-bit data (n.gtoreq.m) having fewer direct current and low frequency components. A dispersion of the digital sum variation of code weights can be reduced, a direct current component is reduced and an error rate can be further reduced by selecting a plurality of modulation tables constituting the combination of one or more sub-groups of modulation data obtained by dividing a group of modulation data by a code weight having the same value based on the digital sum variation of the code weights accumulated until a time at which m-bit data is converted to n-bit code and converting next m-bit data continuously to present m-bit data to n-bit code by using the modulation tables.

Abstract: In a method for limiting the bandwidth of a selected binary signal (B), there is produced a modulated digital signal (D) which presents a continuous series of changes in signal level. The two occurrent logic states (1,0) are each represented by a respective symmetrical pulse train, wherein the frequencies f1, f2 of the pulse trains are mutually different. The higher frequency f2 is equal to the number of bits transmitted each second divided by two herz. The transition between the two pulse trains is arranged so that the integral of the resultant signal will be zero within the duration of three of four data bits. In a preferred embodiment of a coder and decoder each include a code word counter which, together with a combinatory logic circuit (code word table) activates or is activated by a shift register for transmitting or receiving respectively the modulated digital signal.

Abstract: A method of recording data in a recording medium is performed by using an RLL (Run Length Limited) Code represented by (d,k,m,n)=(1,7,2,3). When it is assumed that X is an indeterminate bit which is determined by the data, a one-byte resync signal with a pattern represented by "X01000000001" is periodically inserted into the data. Then, the data into which the resync signal is inserted is recorded on the recording medium. A method of recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording is performed by using an RLL code represented by (d,k,m,n)=(1,7,2,3). When it is assumed that X is an indeterminate bit which is determined by the data, one of one-byte resync signals represented by patterns "X01000000001" and "X01000000101" is selected such that a DSV (Digital Sum Value) of a coded signal is decreased. The selected resync signal is periodically inserted into the data. Then, the data into which the resync signal is inserted is recorded on the recording medium.

Abstract: An encoding apparatus for constructing an asymptotically optimal coding scheme for second order DC-constrained channels is disclosed. A first encoding function block breaks an input data stream into equal sized vectors of length m bits. A sign designation bit is then attached to each vector to make vectors of length m+1 bits. r redundancy bits are added to each vector, to produce balanced vectors of length m+1+r bits. A first moment is calculated for each vector. A determination is made whether the addition of this vector's first moment value to an accumulated running sum of all the vectors' first moments effectively drives the running sum in the direction of zero. If is does then that vector's first moment is added to the accumulated running sum of first moments and the vector is added to the output array.

Abstract: A modulating method and apparatus and a demodulating method and apparatus in which a variable length code (d, k;m, n;r) which can provide a greater minimum reversal distance to allow recording of a higher density than ever is provided. According to the modulating method and apparatus, digital data of a basic data length of m bits is modulated into a variable length code (d, k;m, n;r) of a basic code length of n bits, and where the distance between adjacent ones of the digital data is represented by T, the minimum reversal distance of the variable length code is equal to or greater than 2.0 T and the minimum length of a run of a same symbol is equal to or greater than 4.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords," and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and systematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: A method and apparatus for using a modified 8B/10B system for transmitting 10 bit wide data packets in 12 bit code in which 5B/6B encoder/decoders separate the 10 bit wide data into two 5 bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12 bit code words to provide reliable byte boundaries.

Abstract: A circuit for calculating a DC value for use in a code conversion apparatus of a recording and reproducing system includes a first storing element, second storing element, parallel to serial convertor, selecting circuit and a DC value calculating circuit.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: An encoder separates an input digital signal including m bits into the first group and the second group, and encodes each piece of data in the first group to a single code word including n bits in one-to-one correspondence and encodes each piece of data in the second group to two code words each including n bits in one-to-two correspondence. A CDS calculator calculates a CDS value for each of the words output from the encoder. A DSV calculator calculates the accumulated DSV value of the individual words output from the encoder. When the two-n-bit code words are output from the encoder, a code selector selects that one of the code words which decreases the next accumulated DSV value to be calculated by the DSV calculator, according to the CDS value from the CDS calculator and the accumulated DSV value from the DSV calculator.

Abstract: A plurality of (n-p)-bit non-correlation data having no correlation between data each are added with a common p-bit data to thereby obtain a plurality of n-bit data having data correlation. The plurality of n-bit correlation data are processed using data correlation therebetween so that even a data train having no correlation can be processed effectively. A plurality of m-bit non-correlation data having no correlation between data are separated into a plurality of blocks including (n-p)-bit data and n-bit data. A p bit among the separated n-bit data is added to the separated (n-p)-bit data to thereby obtain a plurality of n-bit data having data correlation, in both cases n and m being an integer more than 2 and p is an integer smaller than n.

Abstract: A modulating method and apparatus and a demodulating method and apparatus wherein high density recording can be achieved and a dc component can be controlled with a variable length channel code are disclosed. Recording data are divided into a predetermined plurality of blocks, and those of the recording data at a portion other than a boundary portion of each of the blocks are coded referring to a table of a first ROM so that data of m bits may be converted into a code of n bits. The remaining data at the boundary portion of each block are converted into a code referring to another table of second ROM so that data of m bits may be converted into a code of n bits. Further, a code of n bits for minimizing a dc component is produced referring to a third table of a further ROM and is added to the code generated by the first and second ROMs.

Abstract: A modulator circuit is constructed such that an input signal is code converted, after an error code correction code is added thereto, into a channel bit pattern suitable for characteristics of a recording and reproducing system for recording and reproduction of digital data. Margin bits are inserted between adjacent channel bit patterns in order to limit the lengths of the channel bit patterns. One or ones of a plurality of predetermined margin bit patterns which are to be inhibited from being inserted between particular two channel bit patterns are determined in accordance with a predetermined algorithm referring to the second last, the last and the present channel bit patterns and the last margin bit pattern. The output of an integrating circuit for measuring a digital sum variation of a channel bit pattern signal and a channel bit pattern is provided with a saturation characteristic so that the output may not diverge.

Abstract: Digital data recording/reproducing apparatus which uses a simple coding scheme for DC channel codes of the form M/N where M=N-1 and M and N are positive integers.

Abstract: In digital data transmission and storage, binary data strings are encoded into symbols from a quaternary alphabet by a specific inventive use of finite-state machines. The novel, high-rate quaternary codes offer spectral shaping properties together with a significant increase in noise margin when used on channels which lend themselves to partial-response shaping. In principle, the encoding occurs in three steps: a u-state transition diagram generates quaternary symbols whose running digital sum assumes values from a given set; the u-state transition diagram is converted into a v-state machine, each of the v states being associated with a number of transitions sufficient to encode the input data bytes into output code words; finally, the v-state machine is switched into a next state depending on its current state and the last encoded input data byte.

Abstract: A secondary modulation method which replaces any bit excluding the leading bit of consecutive five or more ones in an odd-numbered bit pattern of a train of RLL-modulated data, with a zero to provide a modulated bit pattern having no consecutive zeros. It is therefore possible to form marks of a given width on a disk without any mark edge shift, thus preventing the level of the waveform of a signal read from a disk from falling below the slice level at the position where the waveform of the read signal should show "1". This can ensure the proper data reproduction.

Abstract: An 8B/10B encoder which provides an output of one of a pair of opposite disparity non-complementary 8B/10B command code outputs responsive to RD and selected command inputs.

Abstract: A plurality of first codeword pairs each including a 15-bit codeword of which CDS is equal to +3 and a 15-bit codeword of which CDS is equal to -1 and a plurality of second code pairs each including a 15-bit codeword of which CDS is equal to +1 and a 15-bit codeword of which CDS is equal to -3 are produced. One of the plurality of first code pairs and one of the plurality of second code pairs are assigned to each 8-bit data word, and one of the first and second code pairs assigned to each 8-bit data word is selected so that the number of continuous identical bits in a 15-bit codeword sequence is not less than 2 and not more than 8. One of two 15-bit codewords included in the selected code pair is selected so that DSV at the last bit of each 15-bit codeword periodically varies.

Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved.

Abstract: A disparity detection circuit used in a signal decoder which decodes a 4-bit signal into an original 2-bit main signal and 1-bit service signal, from which the 4-bit signal is coded according to a coding rule which stipulates that an original 2-bit main signal and 1-bit service signal should be coded into a 4-bit signal with 1 additional bit added and with pre-determined disparity carrying, determines whether the 4-bit signal conforms to the coding rule and detects the disparity of the 4-bit signal which is determined as conforming to the coding rule.

Abstract: For reducing the d.c. component of a digital signal in which a good many data words are put together in data blocks each having the same number of words, a supplementary word is derived and is transmitted or stored along with the data words. The bit mix of the supplementary word contains information for shifting the word bit-mix range, defined in accordance with the d.c. component of various words of the data words in the data block. The bit-mix value of the supplementary word is derived by evaluation of the weighting of ASE-coded data words in the data block, this being done in a manner dependent on the standard deviation and an expected value or center of gravity of the data block. A difference value determined with respect to the center of gravity and the value of a middle level value of a data word represents the value of the supplementary word with which, by the use of the modulo-2 addition the digital signal is shifted in bit-mix value range.

Abstract: A running disparity circuit for 8B/10B decoding which reduces power consumption and substantially reduces the number of gates and the required silicon area by employing a combination of state type devices and combinatorial logic instead of combinatorial devices exclusively.

Abstract: High speed telecommunications systems are disclosed which use a novel line coding scheme for better performance. The line code according to the scheme be can used to produce a block code of arbitrary length. It bounds the minimum number of transitions in a block, and the dc balance of the code. The overhead required is 2 bits if framing is not included and 3 bits if it is. A lookup table is not required to implement the code, thus it remains efficient for longer block lengths. The algorithm required to encode and decode the data can be implemented in serial at the transmission rate or in parallel at the block rate. The coding scheme results in a significant reduction in hardware components of the communication system.

Abstract: A digital modulation system is disclosed in which a string of input data is divided at intervals of 8 bits and the resulting 8-bit data words are converted into 16-bit modulated digital code data words. Code conversion is made so that the resulting 16-bit modulation code words have two or more consective digits between the 2nd and the 15th bits, five or less consecutive digits between the 1st and the 16th bits, four or less consecutive digits between the 13th and the 16th bits, the absolute value of the CDS of all 16 bits in each modulation code block is not more than 4 and the absolute value of the DSV from the leading bit to an arbitrary bit in each modulation code block is not more than 5. Also, the number of consecutive digits in any portion of the digital data is not less than 2 and not more than 5 and the absolute value of the DSV is not more than 3 from the beginning of the coded data stream to any point therein. An error rate more favorable than the M.sup.

Abstract: A code modulation system wherein an 8-bit input is converted to a 14-bit code by creating modulated data code tables and associating a given 8-bit input with a particular table based on the Digital Sum Variation value, the Non-Return to Zero Inverted waveform polarity, and the end-bit value of the preceding 14-bit modulated code.

Abstract: In an information data recording and reproducing device which can record and reproduce input information data accurately, an error correction code of the product sign format is added to the input information data to form coded data. The coded data are then NRZI converted and recorded onto a recording medium together with identification data of a predetermined data pattern. Error detecting and correcting are performed on data reproduced from the recording medium so as to obtain the data recorded on the recording medium.

Abstract: A data converting apparatus inserts DC control bits in an input data series to generate a redundant data series. This apparatus determines the value of the DC control bits in such a way as to minimize the DC component of an output code series which is obtained by subjecting the redundant data series to code conversion. The apparatus performs code conversion after inserting the determined DC control bits.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords, " and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and sytematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: In a data conversion method of converting source data of M bit unit to be recorded on a recording medium into conversion data of N (>M) bit unit, n, which is a number of inter-symbol interferences permitted in a transmission path, continuous codes in the codes of the conversion data are weighted with a weighting distribution decreasing linearly from a distribution center, the weighted n continuous codes are sequentially added to form the intermediate series, and then such conversion data that the sum of absolute values of differences of codes between the intermediate series (i.e., the code length) is more than a predetermined number of times as large as a reference value of the weighting coefficient is selected as a modulation code, whereby the pattern length between the code patterns can be made larger to thereby improve the recording density remarkably with using the present recording medium and recording and/or reproducing apparatus.

Abstract: An apparatus for processing an input data signal has a generator providing a plurality of pseudo-random signals each of which scrambles the input data signal for providing a plurality of respective scrambled outputs, a detector by which a DC component, such as, a run-length or a digital sum value, is detected for each of the scrambled outputs, and a selector responsive to the detector for selecting one of the scrambled outputs, for example, having a minimum run-length or a digital sum value closest to zero. An identifying signal identifying the pseudo-random signal used in scrambling the selected scrambled output is then transmitted with the latter, for example, by recording on a magnetic tape. When the transmitted signal is received or reproduced, the identifying signal included with it is detected, and the received signal is descrambled with a pseudo-random signal corresponding to the detected identifying signal.

Abstract: A method for coding a binary data string for a partial-response channel having a transfer function with a spectral null at zero frequency to provide a coding rate 8/10 and an output which is invariant to 180-degree phase shifts in the channel output signal. A finite-state machine is created having two pairs of states and a plurality of codewords each corresponding to a respective binary data byte. The binary data string is encoded by said machine into a string of binary codewords having a power spectrum value of zero for a frequency of zero. In response to each successive data byte in the binary data string, there is generated one of two complementary codewords from the one of that pair of the states designated by said machine as corresponding to the data byte for the then current state of the machine.

Abstract: A signal having a non-uniform probability density is processed for transmission in pulse code modulated form. The signal is quantized using conventional methods and the quantized signal is then coded using a non-sequential coding scheme in which binary codewords for the quantization levels are chosen in accordance with the probability of the quantization levels and number of ON bits in the codeword. Quantization levels of higher probability are assigned codewords with fewer ON bits. An optical network includes a central station having a master clock source. The central station is connected to a remote station including a signal processor arranged to process a signal for return transmission to the central station using minimum power codeword assignment.

Abstract: In a digital data modulation circuit, a digital data block formed of k words, each of which includes m-bit binary data, is input to an error-correcting coding circuit which adds (n-k) check words to the input data block. The error-correcting coded data block is supplied to an arithmetic operation circuit, which calculates the number of "1" bits and the number of "0" bits to be included in the coded data block output from the error-correcting coding circuit so that the difference between the number of "0" bits and the number of "1" bits included in the coded data blocks which have been output from the error-correcting coding circuit approximates 0 and calculates one control word corresponding to the calculated number. The coded data block output from the error correcting coding circuit is supplied to a modulo-two adder which adds the control word to every word belonging to the coded data block.

Abstract: A digital modulator converts M-bit data words to N-bit code words (N>M) each containing a specific number of bits `1`. The specific number is one of a plurality of predetermined numbers which are different by at least 3 from one another. A specific data word may be converted to either one of two code words having different numbers of bits `1` from each other so as to reduce DC components of a channel code constituted by the code words.

Abstract: A signal conversion circuit is used to convert a parallel signal to a serial signal and comprises a parallel input/serial output type of shift register having input terminals corresponding in number to at least n+k bits (n and k: integer), an inverting circuit and a timing circuit. The n-bit input parallel signal is applied to n successive input terminals of the shift register and k bit of the n-bit parallel signal is inverted by the inverting circuit to be applied to the remaining k input terminal of the shift register. The (n+k)-bit parallel signal loaded into the shift register is serially output at a predetermined rate by the timing circuit to provide a serial signal.

Abstract: In a variable-length coding/decoding device, an r.multidot.m-bit data word is converted into an r.multidot.n-bit code word, where r is an integer having the relationship 1.ltoreq.r.ltoreq.r.sub.max, a basic data word length consists of a m bits (m is a positive integer), and a basic code word length consists of n bits (n is a positive integer), and each of data words of a variable-length run-length-limited code limiting the run number of bits of a first value (e.g., "o") between successive bits of a second value (e.g., "1") in a binary-coded bit string generated by concatenation of code words after the conversion to a value no smaller than d and no larger than k into a code word corresponding to thereto. At that time, an input data word is once coded into an r.sub.max .multidot.q-bit (q is a positive integer) code word, and then divided into r.sub.max blocks each consisting of q bits, and a code word in each of the blocks is coded to obtain a variable-length run-length-limited code word.