Abstract: According to one embodiment of the present invention a number of input bits are received in a first encoder circuit and the input bits are encoded to generate encoded bits in the first encoder circuit. An input disparity bit is generated from the encoded bits, and the input bits and the input disparity bit are received in a second encoder circuit. The input bits are then encoded into a number of output bits based on the input disparity bit in the second encoder circuit. According to another embodiment of the present invention an encoder system includes a first encoder circuit having a number of inputs coupled to receive a number of input signals, to encode the input signals, and to generate a disparity signal at an output based on the encoded input signals.

Abstract: The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.

Abstract: Encoding and decoding systems and methods for digital data in 24 bit sequences. An encoder generates state variables as a function of four or fewer bits of the 24 bit sequence, and encodes the sequence into 11 and 14 bit codewords. After transmission, the 11 bit and 14 bit codewords are decoded using recovered state variables. The encoding places a run length limit (RLL) of k=7 on a 25 bit codeword comprised of the 11 and 14 bit codewords to limit runs of zeros. Each of the 11 bit and 14 bit codewords are preferably also encoded with a run length limit of interleaved bits is i=7. The encoding and decoding systems and methods can be applied to a magnetic disc drive.

Abstract: An allocating method of allocating a run length limited (RLL) code having enhanced direct current (DC) suppression capability, modulation and demodulation methods, and a demodulation apparatus are provided. In order to control DC suppression, a pair of code groups having suppression controlling capability are allocated, and a (1, 8, 8, 12) code having DC suppression capability, in which a code word of the pair of code groups has the sign of code word sum value (CSV) parameter, which represent DC value in a code word, and the characteristic of an INV parameter, which predicts the transition direction of digital sum value (DSV) of the succeeding code word, both opposite to those of the code word which belongs to the other code group and corresponds to the same source code, is used and is appropriate to high-density optical disc system.

Abstract: A method of inhibiting copying of digital data. In a first embodiment, a sequence of symbols is added to original data, the sequence of symbols selected to encode into channel bits having a large accumulated digital sum variance. The sequence of symbols is then encoded by a special encoder that generates special channel bits that don't have a large accumulated digital sum variance. The special channel bits may be unambiguously decoded, but the resulting decoded symbol sequence will likely be reencoded into channel bits having a large accumulated digital sum variance. In a second embodiment, a single symbol in the sequence of symbols is replaced after error correction symbols have been added. The sequence of symbols with one substituted symbol is encoded into channel bits that don't have a large accumulated digital sum variance.

Abstract: A method of generating a run length limited (RLL) code having improved direct current (DC) suppression capability and modulation and demodulation methods of the generated RLL code. According to the method of generating the RLL codes, code words that satisfy a (d, k) run length constraint are generated.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal. The device comprises a merging unit (4′) for merging a 1-bit merging word at equidistant positions in the serial datastream of the binary source signal, so as to obtain a composite binary source signal. A shuffling step is carried out on the composite binary source signal in a shuffling unit (8′). Next a conversion is carried out in a converter unit (10′), resulting in the channel signal (FIG. 2). Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: An improved DC compensation method for use in conjunction with telephony signalling. The method includes defining a frame that includes at least two n-bit codewords. An unsigned codeword is then identified within the frame by applying a rule to the codewords in the defined frame. Next, a sign bit is appended to the unsigned codeword, thereby producing a DC compensating codeword. The sign bit is selected based upon a weighting function of the linear values associated with previously transmitted codewords. The remaining unsigned codewords in the frame are assigned sign bits from user data.

Abstract: A storage system employs a method for encoding a sequence of input data blocks into a sequence of codewords. Each input data block includes a first predetermined number of bits (the data block length). Each codeword includes a second predetermined number of bits (the codeword length). The code rate, i.e., the ratio of the first number to the second number, is greater than ¾. The method is performed in a sampled-data channel in a storage system; and the channel includes a circuit the performance of which is adversely affected by an excessive run length of bits between occurrences of a predetermined influential pattern. Preferably, the influential pattern is a two-bit sequence of adjacent 1's, which favorably influences the performance of a timing recovery circuit. The method includes receiving the sequence of input data blocks and generating the sequence of codewords responsive to the received sequence of input data blocks.

Abstract: Data words are converted to codewords in accordance with a run-length limited (RLL) or maximum transition run (MTR) code in which the codewords are subject to one or more constraints on the number of consecutive like symbols. The data words and codewords are each partitioned into a number of disjoint subsets. Associated with each of the disjoint subsets of data words is a distinct mapping. A given data word is converted to a codeword by applying to the given data word the mapping associated with the subset containing that data word. The mappings are configured to utilize symmetry whenever possible. For example, if Y=&psgr;(X) represents the mapping of a given data word X onto a corresponding codeword Y. then it is preferred that X′ and Y′ representing the words X and Y in reversed order, satisfy the relation Y′=&psgr;(X′).

Abstract: A modulation encoder includes a base conversion circuit that converts a partitioned input data stream from a first base representation in accordance with the size of groups of bits in the partitioned stream into a second base representation. The base conversion circuit includes a circuit to produce intermediate values of the partitioned stream in the second base representation and a residual value logic circuit that performs modulo-arithmetic on intermediate values modulo the second base representation, and a one's complement logic network fed by the residual value logic to produce output code words. A modulation decoder includes a one's complement logic circuit fed by modulation code words to produces residual value words; and a base conversion circuit that converts residual value words from a first base representation into a second base representation to provide original user data.

Abstract: Disclosed is a data processing equipment for conducting the whitener encoding to suppress DC bias in transmit data in a communication device, which has: a multiplexer which parallel-to-serial-converts transmit data and a scrambler which randomizes the converted data; a first counter which counts by +3, +1, −1 or −3 when 2-bit symbol data in the data concerned have a logical level of ‘10’, ‘11’, ‘01’ or ‘00’; a second counter which counts by +3, +1, −1 or −3 when the 2-bit symbol data in all data to be already transmitted have a logical level of ‘10’, ‘11’, ‘01’ or ‘00’; a way to compare a sign bit (MSB of counted weight value) of the first counter with a sign bit (MSB of counted weight value) the second counter; two bit-inversion circuits which invert between ‘1’ and ‘0’ of the data according to the comparison result of the comparing means; two n/2

Abstract: A system and method for encoding a sequence of 32 bit digital data words into a sequence of 33 or more bit codewords having constraints of (d=0, G=9/I=9) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method includes dividing each 32 bit digital data word into three 8-bit bytes and another 8-bit byte, expanding the another 8-bit byte into a 9-bit word, dividing the 9-bit word into three 3-bit subparts, forming three 11-bit intermediate blocks, each comprising one of the three 3-bit subparts and one of the three 8-bit bytes, encoding each of the three 11-bit intermediate blocks to generate three 11-bit encoded words, and forming each codeword from a set of the three 11 -bit encoded words. The set of the three 11-bit encoded words satisfies a predetermined minimum zero run length (d) constraint, a predetermined maximum zero run length (G) constraint, and a predetermined maximum interleave zero run length (I) coding constraint.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1.

Abstract: The four tables P, Q, R and S contained in an ROM 2 for 16-24 modulation have a total number of data in which the continuing bits are 2 bits, that is not larger than i bits among the 24 bits, so that the number of continuing bits having the same code is from 2 to 8 bits, so as to have the same characteristics as the (1, 7) code, and to stably lock the PLL. A comparator/selector circuit 5 selects an optimum table out of the tables P, Q, R and S.

Abstract: A general rate N/(N+1) (0, G), code construction, e.g., for a magnetic recording system, allows for encoding or decoding of a dataword having N elements, N preferably being an integer multiple of eight. The dataword is divided into N/8 bytes of binary data that are encoded as a run-length limited (RLL) codeword in accordance with the general rate N/(N+1) (0, G) code construction. The general rate N/(N+1) (0, G) code construction is characterized by the constraints (d=0, G=(N/4)+1, l=N/8, r=N/8). the N/(N+1) (0 (N/4)+1, N/8, N/8) RLL codeword is constructed from the dataword in accordance with 1) pivot bits identifying code violations related to the constraints, 2) correction bits set to correct code violations, and 3) preserved elements having values not included in the code violations.

Abstract: A coding system includes methods and apparatus for producing a (0,6) run length limited rate 16B/18B code. The code produced is dc balanced and capable of operating near the theoretical performance limits for a 16B/18B code. This means the code is near optimum for run length and digital sum variation for a 16B/18B code. In one aspect of the invention, each 16-bit input data stream or block is broken into a 9-bit and a 7-bit sub-block and encoded separately while maintaining both dc balance and run length constraints across all block and sub-block boundaries. The present invention also provides a plurality of special purpose control characters such as commas, delimiters, idle characters, etc., by using the extra bits in the coded blocks whereby the special characters may be readily distinguished from data, while at the same time maintaining the dc balance and run length limitations in such characters. The 16B/18B transmission coding system of the invention also provides error correction techniques.

Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

Abstract: A method and apparatus for encoding a sequence of 32 bit digital data words into a sequence of 33 bit code words in consonance with predetermined minimum zero run length (d) and predetermined maximum zero run length (k) for recording upon a magnetic medium within a magnetic recording channel is disclosed. The method comprises steps of dividing each data word into eight data nibbles, determining whether any data nibble contains all zeros. If no code violation, mapping the eight data nibbles to seven code nibbles and to four bits of a five bit code sub-word and setting a fifth control bit to one. If one or more code violations are present, embedding code violation locations within at least the five bit code sub-word and other code nibbles if necessary and remapping data nibbles ordinarily directed to the code sub-word and nibble locations to code locations otherwise containing the data nibbles determined to be code violations.

Abstract: A message is encoded into an array, which is an element of a constrained array set. The message is encoded by considering candidates for each entry (e.g., column, bit) of the array. The candidates have a predetermined ordering. For each candidate that is considered, a lower bound is determined. The lower bound indicates a number of set elements including both the candidate being considered and previously selected candidates of the array. An entry is filled with a candidate based upon the value of the lower bound relative to an intermediate message. The intermediate message is initially equal to the message being encoded, and is updated after each column of the array has been filled.

Abstract: A method and apparatus for bias suppression which includes a transmitter having a bias suppression encoder and a closed-loop VCO FM modulator and a receiver having a bias suppression decoder and an AC coupled FM demodulator. The bias suppression encoder generates a running sum of an encoded digital data signal as well as the sum of an (N+1)-bit block of an injected digital data signal such that the encoder may invert a block of (N+1)-bits of the injected data signal if both sums are of the same polarity thereby reducing the average DC bias of the encoded digital data signal. The encoded data signal is modulated using a closed-loop VCO FM modulator with the DC tracking effect minimized as compared to modulating the non-encoded signal directly. In the receiver having an AC coupled FM demodulator, the bias suppression decoder extracts a stuff bit set by the transmitter and inverts the received block of data if the stuff bit is true.

Abstract: A digital modulator which inputs a data stream to convert to a channel bit stream. The multiplexed data block is generated by multiplexing dummy data to any position within each data block cut out of the data stream one by one. The first Reed-Solomon code is generated by Reed-Solomon-encoding the multiplexed data block as an information part. A plurality of second Reed-Solomon codes are generated by adding a plurality of Reed-Solomon codes for scrambling each of which has identification data showing its scrambling pattern in the same position as that of the dummy data, and the code length of information part and parity part is the same as the first Reed-Solomon code. The second Reed-Solomon code in which the characteristics becomes desirable after modulation among the plurality of the second Reed-Solomon codes is set for output.

Abstract: In a modulation processing unit, m bits of input data are converted to an n bit fixed length code. In an RML conversion unit, a restriction code which limits a minimum run d in a channel bit sequence after converting the fixed length code from repeatedly occurring a predetermined number of times, is converted to a data sequence. A clock is stably reproduced.

Abstract: A predetermined signal pattern whose length is 9 T or more (signal level="1") of a modulation signal S2 modulated by a modulating circuit corresponding to a conventional information signal is varied corresponding to an output signal SC1 of a disc identification code generating circuit. When the signal level of the output signal SC1 is "1", a signal converting circuit varies the signal level at a nearly center position of the particular signal pattern to "0" for 1 T. Thus, a pit whose length is 9 T or more is converted into two pits and one blank and recorded on a compact disc. When a reproducing operation is performed, a nearly center position of a reproduction signal of a pit whose length is 9 T or more is sampled. Corresponding to the sampled result, the disc identification code signal is decoded. Since a binary signal of the reproduction signal is not affected by the conversion, a conventional information signal is correctly reproduced.

Abstract: Arrangements are disclosed for use in a network of digital data processing systems for rapidly encoding information signals for transmission over communication links in the network, and for rapidly decoding information received thereover, thereby to facilitate higher-bandwidth communications over the network. In addition, network command and control information transmitted along in the data transmitted over the network is rapidly decoded and verified by a command decoder and command verifier.

Abstract: A clock signal is easily extracted from a signal transmitted corresponding to a partial response transmission method so as to securely identify bits.As a structure of a recording side, an 8-to-9 converting circuit is connected in series with a pre-coding circuit and a recording amplifier. An output signal of the recording amplifier is recorded on a magnetic tape. A signal reproduced from the magnetic tape is supplied to a reproducing amplifier. On a reproducing side, the reproducing amplifier is connected to a partial response equalizing and Viterbi decoding circuit and a clock extracting circuit. The clock extracting circuit is connected to the partial response equalizing and Viterbi decoding circuit.

Abstract: A coding/decoding method for high density data recording/reproduction, and an encoder/decoder. In the coding method for encoding an 8-bit binary data symbol X.sub.k (k=1, 2, 3, . . . , 8), received from a storage device or a communications channel, into a 9-bit codeword Y.sub.l (l=1, 2, 3, . . . , 9), the number of a maximum transition run (MTR) is limited to a predetermined number, and the number of zero run lengths of the codeword whose MTR is limited is then limited to a predetermined number. Then, a pattern providing a bad effect on detection of a signal is removed from the codeword whose zero run length is limited. In the rate 8/9 modulation code having an MTR of 3, the code rate is high, and the path of the Viterbi detector is reduced as in the rate 2/3 RLL(1,7) code having an MTR of 2, thereby decreasing the delay and complexity of the detector.

Abstract: A magnetic recording system with a rate 16/17(0,6/8) encoder/decoder modulation code. This modulation code has a low k constraint for synchronization of a road clock of the magnetic recording system. Furthermore, this magnetic recording system has a low hard error rate due to low 3- and 4-byte error propagation. The digital logic circuit for the encoder/decoder system is elegantly simple. Such simplicity reduces propagational delays and circuit size, as measured in number of logic gates. The modulation code is implemented with a decoder that includes a lower byte decoder and an upper byte decoder. An input of the upper byte decoder is in part coupled to and in part decoupled from the lower byte decoder. Similarly, an input of the lower byte decoder is in part coupled to and in part decoupled from the upper byte decoder.

Abstract: Clock is reproduced stably. If data (limiting code) containing a plurality of consecutive minimum inversion interval Tmin is contained in the data inputted from a shift register, a Tmin consecution limiting code detection unit detects such consecutive interval. A constraint length judgement unit judges the constraint length i to be the constraint length corresponding to the code for limiting the constraint length i when a detection signal is inputted from the Tmin consecution limiting code detection unit, and outputs the judged constant length to a multiplexer. The multiplexer selects the output of a converter corresponding to the constraint length supplied from the constraint length judgement unit out of converters 14-1 to 14-r, and supplies the selected output to a run detection processing unit through a buffer.

Abstract: A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.

Abstract: A sequence of m-bit information words is converted to a modulated signal wherein each received information word from the sequence is converted to an n-bit code word. The code word is selected from a set of codewords that depends on a coding state that is related to a digital sum value at the end of the part of the modulated signal that corresponds to the delivered code word. By at least one of the digital sum values, a first (S2, S4, S6, S8, S10, S12) or a second (S3, S5, S7, S9, S11, S13) coding state of a pair of coding states is determined. Which of the two coding states of the pair is determined depends on the information word that corresponds to the previously delivered code word. The sets (V2/V3; V4/V5; V6/V7; V8/V9; V10/V11; V12/V13) of codewords belonging to the pairs of coding states contain no codewords in common.

Abstract: An information recording apparatus 100, wherein record data whose length is 8 bits is modulated to code data whose length is 16 bits by using 8/16 modulation-demodulation method, and a data-sector including a plurality of the code data is recorded onto a DVD-RAM 1. In case that the last code data placed at the end-part of the data-sector is recorded onto the DVD-RAM 1, a discriminating data to used for demodulating the last code data to record data by using the 8/16 modulation-demodulation method is generated, and the discriminating data is recorded onto the DVD-RAM 1 at the place immediately after the last code data.

Abstract: In the case of transmitting upon converting the 8-bit word string data showing signal information to the 10-bit word string data consisting of word synchronous data, 8-bit word string data showing signal information is obtained and after inserting 2 each of the 8-bit word synchronous data and the 8-bit auxiliary word data to be converted to the 10-bit neutral word data, 8 to 10 bits conversion is conducted to the 10-bit word string data and transmitted; when converting the 8-bit word synchronous data to 10-bit word synchronous data, if the immediately preceding word data is the data having plus running disparity, it is converted to 10-bit word synchronous data having minus running disparity, and if the immediately preceding word data is the data having minus running disparity, it is converted to the 10-bit word synchronous data having plus running disparity. Thereby, in the case of reproducing the signal information at the receiving end, the necessary signal synchronization can be certainly obtained.

Abstract: A method and system for parallel encoding of data for bit-stuffed HDLC compatible transmission is presented. The method analyses a byte in parallel with four recirculated previously encoded bits during each clock cycle. The recirculated bits allow for correct analysis of the presence of a fifth consecutive one within the byte including the first four bits thereof. The encoded byte is provided to a FIFO and, when 8 bits are stored therein, the eight most significant bits are extracted from the FIFO for transmission via a digital or analogue network. The FIFO provides two bytes without receiving an intervening encoded data byte when a risk of an overflow exists.

Abstract: A system and method employing a rate 16/17 (0,5) code constructed in accordance with a set of pivot bits and a set of corrections for predefined code violations limits the number of consecutive zeros seen by a channel to five. The rate 16/17 (0,5) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance. Each constructed codeword is block encodable and block decodable, and the code construction allows for efficient circuit implementation in both an encoder and a decoder.

Abstract: System for decoding code words in the EFM-PLUS and/or EFM format in which an enumeration block makes it possible to associate in a one-to-one manner with each of the code words a numerical value from a practically continuous set of numerical values. The numerical value, possibly summed with an offset value, by an address generator, addresses a read-only memory in which are stored information codes, each of which is associated, as decoded information, with one of the code words.

Abstract: A dc balance-value calculation circuit is used in a recording signal generator for performing the block coding of original data to generate a code word having a series of at least two non-inverted bits and generating a recording signal based on the code word. The dc balance-value calculation circuit calculates a dc balance value representing a shift in the dc balance of the recording signal. The dc balance-value calculation circuit includes: selection means for separating the code word generated by the block coding into unit data of a plurality of bits, and selectively outputting the unit data; determination means for determining a change in a dc balance value for each unit data, based on the unit data output by the selection means; and dc-balance-value calculation means for calculating a dc balance value in accordance with the determination result by the determination means.

Abstract: An encoding/decoding method for a signal having at least two different positive and negative levels. Each symbol representing, for instance, two binary bits is encoded in each symbol period. During each symbol period, the encoded signal transitions between a level of one polarity to a level in the opposite polarity. The levels and transitions are selected so that there is no DC component. The frequency spectrum is shifted away from the lower frequencies with this encoding.

Abstract: There is provided an EFM encoder comprising a DSV calculator which is smaller in circuit scale than a conventional DSV calculator. The above DSV calculator has a merging-bit DSV calculator, a frame-signal DSV/polarity evaluator, adding means, and an overflow/underflow processor. The merging-bit DSV calculator calculates merging-bit DSV data based on merging bits and on a cumulative polarity signal. The frame-signal DSV/polarity evaluator outputs frame-signal DSV data in consideration of the polarity in the final bit of the merging bits. The adding means adds up the cumulative DSV data, the merging-bit DSV data, and the frame-signal DSV data so as to calculate DSV. The overflow/underflow processor performs, when overflow or underflow has occurred in the result of calculation from the adding means, exception handling with respect to the calculation result and outputs the calculation result that has undergone the exception handling as new cumulative DSV data.

Abstract: Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

Abstract: A DSV (Digital Sum Value) control system for use in conversion of a sequence of m-bit digital data codes into at least first and second sequences of n-bit digital modulation codes using a plurality of modulation tables under the DVD (Digital Video Disc) standards, for example. The DSV control system outputs a sequence of modulation codes produced by selecting, in time sequence, one of the codes of the first sequence or one of the codes of the second sequence according to a select signal SB. The select signal SB is provided based on a DSV control enable flag indicating that DSV control enable codes of the first and second sequences will appear at a following address and a select signal SA indicating which of the DSV control enable codes of the first and second sequences should be selected in order to optimize a DSV of the outputted sequence of modulation codes.

Abstract: The configuration of a whitener encoder used in a wireless LAN is simplified, thereby reducing the size of the circuit. The present weight of an n-bit interval is calculated by a counter that counts up when the transmitted data is "1", and counts down when it is "0". The weight for data already sent out is calculated by a counter that counts up when the transmitted data is "1", and counts down when it is "0". Whether or not the transmitted data is inverted is determined by comparing only the most significant bits, which are the sign bits of the counter, with a comparator circuit. A large circuit need not be used.

Abstract: The present invention provides a lossless coding scheme that maps unconstrained binary sequences into sequences that obey the (d,k)-RLL constraint while offering a degree of DC control. In the preferred embodiment, the channel encoder is a state machine which uses a single "overlapping" table for all states rather than using multiple tables. Recognizing that a subset of codewords in a first state x.sub.i are identical to a subset of codewords in the second state x.sub.j, the overlapping encoding table uses identical addresses for the subset of identical codewords in the first and second state. Thus addresses for more than one state may point to a single codeword. A number of input bytes can be encoded into two different codewords which have different parity of ones, thus allowing for DC control. Decoding is carried out in a state-independent manner.

Abstract: An improved DC compensation method for use in conjunction with telephony signalling. The method includes defining a frame that includes at least two n-bit codewords. An unsigned codeword is then identified within the frame by applying a rule to the codewords in the defined frame. Next, a sign bit is appended to the unsigned codeword, thereby producing a DC compensating codeword. The sign bit is selected based upon a weighting function of the linear values associated with previously transmitted codewords. The remaining unsigned codewords in the frame are assigned sign bits from user data.

Abstract: A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks.

Abstract: Method and apparatus for encoding digital information to be recorded on a magnetic medium is disclosed. The invention provides for receiving a sequence of (2.sup.m n+d) user bits, mapping the sequence of user bits to 2.sup.m dc-free codewords, and recording the 2.sup.m dc-free codewords on a magnetic medium. A modulation coder, which includes a memory containing multiple non-intersecting subconstellations of dc-free codewords, performs the mapping in a non-equiprobable manner such that a particular codeword from a larger subconstellation is more likely to be used than a particular codeword from a smaller constellation. Less desirable codewords, such as those containing relatively long strings of bits having the same value, are assigned to the smaller subconstellations, thereby lessening the likelihood of loss of timing and gain parameters in the system, as well as maximizing the transmission rate and efficient use of the set of possible dc-free sequences of a given length.

Abstract: A method and an apparatus are disclosed for recording a binary signal onto a magnetic record carrier. The binary signal is supplied to an input terminal. The apparatus comprise generators for generating at least two write pulses (P.sub.1,P.sub.2) for each bit of the binary signal to be written. More specifically, the generators are adapted to(i) generate at least two write pulses of a third polarity for the first bit of the first polarity in the first sequence,(ii) generating a write pulse of the third polarity and a write pulse of a fourth polarity for the at least second bit of the first polarity occurring in the first sequence, the third polarity being opposite to the fourth polarity,(iii) generating at least two write pulses of the fourth polarity for the first bit of the second polarity in the second sequence,(iv) generating a write pulse of the third polarity and a write pulse of the fourth polarity for the at least second bit of the second polarity occurring in the second sequence.

Abstract: A method of decoding a sequence of samples received over a communications channel, such as a partial response channel, in which the sequence represents a length k binary bit stream encoded as a sequence of bipolar symbols comprised of q groups of L symbols, each length L group of said symbols corresponding to one of 2.sup.m subwords having a predetermined block digital sum. The decoding method makes use of the structure of the encoding method by finding, in one illustrative embodiment, for each group of L samples, the maximum likelihood path through a time varying trellis supporting the sets of subwords having predetermined block digital sums to identify said subwords; recording the state metrics and branch metrics for each path and identifying, from the metrics the maximum likelihood path, the order of concatenation of the subwords.

Abstract: A code conversion method and apparatus is provided for scrambling and modulating data. The method and apparatus includes scrambling an input main data unit based on any of plural types of pseudo-random number sequences, and modulating the scrambled main data unit based on any of plural types of modulation data. An output main data unit is produced from the modulated main data unit, and a calculated value representing a difference between a number of 0 bits and a number of 1 bits included in the output main data unit is obtained. Any of the modulation data is then selected dependent upon the calculated value.

Abstract: A signal modulation method used for a digital channel of digital recording media and digital communication. The method includes the steps of (a) receiving data in a first data unit of a first bit length and RLL encoding the received data into a (d,k) code word; and (b) receiving data in a second data unit of a second bit length and RLL encoding the received data if a number of consecutive zeroes is less than d when two codes words encoded in said step (a) are concatenated. Therefore, a higher resolution than that of other modulation codes is achieved, for a minimum time interval, 4T (diffraction limit). The DC component of a modulated code can be suppressed by controlling merging bits.