Abstract: The present invention pertains to a modulation apparatus and method in which the modulation apparatus is realized with a simple circuit structure and is easily applicable to other systems. A pattern conversion unit 32 converts data having a basic data length of 2 bits supplied from a DSV control bit determination and insertion unit 31 into a variable-length code having a basic code length of 3 bits in accordance with a conversion table. A minimum-run-length limitation code detection unit 33 detects, from a data sequence containing a DSV control bit, the position of minimum runs consecutive from a channel bit string converted by the pattern conversion unit 32. A consecutive-minimum-run replacement unit 34 replaces a predetermined portion of the channel bit string supplied from the pattern conversion unit 32 for a predetermined pattern based on the position information supplied from the minimum-run-length limitation code detection unit 33, and limits the minimum run length to a predetermined number or less.

Abstract: The present invention relates to a modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence, and to a DSV-control-bit generating method. A 1-7 PP data conversion unit 52 supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table based on Table 3 to a modulation-delimiter detecting unit 81, and supplies to a valid-delimiter detecting unit 81 a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence including the DSV control bit inserted. The modulation-delimiter detecting unit 81 detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto, and supplies a modulation-delimiter signal to the valid-delimiter detecting unit 82.

Abstract: An encoder suppresses effectively the high-frequency components of data to be transmitted by decreasing the changing points of serial data, thereby suppressing EMI. A changing-point counter counts changing points of n-bit data (n: a positive integer) to generate a counting result, where values of adjoining bits change at each of the changing points The changing-point counter outputting a discrimination bit which is true when the counting result exceeds a predetermined value. A code converter converts the n-bit data in such a way that bits of the n-bit data located at predetermined positions are inverted when the discrimination bit is true. A parallel-to-serial converter converts (n+1)-bit data to a (n+1)-bit serial code, the (n+1)-bit data being generated by adding the discrimination bit to an output of the code converter.

Abstract: A method for correcting an analog signal to target levels is provided. Firstly, the analog signal is periodically sampled to obtain a plurality of sampled points. Then, levels of the sampled points are compared with a threshold value to find a set of sequentially sampled points including a head and a tail ones, each having a first comparing result with the threshold value, and the other intermediate ones, each having a second comparing result with the threshold value. Then, one of the set of sequentially sampled points, which has the second comparing result with the threshold value, is adjusted to one of the target levels. A device for correcting an analog signal to target levels is also provided.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method generates for each data word a number of intermediate sequences by combining mutually different digital words with that data word, scrambles these intermediate sequences, translates each scrambled sequence into a (d,k) constrained sequence, detects running digital sum (RDS) every bit for each translated (d,k) constrained sequence while counting sign changes of each RDS, selects one sequence of which RDS changes most in sign among the (d,k) constrained sequences after discarding every sequence of which maximum value of RDS is beyond a preset threshold, and records the selected sequence onto a recordable medium such as an optical disk or a magneto-optical disk. The present invention can suppress DC component more remarkably in case that a sequence becomes longer.

Abstract: Managing a primary bit stream involves converting a qB/rB encoded bit stream to an xB/yB encoded bit stream and multiplexing an additional bit stream with the xB/yB encoded bit stream at a transmission side of a link. The additional bit stream is then demultiplexed from the xB/yB encoded bit stream and the xB/yB encoded bit stream is converted back to the qB/rB encoded bit stream at the receiver side of the link. The qB/rB encoded bit stream is converted to and from the xB/yB encoded bit stream so that the additional bit stream can be multiplexed with the qB/rB encoded bit stream using multiplexing/demultiplexing systems that are compatible with the xB/yB multiplexing system. In an application, a 4B/5B encoded bit stream is converted to an 8B/10B encoded bit stream and an additional bit stream is multiplexed with the 10B code-words of the 8B/10B encoded bit stream using code-word manipulation.

Abstract: A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits.

Abstract: A coding system that in a first embodiment is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords has an 8-bit first half and a 9-bit second half, wherein the first half has at least 3 or more ones, and wherein the second half comprises at least 3 or more ones. The first half and second half of the codewords each have odd-coordinate bits and even-coordinate bits, at least one odd-coordinate bit of each half has a value of one, and at least one even-coordinate bit of each half has a value of one. In a second embodiment, the coding system is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords have an 11-bit first half and a 6-bit second half, wherein the first half comprises at least 3 or more ones, and wherein the second half has at least 2 or more ones.

Abstract: A coding scheme encodes a series of M-bit message words into a series of N-bit codewords having a bounded unbalance. A part of the M-bit message words are used to index bits and others source words. The message words are grouped to a plurality of subsets using the index bits thereof. The unbalanced codewords are classified to a plurality of sets based on a state transition in a trellis. Each of the classified unbalanced codewords is stored at a codebook for each codeword set, respectively. The codebook has the source words, a codeword ID for each of the source words and the classified unbalanced codewords. The message words are encoded into the respective codeword in the codebook, respectively, by using the index bits of the message words and the state transition in the trellis having states and levels. The codewords are selected by transition for each state at each level stage of the trellis based on correlations.

Abstract: A method of clock recovery in digital transmission systems based on a transition minimized differential scaling (TMDS) is described. Repeater based on the said method allows a TMDS transmission over long lines to a plurality of TMDS receivers without accumulating of phase distortions.

Abstract: One embodiment of the present invention provides a system that transmits a stream of datawords through a bundle of conductors with a three-dimensional structure. Upon receiving a dataword to be transmitted, the system uses an encoding function to encode the dataword into a current codeword in a stream of codewords, wherein the current codeword is less than double the size of the dataword. Next, the system transmits the current codeword to a destination through the bundle of conductors. Note that the encoding function depends on a preceding codeword in the stream of codewords, so that when the preceding codeword changes to the current codeword, rising transitions are substantially matched with falling transitions within the bundle.

Abstract: A device and associated method for processing a digital information signal from a channel signal. The digital information signal is runlength limited with one or more constraints. The device comprises receiving means for receiving the channel signal and means for comparing a detected runlength with a predetermined value indicative of a minimum runlength constraint or a maximum runlength constraint of the channel signal and for generating a control signal when the detected runlength violates said constraint. The device further comprises substitute means for in response to the control signal deleting or inserting an element in the channel signal.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A code modulation and demodulation method includes removing a DC component of a code stream to be modulated when source data is recorded on an optical information storage medium and controlling a suppression of the DC component contained in the code stream when the source data is converted into a codeword to be recorded on an optical information storage medium. The method includes determining a control timing to suppress the DC component of the code stream to which the source data are converted, performing a code conversion at each control time for the DC component so that the code stream branches into a pair of branch code streams one of which extends in a direction where a running digital sum (RDS) of the code stream increases, and another one of which extends in the direction where the RDS of the code stream decreases, and selecting the path of the code stream that has a most bounded path around RDS ‘0’ from the paths of the branch code streams each control time.

Abstract: The present invention relates to method and apparatus of modulating a series of data words into (d,k) constrained sequence in order to record onto a recording medium. The present method generates, for each data word, a number of alternative sequences by combining mutually different digital words with the data word, calculates for each alternative sequence a digital sum value (DSV) and a penalty based on respective consecutive-zeros sections within the sequence and a joining consecutive “zeros” to a previously-selected sequence, and selects one alternative sequence for recording onto a recordable medium based on the calculated DSV and penalties. Owing to the present invention, DC component of sequences to be recorded onto a recording medium is suppressed and stabilization of a reproduction clock is improved through writing more edge information (i.e., “1”s).

Abstract: Data modulating/demodulating method and system and apparatus using the same. The modulation method with smaller modulation table, compared to the conventional modulation table, is used to modulate the source data to the channel bits to be recorded to an external storage apparatus, such as optical disc. The demodulation method with smaller demodulation table, compared to the conventional demodulation table, is used to demodulate the bit data stream recorded on a storage apparatus, such as optical disc, to the original source data.

Abstract: A method of transmitting digital data, which comprises the steps of obtaining first and second 8-bit word sequence data respectively based on luminance signal information data and chrominance signal information data which constitute a digital video signal, causing each of the first and second 8-bit word sequence data to be subjected to 8 bits to 10 bits conversion to produce first and second 10-bit word sequence data, obtaining third and fourth 8-bit word sequence data based on the first and second 10-bit word sequence data, respectively, inserting an additional word data group including 8-bit word synchronous data allotted a predetermined specific code into each of the third and fourth 8-bit word sequence data at predetermined word intervals to produce first and second composite 8-bit word sequence data, converting the first and second composite 8-bit word sequence data into first and second serial data, respectively, and transmitting the first and second serial data through first and second transmission lin

Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: A digital modulation method in which at a head of an input block (pre-translation), each of a plurality of different types of initial data of t bits is multiplexed to generate a plurality of different types of multiplexed blocks, t bits at the head and immediately following t bits of each of the multiplexed blocks are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and the immediately following t bits are subjected to an exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter in the similar manner, a convolution operation is executed. A plurality of different types of translated blocks are produced by the convolution operation, and DC components of thus provided translated blocks are calculated, respectively, absolute values of the respective DC components are compared with each other, and a translated block having the minimum value is selected and output externally.

Abstract: Improvement in the transmission of Boundary Scan Test mode data may be achieved through the assignment of boundary scan test mode traffic to selected bit patterns that facilitate clock recovery and frame alignment in the serial channel. The encoding of boundary scan test traffic as such may be achieved through either multiplexed transmission to the serializer/deserializer (SERDES) alongside a regular channel encoder or incorporated into the channel encoder.

Abstract: An information carrier includes runlength limited marks in a track. The runlengths of the marks represent main channel bits and variations of a further parameter of the marks representing secondary channel bits. Not all marks have the variations, only marks of at least a predetermined runlength have the variations.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A method and apparatus for recording and reproducing information to and from an optical disk. If the size of a shortest mark is made small, a signal amplitude lowers and errors are likely to occur. In order to overcome this problem, when data of asymmetric codes is written, the length of a write mark is compensated so that the shortest mark and gap have the same length.

Abstract: A method and a device is disclosed for encoding/decoding digital data transmitted through a serial link, particularly of the so-called “8B/10B” type. A full encoded binary word includes 8 data bits and a 2-bit label. The logical state of a center bit triplet of the byte is detected. When all of the bits are in the same logical state, the center bit of the triplet is inverted prior to transmission. Otherwise, the byte is transmitted as is. The label is forced to the logical configuration “10” when there is a bit inversion, and to “01” in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1.

Abstract: Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30.

Abstract: A method and apparatus for state assignment of a logic circuit comprises receiving internal state representations for the logic circuit, determining binary code for the internal state representations by successively dividing the states into disjoint sets of ever decreasing size Each disjoint set of a pair is assigned a one bit at each division step. The division can continue for all bits to be encoded, or the division can be halted and exact encoding used for the encoding of the final number of bits.

Abstract: Multiplexing an additional bit stream with a primary bit stream, where the primary bit stream is encoded into an xB/yB encoded bit stream, involves selecting yB code-words to convey the additional bit stream. Each xB word is represented by one yB code-word from a corresponding group of yB code-words, with each group of yB code-words including at least one yB code-word belonging to a category of code-words that tends to exhibit positive DC balance and at least one yB code-word belonging to a category that tends to exhibit negative DC balance. Bits of the additional bit stream are multiplexed with the primary bit stream by selecting code-words from one of the two categories to convey 1's and from the other category to convey 0's. Code-words that are not selected to convey bits of the additional bit stream are selected to balance the running disparity of the encoded bit stream.

Abstract: A signal transmission device which transmits n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip is proposed. The signal transmission device includes an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide encoded m-bit parallel digital signals for the I/O driver, where m>n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (m−p), where Cpm>2n and m>p>0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.

Abstract: A method of coding data for communication within a network. The method includes receiving an 8b/10b source protocol data stream containing 10-bit code and translating the data stream into an 8-bit code by converting the 10-bit code into 8-bit data and an ordered set. The method further includes transmitting the 8-bit code.

Abstract: One embodiment of the present invention provides a system for encoding a dataword into a current codeword within a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. The system creates the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword. This is accomplished by using the dataword to select one bits and the zero bits to invert; determining locations of the one bits and zero bits in the preceding codeword; and then inverting the selected one bits and zero bits in the preceding codeword to form the current codeword.

Abstract: A method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: The present invention provides techniques for classifying disparities and source vectors for 7B/8B and 9B/10B transmission codes, which are then used to minimize the complexity of decoding and encoding for 16B/18B codes. The classifications are determined for source vectors and for disparity for coded vectors. The vector classifications are selected in a predetermined manner so that the number of classifications is minimized for bit mapping, disparity control, or both. Additionally, the number of bits changed for bit mapping is minimized. Decoding of 7B/8B and 9B/10B transmission codes is performed by converting coded vectors into a single image and then performing decoding operations to decode the single image of the coded vectors. The single image is a primary coded vector, and an alternate coded vector is an inverted version of the primary coded vector. Techniques are presented for using 5B/6B, 7B/8B and 9B/10B transmission codes in other transmission codes such as 12B/14B and 17B/20B transmission codes.

Abstract: Look ahead encoder and decoder architecture. To increase the encoding speed, bytes of input data to be encoded are applied in parallel to each encoder of a pair of encoders in the look ahead encoder architecture. One encoder of each pair receives a first control input signal, while the other receives a second control input signal. The output bytes of binary data from the two encoders are applied to a multiplexer which selects the proper output byte based on the control output signal resulting from the immediately preceding encoded output byte of binary data. In one embodiment, a single encoder encodes the previous byte, doubling the encoding speed. In a second embodiment, a number of encoder pairs are utilized, with the multiplexers connected in a ring to utilize the selected control output signal from one multiplexer as the select signal for the next multiplexer in the ring, increasing the encoder speed by a factor equal to the number of encoder pairs.

Abstract: A method and apparatus of converting a series of data words into modulated signals are provided. This method generates for each data word a number of intermediate sequences by combining mutually different digital words with that data word, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, checks whether each (d,k) constrained sequence contains undesired sub-sequence of more than kSET “0”s where kSET is smaller than k, and selects one (d,k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences not having the undesired sub-sequence, thereby recording edge information more frequently which will result in stable clock while conducting DSV control normally.

Abstract: A method for modulating digital data and apparatus therefor is capable of determining a digital data stream coded by Run Length Limited swiftly and precisely so as to record data in a recording medium. The digital data modulating method includes the steps of comparing a preset critical value and DSV (Digital Sum Value) of a certain digital data stream, computing the penalty of the digital data stream by multiplying the number of the time that the DSV of the digital data stream is larger than the critical value by a preset weight value of the critical value, comparing the penalty of the digital data and a penalty of another digital data stream and selecting a digital data stream with a smaller penalty as the digital data stream. Therefore, with the method for modulating digital data and apparatus therefor, the digital data stream which will be modulated among a number of digital data streams can be selected precisely and swiftly.

Abstract: A system and method are disclosed for writing a multilevel data sequence to a storage medium so that a read signal generated by reading the multilevel data sequence from the storage medium will have reduced low frequency content is described. The method includes evaluating the effect of a plurality of candidate merge symbols on an RDS of the read signal. A preferred merge symbol is selected from among the plurality of candidate merge symbols based on the effect of the preferred merge symbol on an RDS of the read signal. The preferred merge symbol is added to the multilevel data sequence so that the RDS of the read signal is controlled.

Abstract: A data modulation method resistant to channel distortion and a method of correcting error in data coded by the modulation method. The data modulation method uses a run length limited (RLL) modulation code applied to write data to an optical storage medium, the RLL modulation code being expressed as RLL (d, k, m, n, s) with s=2 or greater, where d is minimum run length, k is maximum run length, m is a data bit length before modulation, n is a codeword bit length after modulation, and s is a space length between codewords. Further, the data modulation method provides run lengths expressed as in+1=in+s (n=1, 2, . . . ), where i1=d.

Abstract: A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Abstract: An encoder encodes a stream of date-bits of a binary source signal into a stream of date-bits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words. The encoder includes a converter for converting the source words into corresponding m-bit channel words. The converter converts n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting. The relations hold that m>n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1. A decoder decodes the channel signal, obtained by means of the encoder, to reproduce the source signal.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method generates for each data word a number of intermediate sequences by combining mutually different digital words with that data word, scrambles these intermediate sequences, translates each scrambled sequence into a (d,k) constrained sequence, detects running digital sum (RDS) every bit for each translated (d,k) constrained sequence while counting sign changes of each RDS, selects one sequence of which RDS changes most in sign among the (d,k) constrained sequences after discarding every sequence of which maximum value of RDS is beyond a preset threshold, and records the selected sequence onto a recordable medium such as an optical disk or a magneto-optical disk. The present invention can suppress DC component more remarkably in case that a sequence becomes longer.

Abstract: The present invention relates to method and apparatus of modulating a series of data words into (d,k) constrained sequence in order to record onto a recording medium. The present method generates, for each data word, a number of alternative sequences by combining mutually different digital words with the data word, calculates for each alternative sequence a digital sum value (DSV) and a penalty based on respective consecutive-zeros sections within the sequence and a joining consecutive “zeros” to a previously-selected sequence, and selects one alternative sequence for recording onto a recordable medium based on the calculated DSV and penalties. Owing to the present invention, DC component of sequences to be recorded onto a recording medium is suppressed and stabilization of a reproduction clock is improved through writing more edge information (i.e., “1”s).

Abstract: The invention relates to a modulation code system, including an encoder and a decoder and two corresponding modulation code methods. More specifically, the encoder 100 serves for transforming an original signal s into an encoded signal c satisfying predefined second constraints. Such encoder signals are, for example, transmitted via a channel 300 or stored on a recording medium. After receipt or restoration, said encoded signal c is decoded by a decoder 200 in order to regenerate the original signal s again. It is the object of the present invention to improve the known modulation code systems and methods in such a way that their embodiment requires less hardware. This object is solved in that the encoder 100 comprises a series connection of a modulation code encoder 110 and of a transformer encoder 120 allowing an N-time integration of the output signal of said modulation code encoder 110.

Abstract: A sequence of randomly arriving input codes of first type (control) are stored in first sequential storage locations in order of arrival and the input codes of second type (data) are stored in second sequential storage locations in order of arrival, and order-of-arrival indications of the input codes are stored in third sequential storage locations. The contents of all storage locations are organized into a predetermined format using a signal indicating whether the input code is of the first or second type. The organized format contains an identification code indicating whether or not it is a mixture of the first and second types of input codes. Preferably, a counter is provided for producing a count number of input codes of the first type, which is used to produce data to be appended to the organized format when a predetermined number of input codes are received.

Abstract: To convert a 12-bit data word into an 18-bit code word, the 12-bit data word is divided into the 8 high-order bits and the 4 low-order bits. The 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits, thereby creating an 18-bit code. This enables conversion using small-scale conversion tables.