Abstract: A method of encoding first and second symbols each having n binary bits into first and second code words each having n-1 ternary trits is disclosed. The method involves using a preselected bit from each of the first and second symbols to determine which one of at least two groups of code words comprising n-1 trits is used for encoding. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: In a device or a recording apparatus for converting n-bit data into m-bit data with different conversion methods, and selecting and outputting one of a plurality of converted m-bit data, when controlling output means in accordance with the plurality of m-bit data, a specific signal component is extracted from each of the plurality of m-bit data, the absolute values of the plurality of extracted outputs are obtained, and at least one of the plurality of absolute values or the extracted output corresponding thereto is selectively output (recorded). Thus, superposition and suppression of a specific frequency component can be realized by a single circuit having a very simple circuit configuration. As a result, the size and the cost of a digital signal recording apparatus utilizing a modulation circuit of this kind can be reduced.

Abstract: A control signal generation apparatus for use in a digital information signal recording system enables an optimum channel word of two channel words output from two precoders to be recorded on a digital record medium. The control signal generation apparatus compares the same kind of spectrum components from among peak, notch, and dip components detected from the two channel words, and generates a control signal for selecting an optimum channel word. The apparatus includes a gain controller for controlling the gains of integrators used for detecting the peak, notch, and dip components. The gain controller compares the detected peak, notch, and dip components with upper limit and lower limit set reference values, and generates a gain control signal according to the comparison results.

Abstract: An 8/9 coding apparatus which suppresses the DC component of input data to be recorded on a magnetic tape by converting the 8-bit input data to 9-bit coded data, provided with a CDSc table for the CDSc data, that is, the data of the complement of 2 of the cumulative value of bits in a symbol included in coded data based on the input data. In a DSVc adder, CDSc data is cumulatively added by a polarity in accordance with polarity data, DSVc data indicating the complement of 2 of the cumulative value of the bits for every sector is generated, and an MSB bit thereof is output as MSB data to a table selector. The table selector outputs a table switching signal generated based on the polarity data and the MSB data to a data table, a polarity table, and the CDSc table. The tables are selectively used based on this switching signal.

Abstract: In the present invention, a partly duplexed conversion table is used as a conversion table for converting an M-bit based data string directly into an N-bit based code string without using margin bits. This conversion table is constituted by first and second sub-tables including plural code groups, respectively. The plural code groups include different codes for the same input data. The second sub-table is a table which is partly duplexed with the first sub-table and is produced by allocating different codes to data from first input data to second input data in the first sub-table. The first and second sub-tables are so designed that code sets of the duplexed portions take variants of digital sum variations which are opposite in sign. Codes are allocated to all the code groups in the duplexed portions of the first and second sub-tables with respect to input data sequentially from a code having a maximum absolute value of variant of the digital sum variation.

Abstract: 5*3 states are arranged on a plane composed of the horizontal axis and vertical axis, 2-bit data of 01, 10, 00, and 11 are assigned to the state transitions in the up, down, right, and left-directions respectively in the 3*5 states. A 20-bit code is generated by 10 times the state transitions. 2.sup.16 20-bit codes are prepared and these codes have a one-to-one correspondence to 16-bit data (2.sup.16). The end point of the previous state transition is the starting point of the next state transition, and 16-bit data are converted successively to 20-bit codes while the state transitions occur continuously. In the manner as described above, the conversion efficiency in PR (1, 1) is improved.

Abstract: An apparatus for modulating input data so that at least a part of a predetermined number of the input data is influenced by control data and adding the control data every predetermined number of modulated input data. The apparatus includes (a) modulating mechanism for modulating the input data so that a portion of the predetermined number of the input data exerts an influence on a part of another predetermined number of the input data; (b) detecting mechanism for detecting a specific frequency component in the modulated input data that is outputted from the modulating mechanism; (c) generating mechanism for generating the control data in accordance with an output of the detecting mechanism; and (d) selecting mechanism for selectively outputting the control data generated by the generating mechanism, data that is influenced by the control data in output data of the modulating mechanism, and data that is not influenced by the control data.

Abstract: A transmitter apparatus for transmitting a digital data signal via a transmission medium (10) includes an error protection encoder (3) for carrying out an error protection encoding on the digital data signal so as to obtain an error protection encoded digital data signal, and a channel encoder (6) for converting the error protection encoded digital data signal processed into a channel encoded digital data signal. The channel encoded digital data signal is supplied to the transmission medium. The error protection encoder (3) is adapted to carry out an error protection encoding step on packets of p m-bit digital words in the digital data signal, and for supplying error protection encoded packets (Q) of n m-bit digital words to an output, where n, m and p are integers larger than 1, and n>p.

Abstract: An Ethernet-type local area network having multiport repeaters and nodes within a specified distance of the hub is able to communicate high speed digital data over multiple pairs of twisted-pair wires using long symbol group-type ternary coding. Bundle mode termination minimize impedance mismatches. Low-frequency collision detection circuitry permits detection of packet collisions on an a.c.-coupled network. Precise serialized digital to analog conversion is realized using chains of gates to form delay elements with precise delays.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: This invention provides a code generator for reduction of the power consumption of digital signal processors. A plurality of codes are prepared for an item of data. A code with the lowest polarity-inverting bit count for input data, is selected from among the prepared codes. The code generator of the present invention has a code generation section, a code selection section and a code output section. The code generation section inputs data from a data file and generates all codes allocated to the input data. The code selection section makes a comparison between each of the generated codes and a code that is transferred just before or after any one of the generated codes is transferred over a bus of the digital signal processor, in order to select from among the generated codes a code having the lowest polarity-inverting bit count. The code output section writes the selected code into a code file.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation.

Abstract: A method of inhibiting copying of digital data. In a first embodiment, a sequence of symbols is added to original data, the sequence of symbols selected to encode into channel bits having a large accumulated digital sum variance. The sequence of symbols is then encoded by a special encoder that generates special channel bits that don't have a large accumulated digital sum variance. The special channel bits may be unambiguously decoded, but the resulting decoded symbol sequence will likely be reencoded into channel bits having a large accumulated digital sum variance. In a second embodiment, a single symbol in the sequence of symbols is replaced after error correction symbols have been added. The sequence of symbols with one substituted symbol is encoded into channel bits that don't have a large accumulated digital sum variance.

Abstract: A modulating apparatus wherein input data is modulated in the case of recording code data, which can be read optically, on a recording medium, so that a number of consecutive bits of a predetermined value in the code data is less than a predetermined number of consecutive bits of the predetermined value in a reference mark (e.g., a marker in a dot code), in order to discriminate the code data from the reference mark. An 8-10 modulating apparatus for modulating 8-bit input data to 10-bit data comprises two 4-5 modulating units (memories) for converting 4-bit input data to 5-bit data. And a 10-8 demodulating apparatus for demodulating 10-bit input data to 8-bit data comprises two 5-4 demodulating units for converting 5-bit input data to 4-bit data.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A method of encoding a five bit symbol into a four trit code word is disclosed, comprising defining out of forty-eight combinations of four trit code words three groups, each group containing sixteen code words, each code word within a group having a Hamming distance of at least two from any other code word in the group, and each code word being associated with a particular combination of four bits selected from said five bit symbol. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: A variable rate bit inserter is provided which efficiently encodes data prior to writing to a magnetic storage media. In a preferred embodiment, the bit insertion technique monitors the phase and amplitude content of the data stream and inserts appropriate bit patterns to ensure that phase and amplitude lock are maintained on the data stream for reading and decoding purposes.

Abstract: The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform.

Abstract: An encoder for matched spectral null binary codes is described, particularly for 12B/15B codes. The codeword trellis is partitioned into two or more subtrellises, and each subtrellis is encoded separately. The codeword is the concatenation of the codewords produced by the subtrellises. Some valid sequences have to be excluded, in order to ensure that all concatenations are valid, but the storage requirements, are greatly reduced.

Abstract: A method of converting a series of m-bit information words to a modulated signal. For each information word from the series an n-bit code word is delivered. The delivered code words are converted to the modulated signal. The code words are distributed over at least one group of a first type and at least one group of a second type. For the delivery of each of the code words belonging to the group of the first type the associated group establishes a coding state of the first type. When each of the code words belonging to the group of the second type is delivered, a coding state of the second type is established which is determined by an information word belonging to the delivered code word. When one of the code words is assigned to the received information word, this code word is selected from a set of code words based on the coding state. The sets of code words belonging to the coding states of the second type are disjunct.

Abstract: A data encoding method for converting a (m i) bit based data word string into a (n i) bit based codeword string. The encoding method receives a (m i) bit based data word string by a shift register 1, decides a constraint length specifying the length of a data word which is to be converted by an encoder 2, and decides on which number of bits as counted from the leading end of the m bits falls the leading end bit of the data word which is to be converted. The encoding method selects, by a selector 3, one of a plurality of conversion tables constituting variable length tables and at least satisfying the minimum run length d, in accordance with the constraint length and the above results of decision. The encoding method also generates a codeword corresponding to the data word, now to be converted, in accordance with the selected conversion table.

Abstract: Disclosed are an encoding method and demodulating method for a PRML system for maximum-likelihood-detecting and demodulating a encoded partial response signal. The encoding method comprises a step of segmenting an input data string into 4-bit data and a step of converting the 4-bit data into 6-bet code words Y={001011, 001101, 001110, 010011, 010110, 011001, 011010, 011100, 100011, 100101, 100110, 101001, 101100, 110001, 110010, 110100}.

Abstract: A signal binary coding circuit and a recording medium reproducing apparatus can binary coding efficiently the input signal sampled by the discrete time, by providing: a subtracting circuit for subtracting direct current components from the sampled value input; a comparator circuit for comparing the output value of said subtracting circuit and a threshold and outputting the binary signal based on said comparison value; an amplitude limiting circuit to amplitude-limit the output value of the subtracting circuit with the fixed value; and a direct current component forming circuit to calculate direct current components from the output value of the amplitude limiting circuit.

Abstract: An encoder includes a control bit insertion circuit (12) for inserting a control bit into input data, which is then subjected to I-NRZ modulation by a precoder (14) to generate a reference code. The reference code is given to a 4-code generation circuit (22) through a delay circuit (16), and frequency components of the reference code, and first, second and third codes generated on the basis of the reference code are detected by a frequency detector (18). The frequency components are given to a judge circuit (20) such that it is determined whether the frequency components are large or small. A judge signal is applied to the 4-code generation circuit and a frequency detector from the judge circuit. The 4-code generation circuit selectively outputs one selected from the reference code and the first to third codes on the basis of the judgement signal.

Abstract: Low-redundancy codes are increasingly being striven for, such codes thus inevitably requiring comparatively long code words. However, since the memory requirement for coding tables increases considerably with the length of the code words, the use of code tables is then no longer expedient. Instead, coding is then effected by selecting the optimum code word in each case from a plurality of different code words taking account of coding; prescriptions and spectral decisions. For this purpose, the maximum run length for each code word is also determined, inter alia, but the spectral decisions are decisive as long as the maximum run length does not exceed a predetermined maximum value. Provided that the end of one code word and the beginning of a succeeding code word have the same binary value, incorrect decisions in the selection of the optimum code word may arise in the region where the synchronizing pattern is keyed in.

Abstract: A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of:shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs,encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, andinterleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.

Abstract: Rate 24/25 modulation encoding methods and apparatus improve efficiency in a PRML magnetic recording channel. The rate 24/25 code word uses rate 8/9 RLL encoding of one byte of user data, combined with interleaved unencoded bytes to achieve improved code rates with reasonable global run length constraint. Use of the the rate 8/9 RLL (0,3) subcode results in a rate 24/25 RLL (0,11) code, while a rate 8/9 (0,6/5) subcode results in a rate 24/25 RLL (0,14/13) code.

Abstract: A method and apparatus for bias suppression which includes a transmitter having a bias suppression encoder and a closed-loop VCO FM modulator and a receiver having a bias suppression decoder and an AC coupled FM demodulator. The bias suppression encoder generates a running sum of an encoded digital data signal as well as the sum of an (N+1)-bit block of an injected digital data signal such that the encoder may invert a block of (N+1) -bits of the injected data signal if both sums are of the same polarity thereby reducing the average DC bias of the encoded digital data signal. The encoded data signal is modulated using a closed-loop VCO FM modulator with the DC tracking effect minimized as compared to modulating the non-encoded signal directly. In the receiver having an AC coupled FM demodulator, the bias suppression decoder extracts a stuff bit set by the transmitter and inverts the received block of data if the stuff bit is true. Alternately, the received data block is not inverted if the stuff bit is false.

Abstract: Channel-encoding and channel-decoding of a (d, k, m, n) code are disclosed. An m-bit input word is encoded to an (n-d+1)-bit channel word by an encoding table. One or more merge bits are added to each of the encoded channel words so as to form an n-bit channel word. Depending upon detection of violation of d and/or k constraints in the juxtaposition of consecutive channel words in combination with their intervening merge bit(s), certain bits are converted to cause the d and k constraints to both be met, and for the purpose of minimizing the digital sum value (DSV). To decode the channel words thus encoded, n-bit channel words are received and examined as consecutive pairs to determine the states of the merge bit(s) and the identifying bits of each channel word. The identifying bits and/or the last bit of the first channel code and the first bit of the second channel code are converted based on the validity of the d and k constraints.

Abstract: Data converting method and apparatus for forming an RLL code which can perform a control to eliminate a DC component without an increase in number of bits. Natural numbers m, n, d, k, and k, satisfy conditions such that m<n and d<k<k.sub.1, an input data sequence by binary codes is divided into blocks each consisting of m bits and is sequentially converted to code words every one or a plurality of blocks at a ratio of (m bits:n bits) by a predetermined conversion rule in a manner that after completion of the conversion, the number of bits "0" between neighboring bits "1" is equal to d in minimum and k in maximum.

Abstract: The present invention is directed to a method and apparatus to correct errors in bits of binary coded data transmitted from a first electronic device to a second electronic device by providing a frame of bits which contains a plurality of transmission code constrained bytes of bits; determining a first parity for the bytes of the frame; determining a balance for each of the plurality of code constrained bytes; grouping the bytes into words, wherein each word has a balance formed from the balance of each of the bytes in the word, determining a second parity from the group and word balances; transmitting the frame, the first parity and the second parity of the frame to the second electronic device; the second electronic device redetermines from the transmitted frame a redetermined first parity and a redetermined second parity; the second electronic device compares the transmitted first parity to the redetermined first parity to determine a bit location of an error in said bytes; the second electronic device com

Abstract: An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 101010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialization and disconnect sequences.

Abstract: Source data each consisting of m-bits can be converted into conversion codes each consisting of n (>m) bits with ease, and reverse conversion thereof can be performed with ease. The code conversion and the reverse conversion can be characterized in terms of a series of tables.The current input source data and the next input source data are respectively taken in by registers. Whether or not the run length at a connecting portion between consecutive source data satisfies conditions is determined by a control unit, and a table to be used is selected to finally obtain a conversion code.

Abstract: The present invention relates to an apparatus for modulating input data by encoding the data to a run length limited (RLL) code data satisfying the (d,k,m,n) condition and decoding the modulated data, in which d is a minimum run length, k is a maximum run length, m is the bit number of input code data, n is the bit number of transmission code data, and the encoding and decoding apparatus according to the present invention comprises a look-up table (LUT) for encoding input parallel m-bit code data to r-bit code data in which r is not less than m and less than n, a post-encoder for encoding the encoded r-bit data to an n-bit transmission code data, a pre-decoder for decoding the input n-bit transmission code data to the r-bit code data according to the minimum run length condition, and a LUT for decoding the decoded r-bit code data to the original m-bit code data, by which the transmission code length is shortened according to the minimum run length condition so that the memory size required for encoding and de

Abstract: A method and apparatus are described for coding a frame of N-bit bytes into a frame of coded M-bit bytes wherein M>N>0 and wherein said frame has a frame boundary including the steps of storing a frame of M-bit bytes; providing a code containing a set of M-bit bytes which is a subset of all possible M-bit bytes; for each of the 2.sup.

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.

Abstract: Apparatus and methods for transmitting and receiving a digital data signal. At the transmitter side, packets of p m-bit digital words in a digital signal are error protection encoded to produce error protection encoded packets of n m-bit digital words making up an error protection signal, where n>p. The error protection encoded packets are converted into converted packets of digital words to form a channel encoded signal, which signal is supplied to a transmission medium. The conversion involves use of a generator for supplying a fixed auxiliary packet of n digital words; a calculation unit for calculating in a Galois field GF(2.sup.m) a converted digital word in accordance with the formula DW.sub.i +.alpha..FW.sub.i, where DW.sub.i and FW.sub.i are the binary values corresponding to the i-th digital words in the packet to be converted and the auxiliary packet, respectively, .alpha.

Abstract: An apparatus for encoding a digital signal includes switching means for alternately outputting the digital signal from first and second output terminals at every bit. A first converting means converts the digital signal output from the first output terminal to a signal which will be DC free after NRZI conversion is carried out. A second converting means converts the digital signal output from the second output terminal to a signal which will be DC free. An encoding means is supplied with outputs from the first and second converting means, alternately combining outputs of the first and second converting means at every bit and obtaining a substantially I-NRZI converted digital signal.

Abstract: A method and apparatus for bias suppression which includes a transmitter having a bias suppression encoder and a closed-loop VCO FM modulator and a receiver having a bias suppression decoder and an AC coupled FM demodulator. The bias suppression encoder generates a running sum of an encoded digital data signal as well as the sum of an (N+1)-bit block of an injected digital data signal such that the encoder may invert a block of (N+1)-bits of the injected data signal if both sums are of the same polarity thereby reducing the average DC bias of the encoded digital data signal. The encoded data signal is modulated using a closed-loop VCO FM modulator with the DC tracking effect minimized as compared to modulating the non-encoded signal directly.

Abstract: A sequence of m-bit information words is converted to a modulated binary signal. For each received information word from the sequence an n-bit code word is delivered. The delivered code words are converted to the modulated signal. When one of the code words is assigned to an information word to be converted, this code word is selected from a set of code words that depends on a coding state which is related to a digital sum value at the end of the modulated signal that corresponds to the previously delivered code word. From at least one of the digital sum values, a first or a second coding state of a pair of coding states of a first type is determined. Which of the two coding state of the pair is determined depends on the information word that corresponds to the previous delivered code word. The sets of code words belonging to the pairs of coding states of the first type contain no code word whatsoever in common.

Abstract: Digital modulating method and apparatus are provided which converts m-bit data codes, in sequence, into digital modulation codes each consisting of n channel bits (n>m) to form a modulation code sequence using connection codes. Bit patterns of portions of the modulation code sequence and the connection codes are changed or additional bit patterns are inserted into the modulation code sequence so as to meet given conditions of a minimum transition interval, a maximum transition interval, and a Digital Sum Value. Demodulating method and apparatus performing a reverse modulation operation are also described.

Abstract: A method for encoding a sequence of 16 bit digital data words into a sequence of 17 bit codewords in consonance with predetermined minimum zero run length (d), predetermined maximum zero run length (G) and maximum interleave zero run length (I) coding constraints of (d=0, G=6/I=7) for recording upon a magnetic medium within a magnetic recording channel is disclosed. The method includes dividing the 16 bit data word into an 8-bit A byte: a1, a2, a3, a4, a5, a6, a7, a8; and an 8-bit B byte b1, b2, b3, b4, b5, b6, b7, b8; separately testing the A and B bytes for violation of coding constraints, generating P and Q code bytes from the A and B bytes and inserting a center bit C of value one or zero between the P and Q code bytes to form the 17 bit codeword of a form p1, p2, p3, p4, p5, p6, p7, p8, C, q8, q7, q6, q5, q4, q3, q2, q1, in a manner minimizing hardware logic implementation.

Abstract: A data conversion method, wherein a sequence of first r-bit datawords is divided into groups of x bits where x is the least common multiple of r and m, an arbitrary first dataword selected from x/r groups of first datawords is divided into x/m, an m-bit second dataword is formed by appending r/(x/m)-bit data, obtained by dividing the first dataword into x/m, to the LSB or MSB side of one or other of the non-divided first datawords, and the word-converted m-bit second dataword is converted to an n-bit codeword (m<n).

Abstract: A method for encoding binary data for transmission over a serial link as a ternary code. Binary data is received and mapped into a binary code. The binary code is translated into a ternary code, and the ternary code is transmitted over the serial link. The ternary code is selectively inverted according to a predetermined protocol such that the serial link maintains a time-averaged zero DC balance.

Abstract: A method of coding, and a coder, using a code in which data words are assigned to code word pairs in a selective manner, so that the value of a data word error resulting from inversion of a bit in a code word may be specific to and dependent solely upon the position within the code word of the inverted bit.

Abstract: A method and apparatus generates a channel codeword based on codewords with arbitrary block digital sums. Respective portions of the channel codeword are generated based on respective sets of input symbols, and the channel codeword is generated from the portions in accordance with another set of input symbols. The potions are advantageously codewords, comprising symbols, generated by selecting, for each set of input symbols, a codeword from a codebook and by adapting, as for example by ordering or by inverting symbols in, the codewords to form the channel codeword.

Abstract: A method and apparatus for encoding and decoding m-bit groups of digital data, where m is at least eight, into serial n bit groups such that each encoded serial n-bit group has sufficient data transitions therein to maintain the synchronization of a phase locked loop clock recovery circuit in a high speed serial link of a communication path. Further, this method and apparatus provides a duty cycle that is within an operational range of the ideal 50 percent, which reduces voltage drift of a.c. coupled high speed serial data links, or reduces thermal drift of optically coupled high speed serial data links.

Abstract: A plurality of (n-p)-bit non-correlation data having no correlation between data each are added with a common p-bit data to thereby obtain a plurality of n-bit data having data correlation. The plurality of n-bit correlation data are processed using data correlation therebetween so that even a data train having no correlation can be processed effectively. A plurality of m-bit non-correlation data having no correlation between data are separated into a plurality of blocks including (n-p)-bit data and n-bit data. A p bit among the separated n-bit data is added to the separated (n-p)-bit data to thereby obtain a plurality of n-bit data having data correlation, in both cases n and m being an integer more than 2 and p is an integer smaller than n.

Abstract: The present invention is an apparatus and method for increasing the density of run-length-limited (RLL) block codes without increasing error propagation. By inserting a number of uncoded bytes (M) between each coded byte, the coding density is thereby increased. Starting with an RLL code with a block length (I) which is, for example, a multiple of 8, a number (M) of uncoded bytes may be inserted between each coded byte. The resulting density is: (I+8M)/(J+8M), wherein the resulting k constraint, of the (d,k,l) constraints is increased by 8M, and the resulting l constraint is increased by 4M. For example, starting with an RLL code having a coding density of 8/9 (I=8, J=9) and constraint set of (0,4,4), inserting one uncoded byte between each coded byte (M=1) results in a coding density of 16/17 which is 5.88% greater than the original 8/9 coding density. The constraint set is also increased to (0,12,8), where k is increased by 8 and l is increased by 4.

Abstract: A data conversion apparatus which converts an m-bit data into plural n-bit codes having different CDS values to obtain an intense spectrum at frequencies with a period of p bits has a CDS control signal generator which generates data of a known CDS in codeword with one period which is the least common multiple (q) of n and p, an error detector which detects differences between values of charge in codeword at intervals of (r) bits (where r is the greatest common divisor of n and p) and the data of the known CDS in codeword and detects a sum of absolute values (.DELTA.CDS) of the differences, and a minimum value hold circuit which selects a code having the smallest sum of absolute values (.DELTA.CDS), from the plural n-bit codes having different CDS values.