Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30.

Abstract: A modulator includes a replacement processing unit which replaces a part of main information code-converted in a main information converter with specific information code-converted in a specific information converter and a direct-current component suppress processing unit which performs direct-current component suppress processing for the main information which has undergone the replacement processing in the replacement processing unit. The direct-current component suppress processing can be performed for the main information after the replacement processing of the main information with the specific information to prevent deterioration in direct-current component suppress characteristics due to the replacement processing.

Abstract: A codeword for use in a communication channel is provided. A first segment of the codeword includes a plurality of bits having a running digital sum (RDS) and a second segment includes a plurality of bits based on the RDS of the first segment.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A method and apparatus are provided for encoding and decoding digital information. A sequence of data words is received, wherein each data word has a running digital sum (RDS). The sequence of data words is encoded into a sequence of corresponding code words, which has a current RDS. For each data word a binary symbol is added to the data word and the data word is selectively complemented as a function of the RDS of the data word and the current RDS of the sequence of code words to form the corresponding code word.

Abstract: A system and method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium, includes encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, each set of P symbols being selected to reduce full-swing transitions and to perform DC balancing between successive digital signal transmissions. The system and method further includes transmitting the sets of P symbols over the single transmission medium. Clock data recovery and comma insertions may additionally be provided in alternate configurations.

Abstract: A method of generating an 8B/10B-like code bit sequence that is similar to an 8B/10B code may include: generating a parallel pseudo random bit sequence having N bits wherein N is an integer and N?2; and transforming the parallel pseudo random bit sequence into a parallel first bit sequence that is similar to an 8B/10B code, a number Q of consecutive “0”s or “1”s of the first bit sequence being Q?M1, wherein Q and M1 are integers and M<N. Devices related to such a method are also provided.

Abstract: Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.

Abstract: Provided are a rate 13/15 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a predetermined rate-13/15 MTR code in which 13-bit data corresponds to 15-bit data; outputting input 13-bit data as a 15-bit codeword according to the rate-13/15 MTR code; checking whether codewords satisfy a predetermined constraint condition by connecting the 15-bit codeword and a subsequent 15-bit codeword; and converting specific bits of the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition. The rate-13/15 MTR (j=2, k=8) code includes: 8192 codewords obtained to prevent the number of consecutive transitions from becoming 3 at code boundaries in a modulation coding process. Data can be reliably reproduced with high write density, and a large amount of data can be stored in and reproduced from a magnetic recording information storage medium.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: A data-demodulating method for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

Abstract: Blocks of input data are received. The input data comprises packets of information words. The packets are preceded and followed by control words. A master transition is appended to the beginning of each block to form a respective frame for transmission. The master transition has a sense that depends on whether the block contains any control words. Additionally, for each block that contains one or more control words, a TYPE word indicating a structural property of the block is generated, the block is condensed to accommodate the TYPE word, and the TYPE word is inserted into the block. The coding method provides a very low overhead (3.125%) when implemented as a 64b/66b code.

Abstract: A method of modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: Apparatus for modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: When recording data on a record carrier of the DC content of the data recorded is important in order to allow accurate reproduction of the data. The Digital Sum Value represents the DC content; the Digital Sum Value can be controlled by replacing code words at the output of an encoder by code words that can never occur during encoding. The replacement code word has different parity than the code word it replaces. The resulting stream of code words is subsequent encoded using an NRZI coder, so that the change in parity resulting from replacement code word results in a change of polarity of the NRZI output. The replacement code word can thus be used to change the polarity of the NRZI output to keep the Digital Sum Value low.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: Output data of a multiplexer 11 is EFM-modulated by an EFM modulator 12. In the EFM modulation, merging bits that satisfy run length limit conditions Tmin=3 and Tmax=11 are selected. Among them, merging bits that converge DSV are selected. A run length controlling portion 13 detects a particular data pattern that causes DSV to increase as large as a data read error takes place and controls the EFM modulator 12 so that the run length limit conditions of the EFM are loosened. As a result, an increase of DSV is suppressed. Data is reproduced from a data recording medium on which the data has been recorded in such a manner and the reproduced data is decoded. The decoded data is re-encoded so as to record it to another recoding medium. When the data pattern is re-encoded, DSV increases. As a result, data cannot be correctly reproduced from the other recording medium. Consequently, a copying operation can be prevented.

Abstract: A fast look-ahead path modulation apparatus, used in a recording medium modulation apparatus, reduces computation time during its look-ahead path modulation procedure. It is based on different selection criteria of predetermined states, paths and characteristics of modulation. Accordingly, the apparatus drastically reduces the amount of computation in a regular look-ahead path modulation apparatus. It also reduces hardware costs of the recording medium modulation apparatus and increases efficiency.

Abstract: An EFM data decoding method and apparatus thereof for optical disk system is provided. According to the method, a 14-bit data complying with the EFM modulation criteria but failing to correspond to a 8-bit data based on an EFM decoding table is transformed successfully by looking up an expanded EFM decoding table. The expanded EFM decoding table includes probable 8-bit data corresponding to the erroneous data complying with the EFM modulation criteria. Reliability of data reading is thus enhanced in the present invention.

Abstract: The DVD recording method is intended to increase the number of cycles allowed for recording on the disk an enormous number of times. This method comprises generating two data streams by using a plurality of code mapping variants prepared for coding input data, quasi-randomly selecting one of the plurality of code mapping variants, if absolute DSVs of the two streams are substantially equal, and converting into recording code sequences. This method prevents deterioration of the disk particularly in the management area and increases the number of cycles allowed for rewriting.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A data encoding system for a data stream comprises a data dependent scrambler that receives the data stream including K m-bit symbols, that selects a seed based on the K m-bit symbols, that scrambles the K m-bit symbols using the seed and that outputs a codeword including the scrambled K m-bit symbols and the seed. A DC control module receives a plurality of the codewords from the data dependent scrambler, selectively inverts selected ones of the plurality of codewords to reduce a difference between a total number of zeroes and total number of ones in the plurality of codewords and outputs an encoded data stream.

Abstract: A rate 7/8 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a rate-7/8 MTR code for inputting 7-bit data and outputting a predetermined 8-bit codeword; checking whether codewords satisfy a predetermined constraint condition by connecting the 8-bit codeword and a subsequent 8-bit codeword; and if the codewords do not violate the constraint condition, not converting the codewords. The decoding method includes: checking whether the codewords satisfy a predetermined MTR constraint condition by connecting a current 8-bit codeword c(k) and a subsequent 8-bit codeword c(k+1); if the codewords violate the constraint condition, converting the codewords, and if the codewords do not violate the constraint condition, not converting the codewords; and decoding each converted 8-bit codeword into 7-bit data using a predetermined MTR code.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint, wherein at least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A system and a method for synchronizing running disparity values in a first computer and a data demapping device are provided. The method includes generating a plurality of data characters and a synchronization control character. The method further includes iteratively determining a first running disparity value based on each character of the plurality of data characters and the synchronization control character. The method further includes encapsulating a first plurality of data characters and the synchronization control character from a computer into at least one GFP data block and transmitting the GFP data block to data demapping device. The method further includes decoding the GFP data block to obtain the plurality of data characters and the synchronization control character and iteratively determining a second running disparity value based on each character of the plurality of data characters and the synchronization control character.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: An encoding system for encoding digital data for transmission through a communication channel is described, which includes a DCF encoder and a parity encoder operatively coupled to the DCF encoder. The DCF encoder is adapted to receive a first data sequence, and to generate a first DCF code word and a new running digital sum as functions of the first data sequence and a pre-existing running digital sum, wherein the new running digital sum is limited to a maximum absolute value. The parity encoder is operatively coupled to the DCF encoder, and adapted to receive the first DCF code word from the DCF encoder, and to generate a first interleaved parity code word as a function of the first DCF code word, and to provide the first interleaved parity code word to a channel.

Abstract: The present invention relates to a method for coding a data stream, in which the digital sum value of the coded data stream should be close to zero and two alternative code words can be used for the coding at least for some of the possible data values. It is the object of the invention to propose a method for coding a data stream which provides for simple coding of the data stream while at the same time ensuring a digital sum value close to zero. According to the invention, the object is achieved by a method in which the digital sum value of the coded data stream is determined, this value is compared with a first or a second boundary value in dependence on the polarity of the coded data stream and a received data value is coded by a first or a second code word belonging to the respective boundary value in dependence on the result of the comparison.

Abstract: A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code(d, k; m, n: r) having a basic code length of n bits. A sync signal is added to a recieved train of codes after a minimum run, the sync signal having a pattern that breaks a maximum run. The pattern is repeated twice continuously, and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in the termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects and said expansion objects are manipulated according to control information programmed to produce a set of expanded output data objects.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: A method and apparatus are provided for encoding digital information. A sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: An information encoding apparatus for encoding N pieces of information, the information encoding apparatus includes a scrambling pattern generation section for generating M scrambling patterns (N>M?1; where M and N are each an integer); a scrambled information generation section for applying, to each of the N pieces of information, one corresponding scrambling pattern among the M scrambling patterns so as to generate N pieces of scrambled information; and an encoded information generation section for supplying the N pieces of scrambled information with N parities, respectively, so as to generate encoded information. Each of at least one of the M scrambling patterns is applied to two or more of the N pieces of information.

Abstract: The present invention relates to a modulation apparatus and method and a DSV-control-bit generating method for suppressing an increase in circuit size of the modulation apparatus. When an input data stream is supplied to a DSV control bit determination unit 31, the DSV control bit determination unit 31 determines a DSV control bit to be inserted into the input data stream. Upon supplying the input data stream to the DSV control bit determination unit 31, the input data stream is simultaneously supplied to a delay processor 32. The input data stream is delayed for a predetermined delay time and supplied to a determined-DSV-control-bit insertion unit 33. The determined-DSV-control-bit insertion unit 33 inserts the DSV control bit determined by the DSV control bit determination unit 31 into a predetermined position of the input data stream supplied by the delay means and supplies the input data stream containing the DSV control bit to a modulator 34.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data words, a number of intermediate sequences by combining mutually different digital words with a data word, scrambles the intermediate sequences to form alternative sequences, translates each alternataive sequence into a (d,k) constrained sequences, measures for each (d,k) constrained sequences, not only an inclusion rate of an undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having a small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV, smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: A system and method of forming RLL coded data streams with separator blocks has an RLL encoder and a channel encoder. The input code word is divided into data portions and a separator portion. The data portions are inserted into an output codeword without encoding. Each data portion is separated from a next data portion by a space. The separator portion is encoded into non-zero separator sub-matrices, which are stuffed into the spaces between the data portions. The separator portions and the data portions may be separately permuted without exceeding a maximum number of consecutive zeros.

Abstract: A method of and an apparatus for modulating data to be resistant to channel distortion. A space extending encoder performs a first code transformation to extend a run length of digitized data to a predetermined length and outputs the space-extended data. A multiplexer multiplexes the space-extended data and data transformed by a predetermined second code transformation. A format converter converts the multiplexed data into a predetermined format which is suitable for writing to a recording medium. The apparatus and method enable recorded data to be resistant to channel distortion, enable the data to be recorded with increased recording density, and enable the data written to the recording medium to be reproduced with improved reliability.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method may comprise encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is formed to reduce full-swing transitions between successive digital signal transmissions.