Abstract: Methods and apparatus are described for performing a variable sample rate conversion. A difference between a first sample rate associated with a first signal and a second sample rate associated with a second signal is tracked. A sample rate conversion ratio is adjusted in response to the difference. One of the first and second sample rates is converted using the conversion ratio.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values (xn), output values (yk) of an output signal are produced. If the frequency of the output signal is greater than the frequency of the input signal and the shape of the output signal essentially corresponds to the shape of the input signal, according to the invention the difference between a first and a second input value (xn, xn−1) subsequent to this is determined, interpolation values (PO . . . PN) of an interpolation progression (p) are scaled in dependence on the difference determined and output values (yk) in each case are produced by addition of the first input value (xn) to a scaled interpolation value (PO . . . PN).

Abstract: A table-driven, integer-based method for approximating down sampling of wave data is disclosed. This method provides an efficient approximation of the desired down sampled wave data without a significant impact to overall system performance. Integer calculations are exploited by: (1) multiplying all values of ti by a large enough value to include all significant portions of the decimal value; (2) making all values of &Dgr;t integer values; and (3) using integer arithmetic for most calculations of &Dgr;t and ti. The following static integer tables assist in the final calculations: (1) T[ ], where each element contains the value of ti divided by &Dgr;t and multiplied by a large enough value, M, to place all significant decimal values to the left of the decimal; and (2) D[ ], where each element contains the number of samples of San to drop before arriving at a useable San and San+1 pair.

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: A method for time scale modification of a digital audio signal produces an output signal that is at a different playback rate, but at the same pitch, as the input signal. The method is an improved version of the synchronized overlap-and-add (SOLA) method, and overlaps sample blocks in the input signal with sample blocks in the output signal in order to compress the signal. Samples are overlapped at a location that produces the best possible output quality. A correlation function is calculated for each possible overlap lag, and the location producing the highest value of the function is chosen. The range of possible overlap lags is equal to the sum of the size of the two sample blocks. A computationally efficient method for calculating the correlation function computes a discrete frequency transform of the input and output sample blocks, calculates the correlation, and then performs an inverse frequency transform of the correlation function, which has a maximum at the optimal lag.

Abstract: A vehicular audio system receives audio inputs from audio sources and a radio receiver. Analog audio is converted to digital, and digital audio remains natural digital. The receiver front end converts a radio signal to an intermediate frequency then an ADC converts that to a digital signal. The inputs that are converted to digital are selectively mixed with each other and with the natural digital signals. This allows for sounds from multiple sources to be heard simultaneously so that a telephone ring may be provided without requiring background music to be interrupted and for uses such as voice by microphone over a music tape. A reference frequency to the receiver front end of 7.2 MHz is particularly beneficial for noise reduction and consequent mixing of digital audio at 48 KHz, the standard frequency for typical digital audio inputs.

Abstract: An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate.

Abstract: Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats. The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats.

Abstract: A method and apparatus of correcting a data signal sampled at a first rate to a data signal displayed on a video monitor at a second rate is claimed. A data signal is received at a first rate. The data signal is separated into data windows. The minimum and maximum values and positions of data points in data windows are identified relative to a reference, and displayed on a video monitor.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: Systems and methods that encode and decode data in a manner that limits error propagation by parsing a data word of length n into a predetermined number of data blocks, individually encoding each data block into a single associated code block, and then combining each of the code blocks to form a resulting code word of length (n+1), resulting in a code rate of n/(n+1). By parsing and encoding the data word in this manner, errors that occur with respect to one or more bits of one code block will not be propagated throughout an entire data word during the decoding process.

Abstract: Apparatuses and methods for decoding a bit stream of variable-length and fixed-length codewords representing encoded digital content. A decoder includes a memory for storing microinstructions that control the decoder. The decoder further includes a first barrel shifter for extracting a first bit field from the bit stream, a position of the first bit field being specified by the microinstruction, and a second barrel shifter for extracting a second bit field from the bit stream, a position of the second bit field being specified by the microinstructions. A microprogram counter keeps an address of a currently-executing microinstruction of the microinstructions, where a next state of the microprogram counter is determined by the microinstructions and the first bit field. A data converter modifies a value of the second bit field according to the microinstructions. A data storage stores either data in the microinstructions or an output of the data converter as decoded data values.

Abstract: A data converter includes first and second input signal paths receiving an input signal having an input frequency, the first input signal path dividing the input frequency by a first divisor and the second input signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first input signal path and an output from the second input signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and a current state of the control signal and selectively resets the state of the control signal to set the selector output frequency to a desired frequency.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: A method and apparatus enabling the substantially concurrent operation of multiple decimators within a digitizing measurement device such as a digital storage oscilloscope (DSO), wherein the multiple decimators provide multiple processed sample streams that may be used for a composite presentation of input signal data.

Abstract: A sample rate conversion system developed to implement a rate change of M/N using a very efficient design implementation. The sample rate conversion system of the present invention is implemented as a CIC-based interpolating sample rate converter with noise-shaped control of the N value. For a decimator, noise-shaped control of the M value is utilized. In the interpolator, the N value is the correct value on average, but demonstrates instantaneous errors (“non-uniform” resampling) that are corrected through noise-shaping. The CIC SRC implementation capitalizes on the fact that the outputs of the CIC that are discarded during downsampling need not be calculated by the CIC in the first instance. The combination of the computational simplicity of CIC SRC with noise-shaped, non-uniform resampling performs the sample rate conversion very economically and facilitates conversion between a plethora of sample rates at the input and output without requiring the various filters to be explicitly formulated.

Abstract: A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.

Abstract: Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: A resampler is used to convert an input digital signal sequence having an input sampling rate into an output digital signal sequence having an output sampling rate (fout). An estimating unit estimates the sampling rate ratio between the input sampling rate and the output sampling rate (fout) and estimates the set point phase of the output signal sequence in observation intervals whose observation length is variable. A controlling system compares the actual phase of the output signal sequence with the set point phase and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio and the deviation of the actual phase from the set point phase. An interpolator interpolates the input signal sequence for generating the output signal sequence at sampling times whose location in time is predetermined by the control signal (RTC,k).

Abstract: In an RBW filter, a bandwidth is set so as to selectively pass a frequency component of only a desired signal bandwidth of the measured signals that have been frequency converted into a normalized intermediate frequency signal. A waveform detector detects a signal that passes through the RBW filter. An A/D converter samples the signal detected by the waveform detector at a predetermined sampling rate at which a Nyquist frequency is within the frequency bandwidth of the RBW filter, thereby converting the sampled signal into digital data. A data storage section stores the digital data converted by the A/D converter. A signal processing section re-samples the digital data stored in the data storage section so as to reproduce a bandwidth of the detection signal of the waveform detector, thereby generating arbitrary time data.

Abstract: A DA converter includes fs detection means for detecting an input sampling frequency fs of digital data by using a sampling clock LRCK and a master clock xfso, an oversampling digital filter for oversampling the digital data on the basis of the input sampling frequency fs, fs change detection means for detecting a change in the input sampling frequency fs, and mute control means for muting the data to be DA-converted on the basis of the detection result of the fs change detection means.

Abstract: A resampler converts a digital input sequence with an input sampling into a digital output signal sequence with an output sampling rate. An estimation device estimates the sampling rate ratio between the input sampling rate and the output sampling rate and the desired phase of the output signal sequence in an observation interval with a predetermined length of N samples of the output signal sequence, the observation intervals overlapping in the ratio 1:6. A control device compares the actual phase of the output signal sequence with the desired phase and, in a manner dependent on the estimated sampling rate ratio and the deviation of the actual phase from the desired phase, generates a control signal for in each case N/6 samples of the output signal sequence. An interpolator interpolates the input signal sequence for the purpose of generating the output signal sequence at sampling instants whose temporal position is predetermined by a control signal.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A bandwidth disparity often exists between the front side bus bandwidth and the memory interface bandwidth. The invention effectively increases the bandwidth of a memory interface bandwidth for increasing central processing unit performance. In one aspect, data is buffered by a memory controller hub and compressed by dropping data elements if repetitious data elements appear in a data stream. The dropped data elements are indicated by tagging a previous data element for later recovery. In another aspect, tagging is provided by modifying error correction code bits of the tagged data element or by modifying the data elements. In another aspect, dropped data elements are detected by identification of an error correction code, the dropped data elements reinserted into the data stream, and the data buffered before being presented to a front side bus.

Abstract: A method comprising identifying a sample rate of received audio content, receiving a conversion sample rate, and converting the received audio content to the received conversion sample rate. Wherein the conversion comprises utilizing a repeating sequence of packets where all but one of the packets of each sequence are truncated to a whole number of samples, while the remaining packet is rounded up to the next whole number of samples if the conversion fails to resolve packet size to a whole number.

Abstract: An integrated analog to digital and sample rate converter 206 includes sampling circuitry 207 for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter 208 removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry 209/210 resamples the filtered stream of samples output from leaky integrator filter 208 to generate an output stream of samples at a second rate.

Abstract: Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address contention initiating the next data subblock. Iterative Turbo decoders with MAP decoders use such quasi-parallel interleavers and deinterleavers.

Abstract: A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second umanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Abstract: Data compression techniques reduce a number of encoding words for compressing data. One technique is to assign a common encoding word to a group of data whose activation sequence is pre-selected. Another technique is to assign an encoding word to a pair of converted data. Yet another technique is to assign an encoding word that is indicative of the length of the repletion in the converted word. The above assignments substantially reduces a number of encoding words for the converted words in a process of data compression.

Abstract: An analog to digital converter may achieve an output sampling rate that is not an integer multiple of the system clock. This may be done without using the conventional phase-locked loop circuit that generally requires a longer design time, more testing, and more silicon area. A pseudo clock may be generated from the system clock in which some of the system clock pulses are disabled to achieve a pseudo clock with the desired effective frequency.

Abstract: A sample rate conversion method and apparatus is disclosed to convert an input data stream having an input sample rate to an output data stream having a desired output sample rate with a preselected accuracy up to a given band limit, comprising constructing a cascading filter system of one or more stages, each stage having one or more filters, and each filter having a filter length such that the cascading filter system meets the preselected accuracy of the desired output sample rate, wherein each filter is constructed in the space of band limited functions, and convolving the input data stream with the cascading filter system to generate the output data stream with the desired output sample rate.

Abstract: A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: There is disclosed apparatus (106) for accessing items of information. The apparatus (106) comprises sixteen memory banks (202) and an address generator (204). Each of the sixteen memory banks (202) stores items of information associated with and corresponding to respective symbols of a sub-set of the symbols. These sub-sets of symbols are mutually exclusive and together comprise a set of symbols. The items of information of the sixteen memory banks (202) together constitute the whole of the items of information associated with and corresponding to the respective symbols of the set of symbols with no duplication of the items of information. The address generator (204) simultaneously generates sixteen addresses for the respective sixteen memory banks (202) in response to one input address, wherein the memory banks (202) output sixteen items of information associated with and corresponding to the respective symbols within a 4×4 neighbourhood of the symbol corresponding to said input address.

Abstract: The present invention relates to a converter for converting a digital input signal (1) into a digital output signal (3) using a set of filtering coefficients. The converter comprises filtering means effecting a filtering function and producing the set of filtering coefficients from phase differences (2) between a sample of the digital output signal and samples of the digital input signal, the filtering function being defined by a set of polynomials. The filtering means also comprise a memory (52) for storing coefficients of the polynomials, and means (53) of calculating the set of filtering coefficients from coefficients of the polynomials and phase differences. Such a converter allows a large number of format conversions, while having limited memory resources.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: In a data transmitter having a data encoder, an encoder mode is detected. Thereafter, an excluded codeword output by the encoder operating in the encoder mode is identified. Next, a selected bit in the excluded codeword caused to have a predetermined value to produce a non-excluded codeword. Finally, the excluded codeword is substituted with the non-excluded codeword, wherein the non-excluded codeword is selected to mitigate effects of a decoding error in a receiver associated with the excluded codeword.

Abstract: A wireless telephone system having a plurality of wireless handsets and a base unit, the base unit having a base transceiver. Each handset has a handset transceiver for establishing a wireless link over a shared channel with the base unit via the base transceiver, wherein the base transceiver transmits to a handset transceiver a first signal representing successive symbols at a first symbol rate. The handset transceiver has a receiver and a transmitter, and a local clock signal generator that provides clock signals at a local clock frequency. The receiver receives samples representing the first signal, and generates symbol error measurements used to cause a receiver interpolator to produce, in response to the received samples, samples taken at times synchronized to the successive symbols of the first signal.

Abstract: To convert a 12-bit data word into an 18-bit code word, the 12-bit data word is divided into the 8 high-order bits and the 4 low-order bits. The 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits, thereby creating an 18-bit code. This enables conversion using small-scale conversion tables.

Abstract: A resampler (1) is used to convert a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout). An estimating unit (11) estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and a setpoint phase of the output signal string (Sout). A regulating unit (12) compares an actual phase of the output signal string (Sout) to the setpoint phase, and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and a deviation of the actual phase from the setpoint phase. An interpolator (7) interpolates the input signal string (Sin) for producing the output signal string (Sout) at sampling times whose temporal position is determined by the control signal (RTC,k).

Abstract: Disclosed is a data converter and a method for converting a digital audio stream representing an analog signal that has been sampled at a certain rate. The circuit includes a divider that receives a clock signal associated with the digital audio stream and divides the clock signal by a selectable division factor. The division factor is set according to divider control signals. At the output of the divider is provided an internal clock signal. A frequency detection circuit receives the signal from the output of the divider, and the frequency detection circuit detects the original sampling rate of the audio signal based upon intrinsic characteristics (e.g., MCLK to LRCK ratio) of the digital audio stream.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: A method for providing a multi-stage filter on an input stream of digital data. In the method, the input stream of digital data is operated on with a first polyphase filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a second polyphase filter routine. An optimizing indexing procedure is applied in performing instructions of the routines so as to execute fewer instructions that do not generate intermediate data on which the output stream of data is based.

Abstract: A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: A comb filter has series connected integrators to which is fed a digital data stream at a high sampling rate in order to yield a digital data stream at a low sampling rate. The most significant bits of the digital data stream are reset in the first and second integrators, the resetting of the bits in the first integrator being stored in a counter. The counter reading of the counter is fed into the most significant bits of the last integrator at a reset time.