Abstract: A signal is converted from a first sampling rate to a second sampling rate by dividing the signal into sample blocks and resampling the sample blocks at a sampling rate that is no higher than a maximum of the first sampling rate or the second sampling rate. The signal may be divided into sampling blocks by dividing the signal into a greatest common factor of the first and second sampling rates of sample blocks per second, wherein a respective sample block includes the first sampling rate divided by the greatest common factor, of samples.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: Signal processing apparatus is described in which at least two sets of automated signal processing functions are controlled by stored automation commands, at times dependent upon at least two respective timecode signals which may each be associated with a respective source signal supplied to the signal processing apparatus.

Abstract: Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Abstract: A transmitter and method is provided for digitally upconverting a baseband digital signal to a modulated intermediate frequency (IF) digital signal and sigma-delta modulating the IF digital signal. The baseband digital signal is split into N phases, as can be accomplished using a polyphase interpolation technique (polyphase filter), and modulated. The modulated N phases are not recombined and each phase is further modulated, as can be accomplished using a digital-to-digital sigma-delta modulator that generates digital output signals at the same rate. A high speed digital multiplexer multiplexes the digital output signals into a single bit stream at a higher rate for subsequent power amplification and RF transmission.

Abstract: A system and methods to convert a digital bit stream to analog values without previous knowledge of the sample rate of the incoming digital bit stream has been achieved. The system comprises a sample rate measurement device being able to measure the sample rate out of the incoming digital bit stream. Another device is removing all bits, which are not required for the digital to analog conversion from the incoming bit stream. The measured and calculated sample rate is added to the “cleaned” bit stream and a digital to analog conversion device is performing the conversion using the sample rate which has been added to the bit stream.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: Audio data decoded in an MPEG system to be stored in a storage unit is supplied to an audio output via a filtering processing. For performing the filtering processing, presentation time interval of respective audio data is changed to conform to a user's designated playback speed, and the decoded audio data stored in the storage unit by being synchronized with the changed presentation time interval is written on an input queue in the set unit. A TSM algorithm is performed in the frame unit with respect to the audio data of the input queue to decrease the quantity of the audio data when the designated playback speed is faster than a normal playback speed or to increase it when the designated playback speed is slower than the normal playback speed, in accordance with a value of the designated playback speed. The TSM audio data is transferred to a middle queue.

Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, includes a storage device 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the writable address, and an interpolation processing unit 14 for interpolating the data read-out from the storage device 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a writable address and a readable address in the storage device 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output timestamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: A high-speed transmitter for digital data having a variable data rare, the transmitter comprising a convolutional encoder, adapted to generate, for each group of k input bits in a bitstream, n coded output bits, such that k and n are integers, n equal to or greater than k, and at least one of k and n is variable responsive to the variable data rate of the transmitter; and a modulator, coupled to map the output bits generated by the encoder to a constellation of M symbols for transmission by the transmitter, M an integer, which is variable responsive to the variable data rate of the transmitter; and wherein for a given rate Rs of transmission of the symbols by the transmitter, the variable data rate Rb is given by Rb=Rs*log 2(M)*Rc, wherein Rc is a code rate equal to k/n.

Abstract: A digital video signal processing system monitors the rate of change of the digital video signal to detect large rates of change that indicate the presence of an object edge in the video image. Upon detection of such an edge, the digital signal is sampled at a variable rate so that more sampling is performed immediately before and after the sudden change in the signal and less sampling is performed during the change. The result is that the edge in the video image occupies less pixels and, therefore, is more clear and defined that would be the case otherwise. Consequently, the appearance of the video image is enhanced. This can be considered as the digital analogue of analog H-sweep velocity modulation.

Abstract: A receiving apparatus constructed to store data received from a network in a buffer and read the data in the buffer based on a reference clock, has a detecting means for detecting change of a sampling frequency of the data, a first controlling means for controlling to stop writing of the data into the buffer and reading of the data from the buffer in response to an output of the detecting means, a clearing means for clearing the data in the buffer in response to the output of the detecting means, a clock changing means for changing a frequency of the reference clock in response to the output of the detecting means, and a second controlling means for controlling to restart the writing of the data into the buffer and the reading of the data from the buffer in response to the output of the detecting means.

Abstract: An outer encoder and an inner encoder encode subsets of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. The use of a combiner at an outer decoder enables better outer decoding of symbols.

Abstract: A flexible data rate matching method in a 3GPP2 system is disclosed that supports flexible data rate repetition on a physical layer of synchronous cdma2000 in an interleaving process.

Abstract: An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate.

Abstract: Methods of and apparatuses for optimizing quantization noise cancellation in multi-phase sampled MASH ADCs are disclosed. A test signal is combined with quantization noise produced by a delta-sigma modulator. Two parallel adaptive filters (i.e. even and odd filters) are configured to receive respective even and odd samples of a digital output signal of a MASH ADC analog modulator. Adaptive coefficients for the even adaptive filter are derived from correlation results between the even samples of the test signal and associated even samples of the final digital output signal. Similarly, adaptive coefficients for the odd adaptive filter are derived from correlation results between the odd samples of the test signal and associated odd samples of the final digital output signal. Using the adaptive coefficients, the even and odd adaptive filters are able to independently compensate for analog variations in the two paths.

Abstract: Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolatio

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A method and apparatus to estimate a motion using searched motion vectors, and an image encoding system adopting the method and apparatus are provided. The motion between lower level frame data is estimated to obtain search points with minimum Sum of Absolute Differences (SADs). The search points are used as a based motion vector. Searches are performed on both upper level frame data and upper level field data using the based motion vector and search points are obtained with minimum SADs. The search points obtained from the searches on the upper level frame data and upper level field data are used as frame and field motion vectors.

Abstract: A signal receiving circuit receives sample data without an occurrence of discontinuity in the received sample data, even if the number of sample data to be transmitted from a transmitting terminal does not coincide with the number of sample data expected to be received by a receiving terminal. The signal receiving circuit has a converting circuit adapted to perform computations on n1 pieces (n1 is a natural number) of first sample data to be sequentially input and to sequentially produce n2 pieces (n2 is a natural number) of second sample data in response to a clock signal, and has a receiving section adapted to sequentially receive the n2 pieces of the second sample data in response to the clock signal.

Abstract: Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values (xn), output values (yk) of an output signal are produced. If the frequency of the output signal is greater than the frequency of the input signal and the shape of the output signal essentially corresponds to the shape of the input signal, the difference between a first and a second input value (xn, xn-1) subsequent to this is determined, interpolation values (PO . . . PN) of an interpolation progression (p) are scaled in dependence on the difference determined and output values (yk) in each case are produced by addition of the first input value (xn) to a scaled interpolation value (PC . . . PN).

Abstract: A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with the existing software.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence which follows run length limiting rules. The run length limiting rules are changed between RLL(1, 7) and RLL(1, 8) in response to auxiliary information to superimpose the auxiliary information on the sequence of the generated output code words.

Abstract: A method and apparatus to perform sample rate conversion using multiple Multiply-Accumulate (MAC) units are described.

Abstract: The present invention provides a processor including a bit-shift circuit for inputting pieces of data held sequentially in a main register and an auxiliary register, shifting the piece of data bit after bit in accordance with a pointer and a bit count and outputting the shifted data by execution of an unpacking instruction specifying the bit count; a mask circuit for masking data output by the bit-shift circuit in accordance with the pointer and the bit count in the execution of the unpacking instruction; and a pointer-updating circuit for updating the value of the pointer by the bit count in the execution of the unpacking instruction.

Abstract: A sigma-delta ADC includes a higher order infinite impulse response (IIR) filter based on a finite impulse response (FIR) filter and possesses the same functionality as a conventional sigma-delta ADC in terms of noise and swings at the output of the analog integrators. The higher order sigma-delta ADC requires only one analog amplifier however, even though it has a higher order analog integration function.

Abstract: A method and apparatus to perform sample rate conversion using multiple Multiply-Accumulate (MAC) units are described.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A bit-stream converter capable of converting a first synchronous compressed bit-stream of data at a first sampling rate to second synchronous compressed bit-stream frame of data at a second sampling rate is disclosed. The bit-stream converter architecture may include a payload length detector and a zero stuffing unit in signal communication with the payload length detector. The zero stuffing unit is capable of zero stuffing section responsive to the payload length detector detecting the payload length.

Abstract: A converter circuit for converting a double width data bus (transmitting data at a single rate) to a single width data bus (transmitting data at a double rate). The circuit operates with a single clock, using the clock (positive clock) and its complement phase (negative clock) to process a set of even data and odd data. The circuit has a data mixer stage and an XOR stage. Even and odd data are mixed, using multiplexors and the positive and negative clocks, to generate mixed data. An XOR function is performed on the mixed data, using NAND gates. Using NAND gates to perform the XOR instead of a multiplexor ensures synchronous output timing, and ensures that the two stages are fully testable according to any scan-chain test method.

Abstract: A method and device are described for detecting bits in a read signal sampled at a system clock frequency which deviates from the bit frequency. A series of bit-frequency relevant signal values (B12) is computed from the series of system clock frequency-measured sample values (B1, B2, . . . ) as a convolution of the measured sample values having a function centered around the desired sampling instant, which function is the Fourier transform of a predetermined pulse response of the sampling procedure. This pulse response is chosen to be such that the sampling procedure is reliable for bit frequencies up to twice the system clock frequency. To be able to process such high bit frequencies in actual practice, a bit detector (320) according to the invention has two data outputs (321, 322) and one validity output (225). Whenever a computation has been finished, a pulse is supplied at the validity output whose frequency may be maximally equal to the system clock frequency.

Abstract: Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated by interpolation from a table of oversampled values with the oversampling rate lower for outlying lobes of the impulse response.

Abstract: Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

Abstract: On a compression side, from an inputted analog signal 101, points 102a to 102f where a differential absolute value is at a predetermined value or smaller are detected as sample points, and a pair of discrete amplitude data on the sample points and timing data indicative of a time interval between sample points is obtained as compressed data. On an expansion side, amplitude data and timing data that are included in the compressed data are used to obtain expansion data by determining interpolation data for interpolating two pieces of amplitude data, based on the two pieces of amplitude data on two successive sample points and timing data therebetween. Thus, when a signal on a time base is compressed and expanded, the operation can be performed on a time base without frequency conversion.

Abstract: In a wireless local area network (WLAN), receiving or transmitting signals having multiple modulation schemes can require the use of multiple clock rates. Providing these multiple clock rates significantly increases silicon area and power consumption, both of which are highly undesirably in a wireless device. A sequencing interpolator can advantageously reduce the number of clock rates by receiving signals at a first rate and outputting signals at a second rate. The sequencing interpolator can include a multiplexer network that selectively determines which coefficients are applied to certain signals. Coefficients are chosen to ensure that an error in a frequency domain is within a given tolerance. The multiplexer network can be controlled by a counter value. At a predetermined count, the interpolated output signal is discarded and the counter is reset.

Abstract: A device for automatically converting a digital sample sequence X(n) inputted at a first frequency fe and converted into an output digital sample sequence Y(m) at a second frequency fs which is smaller than fe. An interpolator-decimator assembly having a decimation rate equal to &ggr;, selected so as to correspond to the frequency offset fe/fs is based on a polyphased filter having p tables of q elements each, said filter being designed such that samples X(n) are input at the fe frequency and table components are activated according to clocking of a second clock derived from the fe clock and wherein one clock pulse is removed.

Abstract: A system for changing the sample rate of a digital signal precisely such that frequency coherence is maintained. The system uses coupled direct digital synthesizers to establish the phase of a resampled clock compared to the original clock. The system implements precision resampling that changes the sample rate of a sampled data signal, while maintaining the frequency coherence of the sampled signal. A precision phase calculation for the relation between an input clock and an output clock enables the precision resampling.

Abstract: Methods and systems for filtering an analog signal sampled at a very high frequency and outputting a digital signal that has a very low sampling frequency to drive a material metering machine. The high frequency digital input signal is input to a first decimation element, which filters out the noise in the signal introduced by an analog-to-digital (A/D) converter and reduces the sampling frequency of the digital signal to a lower sampling frequency of 1200 hertz. The reduced rate digital signal is input into a second decimation element that contains several decimation filters, which reject the 60 hertz line noise and its harmonics while simultaneously reducing the sampling frequency of the digital signal to 10 hertz. The output of the second decimation element is then passed to a bank of selectable filters with sub-hertz cutoff frequencies to remove the machine noise from the material metering machine.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: A method and device are described for detecting bits in a read signal sampled at a system clock frequency which deviates from the bit frequency. A series of bit-frequency relevant signal values (B12) is computed from the series of system clock frequency-measured sample values (B1, B2, . . . ) as a convolution of the measured sample values having a function centered around the desired sampling instant, which function is the Fourier transform of a predetermined pulse response of the sampling procedure. This pulse response is chosen to be such that the sampling procedure is reliable for bit frequencies up to twice the system clock frequency. To be able to process such high bit frequencies in actual practice, a bit detector (320) according to the invention has two data outputs (321, 322) and one validity output (225). Whenever a computation has been finished, a pulse is supplied at the validity output whose frequency may be maximally equal to the system clock frequency.

Abstract: A Frequency Mapping Coding (FMC) scheme varies the application of error correction redundancy to transmitted data based on the channel transmission characteristics and the likelihood of error resulting from characteristics of the data stream being transmitted over the channel. The FMC is an error correction coding scheme making use of the non-linear feed-back mechanism and variable bit input step size to control redundancy applied. The FMC scheme accommodates the non-symmetrical nature of the SNR in bandwidth limited communications environments such as DSL to allow application of IQ based modulation, such as QAM, to these channels and is flexible for varying channel characteristics.

Abstract: Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.

Abstract: Methods and systems for filtering an analog signal sampled at a very high frequency and outputting a digital signal that has a very low sampling frequency to drive a material metering machine. The high frequency digital input signal is input to a first decimation element, which filters out the noise in the signal introduced by an analog-to-digital (A/D) converter and reduces the sampling frequency of the digital signal to a lower sampling frequency of 1200 hertz. The reduced rate digital signal is input into a second decimation element that contains several decimation filters, which reject the 60 hertz line noise and its harmonics while simultaneously reducing the sampling frequency of the digital signal to 10 hertz. The output of the second decimation element is then passed to a bank of selectable filters with sub-hertz cutoff frequencies to remove the machine noise from the material metering machine.

Abstract: The present invention is directed to a system and method which expands the applicability of subsampling to a larger range of signal repetition rates while reducing the range over which the sample rate must be tuned to accommodate a given signal. The resulting sample sequences are in the correct order, enabling direct display with an ordinary oscilloscope or other instrumentation. In one embodiment, a technique is used such that decimation of the samples also improves the response characteristics of the sensor. The system and method provides for a number of different procedures for sampling a signal of a given length. All other parameters being the same, the system allows more freedom in selecting the sample rate to correctly sub-sample a repetitive signal.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal are presented. In some embodiments, more than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. Some aspects of the invention solve the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. In some embodiments, an error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. One embodiment involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: An encoding device in a data transmission/reception system includes a first convolutional encoder that encodes an outer code, an interleaver that permutes input data, a second convolutional encoder that encodes an inner code, and a muti-level modulation mapping circuit that performs signal-point mapping based on eight-phase shift keying. When the encoding device uses the second convolutional encoder having two or more memories, the first convolutional encoder uses, as the outer code, a code with a minimum output distance greater than the maximum input distance at which the minimum-distance inner code is generated.

Abstract: A table-driven, integer-based method for approximating down sampling of wave data is disclosed. This method provides an efficient approximation of the desired down sampled wave data without a significant impact to overall system performance. Integer calculations are exploited by: (1) multiplying all values of ti by a large enough value to include all significant portions of the decimal value; (2) making all values of &Dgr;t integer values; and (3) using integer arithmetic for most calculations of &Dgr;t and ti. The following static integer tables assist in the final calculations: (1) T[ ], where each element contains the value of ti divided by &Dgr;t and multiplied by a large enough value, M, to place all significant decimal values to the left of the decimal; and (2) D[ ], where each element contains the number of samples of San to drop before arriving at a useable San and San+1 pair.

Abstract: A method for converting sample rates includes obtaining coefficients from a sample rate conversion coefficient table. In this method, the table is generated prior to the real-time sample rate conversion using LaGrange Interpolation based on the ratio of the input sample rate to the output sample rate.

Abstract: When, through a multi-speaker of a DVD audio system, signals are recorded/reproduced using a sampling frequency different for every channel, the quantity of calculation of a filter circuit is reduced. Up-sampling information about whether or not the sampling is carried out before the up-sampling by up-sampling means (2a, 2b) is acquired by up-sampling information detecting means (6). The signal up-sampled is filtered by a halfband filter circuit (3), subjected to loss-less compression, and recorded on a recording medium (8).