Abstract: In a display device including a display panel having two areas and a backlight having two light-emitting sections, a first scanning period, a first blanking period, a second scanning period, and a second blanking period are set sequentially in one frame period, scanning lines in a first area are selected sequentially in the first scanning period, the scanning lines in a second area are selected sequentially in the second scanning period, a second light-emitting section is made to turn on in a first turn-on period set in the first blanking period, and a first light-emitting section is made to turn on in a second turn-on period set in the second blanking period.

Abstract: A semiconductor assembly for a display device comprises a display driver integrated circuit (DDIC) chip and an interposer coupled to the DDIC chip. The DDIC chip comprises a plurality of output pads and a plurality of input pads. Further, the DDIC chip is configured to drive a plurality of data lines of the display device to update an active region of the display device. The interposer comprises a plurality of output pads coupled to the plurality of output pads of the DDIC chip and is configured to be coupled to the plurality of data lines of the display device. The interposer further comprises a plurality of input pads coupled to the plurality of input pads of the DDIC chip pads. Further, a width of the interposer is at least as large as a distance between outermost data lines of the plurality of data lines.

Abstract: A method of displaying an image, a display device, an electronic device and a computer readable storage medium are disclosed. The method may comprise: acquiring an image to be displayed, the image comprising a plurality of layers; superimposing first image information of pixels in each of the plurality of layers, so as to obtain second image information of pixels in an overlaid layer image; arranging the second image information based on a plurality of colors, so as to obtain third image information comprising a plurality of portions; and displaying each portion having the same color sequentially in a preset order of the plurality of colors.

Abstract: The present disclosure provides a shift register circuit, a GOA circuit and a display device. The shift register circuit includes a shift register sub-circuit. The shift register sub-circuit includes a pull-up node, a pull-down node and a touch potential control circuit. The touch potential control circuit is coupled to a touch potential control terminal, an output terminal of the shift register sub-circuit, the pull-up node, the pull-down node and a low level output terminal, respectively. The touch potential control circuit is configured to, under control of the touch potential control terminal in a touch phase, control each of the output terminal of the shift register sub-circuit, the pull-up node and the pull-down node to be coupled to the low level output terminal.

Abstract: Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.

Abstract: A pixel driving circuit for an organic light-emitting diode (OLED) display panel is provided. The circuit includes a restoration module, a compensation module including a storage capacitor, a light-emitting module, and a storage capacitor control module. The restoration module receives a first control signal and a restoration voltage and restores the compensation module and the light-emitting module under the control of the first control signal. The compensation module receives a second control signal, and writes a data signal and compensates a threshold voltage under the control of the second control signal. The light-emitting module receives a third control signal and illuminates under the control of the third control signal. The storage capacitor control module adjusts a capacitance value of the storage capacitor in the compensation module according to different refresh frequencies of the OLED display panel, preventing insufficient charging due to an increasing refresh frequency.

Abstract: A foldable display device according to example embodiments includes a flexible display panel including a first display area having at least partially foldable area and a second display area not having the foldable area, a folding sensor in the first display area configured to detect a folding status of the flexible display panel and output a detecting signal which includes the folding status of the flexible display panel, a scan driver configured to sequentially provide scan signals to at least a part of a plurality of scan lines based on the detecting signal, a data driver configured to provide data signals to the flexible display panel based on the detecting signal, and a timing controller configured to convert input image data into corrected image data based on the detecting signal and control the scan driver and the data driver.

Abstract: Technology for a display source device is described. The display source device can receive a frame start indication from a display panel at a start of a frame. The display source device can align a timing of the display source device to a timing of the display panel based on the frame start indication received from the display panel to obtain frame-level synchronization between the display source device and the display panel. The display source device can send one or more frame update regions to the display panel in accordance with the timing of the display source device that is aligned to the timing of the display panel.

Abstract: The present application provides a gate driving circuit, a display apparatus and a method of driving the same. The gate driving circuit includes a plurality of shift registers, which are divided into a first group of shift registers and a second group of shift registers. An output terminal of an A-th stage of shift register is electrically coupled to an input terminal of a (A+1)-th stage of shift register, an output terminal of a (A+1)-th stage of shift register is electrically coupled to an input terminal of a (A+1+n)-th stage of shift register, a reset terminal of the A-th stage of shift register is electrically coupled to an output terminal of a (A+a+n)-th stage of shift register, and a reset terminal of the (A+1)-th stage of shift register is electrically coupled to an output terminal of a (A+a+n+1)-th stage of shift register.

Abstract: A display device includes: a display panel including: a scan line, a data line, and an emission control line; a pixel including: a plurality of transistors connected to the scan line, the data line and the emission control line; and an organic light-emitting diode driven by the plurality of transistors, and a scan driver configured to: in response to an image mode being a moving image mode, generate a first mode scan signal having a turning-on voltage of a transistor for a plurality of horizontal periods; and in response to the image mode being a static image mode, generate a second mode scan signal having the turning-on voltage for a single horizontal period.

Abstract: This disclosure provides a shift register unit that includes an input circuit, a reset circuit, an output circuit, a first pull-down control circuit, a second pull-down control circuit, a first pull-down circuit and a second pull-down circuit. This disclosure also provides a control method for the shift register unit, a gate drive circuit, a display substrate and a display device.

Abstract: A display device includes a pixel column including first to n-th pixels connected to a same data line and different gate lines from each other, a data driving chip which outputs a test data voltage in a test mode and outputs image data voltages in a normal mode, a sensing circuit which is electrically connected to the data line and the data driving chip in the test mode, senses a current output to the first pixel during a first period, and senses a current output to an i-th pixel during a second period, and a signal controller which compares a reference charge amount calculated based on the current sensed during the first period to a first charge amount calculated based on the current sensed during the second period and compensates for a level of an image data voltage applied to the i-th pixel among the image data voltages based on the compared result.

Abstract: The present disclosure proposes a method and a system of controlling backlight driving. The method includes receiving an initial-pulse-width modulating signal and outputting a corresponding pulse-width modulating signal according to the initial-pulse-width modulating signal. The pulse-width modulating signal is used to control a corresponding LED string to illuminate. A cycle of each of the pulse-width modulating signals is the same with a predetermined phase difference.

Abstract: A display device includes a gate driver for applying scan signals and including a plurality of gate driving circuit blocks, and a data driver for applying a data voltage to data lines, wherein the gate driving circuit blocks respectively output a carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit block based on a signal applied to a first control node through a first input terminal and a carry clock signal input to a carry clock input terminal, output a scan signal to a first scan line based on the signal applied to the first control node and a scan clock signal input to a first scan clock input terminal, and output a scan signal to a second scan line based on the signal applied to the first control node and a scan clock signal input to a second scan clock input terminal.

Abstract: A driving module for a display device includes a first transistor, comprising a gate coupled to a first node, a drain coupled to an output end, and a source coupled to a first positive voltage source; a second transistor, comprising a gate coupled to a second node, a drain coupled to output end, and a source coupled to a first negative voltage source; and a voltage generating unit, coupled to an input end, a second positive voltage source and a second negative voltage source for generating a first voltage at first node and a second voltage at second node according to a control signal from input end; wherein voltage difference between a first positive voltage of first positive voltage source and first voltage is smaller than first threshold and voltage difference between a first negative voltage of first negative voltage source and second voltage is smaller than second threshold.

Abstract: An array substrate and a display panel are disclosed. The array substrate includes: a GOA unit; a plurality of gate lines, electrically connected to the GOA unit; and a static-conducting device, electrically connected between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other. In the array substrate, the static-conducting device is arranged between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other to together resist the ESD. In this way, the anti-electrostatic discharge ability of the array substrate is improved, and the product quality is also improved.

Abstract: This application provides a shutdown signal generation circuit and a display apparatus. The shutdown signal generation circuit includes: a first switch, where a first end of the first switch is electrically coupled to a first frequency, a control end of the first switch is electrically coupled to a first node, and a second end of the first switch is electrically coupled to a second node; and a second switch, wherein a first end of the second switch is electrically coupled to a second frequency, a control end of the second switch is electrically coupled to the first node, and a second end of the second switch is electrically coupled to the second node, where the first node is electrically coupled to a control signal, and the second node electrically outputs a gate shutdown signal.

Abstract: A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.

Abstract: A display device includes a display panel, display drivers, an inspection signal output, judgement signal outputs included in the respective display drivers and through which judgement signals generated by the display drivers are output, signal inputs included in at least the display drivers except a most upstream one of the display drivers and through which the judgement signals and the inspection signals are input, switches located between the adjacent display drivers in an upstream and downstream direction to cascade the display drivers and each configured to switch points connected to the signal input of one of the display drivers on a downstream side between the judgement signal output of one of the display drivers on an upstream side and the inspection signal output, and a judgement unit connected at least to the judgment signal output of a most downstream one of the display drivers to receive the judgement signal.

Abstract: An illuminance sensor detects a flicker with higher accuracy than in the related art. The illuminance sensor includes: a light receiving unit that receives light and outputs a current; a flicker measurement counter circuit that performs AD conversion on the current and outputs a first digital signal to a flicker measurement storage device; an illuminance measurement counter circuit that performs AD conversion on the current and outputs a second digital signal to an illuminance measurement storage device; and a flicker detection unit that detects a flicker by analyzing the first digital signal stored in the flicker measurement storage device. A cycle during which the first digital signal is output from the flicker measurement counter circuit is shorter than a cycle during which the second digital signal is output from the illuminance measurement counter circuit.

Abstract: An image processing apparatus including an image data processor unit is provided. The image data processor unit is configured to generate a plurality of partial output frames according to a plurality of input frames. With respect to one pixel in a display panel, each partial output frame among the partial output frames includes sub-pixel data corresponding to a part of sub-pixels in the pixel instead of sub-pixel data corresponding to all of the sub-pixels in the pixel. In addition, a display panel and a display apparatus are also provided.

Abstract: A gate driver on array (GOA) circuit unit, including: a scan portion and an emission portion. The scan portion includes: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, a turn-on signal end, a first clock signal end, a second clock signal end, a power supply end, and a first node. The emission includes: a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, a second capacitor, a third capacitor, a fourth capacitor, a third clock signal end, a first controlling clock signal end, a second node, a third node, a fourth node, and a fifth node.

Abstract: Provided is an interface circuit that includes a circuitry that extracts a first signal, including a clock component, from a differential signal received from an external device through a transmission path. The circuitry extracts a second signal, including a clock component, from an in-phase signal received from the external device. The circuitry communicates with the external device through a pair of differential transmission paths included in the transmission path. The circuitry is notified by the external device of a connection state of the external device by a DC bias potential of at least one of the pair of differential transmission paths.

Abstract: The present application provides a driver for driving a display panel. The driver includes a timing controller, and N cascaded source drivers, N being an integer equal to or larger than 2. The N source drivers are configured to receive sensing signals obtained by detecting characteristics of pixel units in the display panel, respectively. An n-th source driver of the N source drivers is configured to transmit the sensing signal received by the n-th source driver to the timing controller through all source drivers of the N source drivers after the n-th source driver as a signal transmission channel, where 1?n<N and n is an integer. The present application further provides a display apparatus and a method for generating a source driving signal.

Abstract: A refresh rate adjustment method and circuit, a display device, and a storage medium, which pertains to the field of display technologies. The method includes acquiring a current driving refresh rate of a driving apparatus; determining whether the driving refresh rate is less than a driving refresh rate threshold; in response to the driving refresh rate being less than the driving refresh rate threshold, adjusting a display refresh rate of a display device, so that an adjusted display refresh rate is P times the driving refresh rate, and the adjusted display refresh rate is greater than the driving refresh rate threshold, where P is an integer greater than one.

Abstract: Systems, apparatuses, and methods are described herein for phase locked multi-display synchronization. In a slave display device, a first tearing effect signal is received that indicates rendering of a first image frame portion of a first image frame by a master display device has at least been initiated. In response to receiving the first tearing effect signal, a second image frame portion of a first image frame is retrieved from a frame buffer and is rendered to a display screen of a slave display device. In response to rendering the retrieved second image frame portion, a second tearing effect signal is generated for receipt by a host device to trigger the host device to transmit a second image frame portion of a second image frame to the slave display device.

Abstract: An organic light emitting diode display panel includes data lines arranged in a first direction; gate lines arranged in a second direction to cross the data lines; a driving voltage line arranged in the first direction; a reference voltage line arranged in the first direction; data pads respectively at ends of corresponding ones of the data lines; a driving voltage pad at an end of the driving voltage line; and a reference voltage pad at an end of the reference voltage line. A first distance is defined between the driving voltage pad and an adjacent data pad, a second distance is defined between adjacent ones of the data pads, and a third distance is defined between the reference voltage pad and an adjacent data pad. At least two of the first distance, the second distance, and the third distance are different from each other.

Abstract: A driving circuit and an anti-interference method thereof are provided. The driving circuit includes a source driver. The source driver is configured to be controlled by a timing controller. The source driver is configured to adjust at least one of an operation frequency and a receiving bandwidth of a source driving circuit of the source driver when at least one of the timing controller and the source driver detects that an interference event occurs.

Abstract: The present disclosure relates to a display device for driving virtual reality with low latency and compensating the reduced brightness. According to the present disclosure, a display device is provided, and the display device includes a timing controller for receiving a data signal and a timing signal from a host system, a data driving unit for receiving a drive signal from the timing controller, a gate driving unit for receiving a drive signal from the timing controller, a display panel having a plurality of sub-pixels and for displaying a video based on the signals received from the data driving unit and the gate driving unit, and a power supply unit for supplying power to the data driving unit, the gate driving unit, and the display panel; and the timing controller receives an address reset signal from the host system.

Abstract: The present disclosure provides a pixel circuit, a display panel, and a display device. The pixel circuit includes: first and second scan signal input terminals; a data signal input terminal; a first power supply signal input terminal; a light-emitting control signal input terminal; a reference voltage input terminal; first to sixth transistors, a first capacitor, and a piezoresistor having a first electrode electrically connected to a first electrode plate of the first capacitor, and a second electrode electrically connected to a first electrode of the third transistor.

Abstract: A display apparatus including a display panel, an image data processor unit and a display driver is provided. The image data processor unit is configured to generate a plurality of partial output frames according to a plurality of input frames. With respect to one pixel in the display panel, each partial output frame among the partial output frames includes a part, instead of all, of sub-pixel data to be displayed by the pixel. The display driver is coupled to the image data processor unit and a data signal input terminal of the display panel. In addition, a display panel is also provided.

Abstract: In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, the mask signal may be generated by compensating for a processing delay time occurring in a mask signal generation circuit, thereby reducing the inaccuracy of the mask signal due to the processing delay time.

Abstract: At a previous stage prior to displaying an input image in a display region, a display device outputs, to a transmitting section, a first instruction to transmit a first data signal having a specific pattern with a phase difference from a clock signal set to a first phase difference; reads, from a receiving section, a first received data signal corresponding to a data signal received by the receiving section from the transmitting section having received the first instruction; performs, as receipt result determination, first determination based on the first data signal and the first received data signal as receipt result determination; and determines, based on a result of the first determination, a set phase difference corresponding to the phase difference from the clock signal employed in transmitting the data signal based on the input data.

Abstract: A hardware boost method and a hardware boost system are provided. The hardware boost method includes: initializing a status table, wherein the status table includes multiple statuses, each of the statuses corresponds to a first action and a second action, and each of the statuses includes FPS information; and in each episode: determining that a system status belongs to a first status among the statuses; executing one of the first action and the second action according to a value corresponding to the first status and the first action and a value corresponding to the first status and the second action to enter a second status among the statuses and obtain a reward value; and refreshing the value corresponding to the first status and the one of the first action and the second action according to the reward value.

Abstract: A gate driver on array (GOA) circuit includes cascaded GOA unit circuits. An nth stage GOA unit circuit includes a clock signal source, a constant voltage supply, a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a pull-down maintaining circuit, a bootstrap capacitor and a conducting control circuit. An output terminal of the pull-up control circuit is electrically connected to the pull-up circuit, the downlink circuit, the pull-down circuit, the pull-down maintaining circuit, and the bootstrap capacitor. The constant voltage supply is electrically connected to the pull-down maintaining circuit and the pull-down circuit. The clock signal source is electrically connected to the pull-up circuit, the downlink circuit, and the conducting control circuit. The conducting control circuit is electrically connected to the pull-down maintaining circuit.

Abstract: An integrated circuit for driving a display panel and an anti-interference method are provided. The integrated circuit includes a source driving circuit and an anti-interference circuit. The source driving circuit includes a receiving circuit configured to receive an input signal including image data and process the input signal based on at least one operation parameter to generate output data. The anti-interference circuit is coupled to the receiving circuit. The anti-interference circuit determines whether an interference event occurs to the input signal based on the input signal or the output data to obtain a determination result and determines whether to adjust the at least one operation parameter of the receiving circuit according to the determination result.

Abstract: Disclosed are an image display device and an image processing method thereof. A signal processing method of the image display device according to the present invention is a signal processing method of an image display device configured to receive an image having a varied vertical synchronization signal, including detecting an input synchronization signal using an input image clock, extracting an input vertical synchronization signal from the input synchronization signal, delaying the input vertical synchronization signal by a reference value of an output clock, continuously tracking a falling region of the delayed input vertical synchronization signal, and finally generating an output synchronization signal in which a vertical front porch is varied.

Abstract: A pixel includes an organic light emitting diode (OLED), a first transistor connected to a driver and a first node, having a gate connected to a control line, a second transistor between to the first node and a second node, having a gate connected to a third node, a third transistor connected to an anode of the OLED, having a gate connected to the control line, a fourth transistor between the first node and a data line, having a gate connected to a scan line, a fifth transistor between the second and third nodes, having a gate connected to the scan line, a sixth transistor between an initializing line and the anode, having a gate connected to the scan line, a seventh transistor between the initializing line and the third node, having a gate connected to another scan line, and a storage capacitor between the driver and the third node.

Abstract: A gate driver includes a plurality of stages. A present stage among the plurality of stages is configured to receive a clock signal, a scan signal of a previous stage among the plurality of stages that is before the present stage, a first initialization voltage and a second initialization voltage different from the first initialization voltage and to generate a scan signal of the present stage and a initialization signal of the present stage based on the clock signal, the scan signal of the previous stage, the first initialization voltage and the second initialization voltage. The initialization signal of the present stage is varied between the first initialization voltage and the second initialization voltage according to time.

Abstract: A display driving device is disclosed which includes a source driver that supplies voltages to source lines connected to pixels, detects a slew time of the voltages of the source lines, and outputs the slew time, and a timing controller that receives the slew time from the source driver and updates a way for the source driver to control the voltages depending on the slew time.

Abstract: A LCD device of display panels includes n-bit (n<m) driving first display panel that displays first image based on m-bit input image data, n-bit driving second display panel that displays second image based on the m-bit input image data, and image processor including first gradation converter that converts gradation of the m-bit input image data into n-bit gradation, second gradation converter that converts gradation of the m-bit input image data into m1-bit (m1?m) gradation, and extension processor that performs extension processing of extending gradation expression with the n bits on the input image data converted into the m1-bit gradation. The n-bit driving first display panel displays the first image based on the n-bit input image data, and the n-bit driving second display panel displays the second image based on the n-bit input image data subjected to the extension processing.

Abstract: A shift register unit, a driving method, a gate driving circuit, and a display device are provided. The shift register unit includes an input reset circuit; a first storage node potential maintaining circuit; a second storage node potential control circuit; a pull-up node control circuit for controlling the potential of the pull-up node to be a valid level under the control of the second storage node, the second clock signal input end, and the fourth clock signal input end, and controlling to connect or disconnect the pull-up node and the second voltage input end under the control of the second clock signal input end and the third clock signal input end; a pull-up node potential maintaining circuit; a pull-down node control circuit; and a gate driving output circuit.

Abstract: Disclosed are a communication method, which is capable of being applied to a display device where a timing controller is provided in a system board instead of a display module, and a display device using the same. The communication method includes converting the digital video data and control signals into a transmission packet and transmitting the transmission packet from a first transmission module of a system board to a first receiving module of an interface board through a cable, restoring the digital video data and the control signals from the transmission packet, and transmitting the restored digital video data and control signals from the first receiving module to a display panel driver applying a plurality of driving signals to a display panel.

Abstract: Embodiments of a display device for displaying a marked image on a display device are disclosed. The display device includes a control circuit configured to receive image data and supplementary data, and a display panel. The display panel includes a plurality of main pixels, each of the plurality of main pixels including a main pixel electrode and configured to display the image data, and a plurality of supplementary pixels, each of the plurality of supplementary pixels including a supplementary pixel electrode and configured to display the supplementary data. The plurality of main pixel electrodes are arranged in a series of columns and rows to form a matrix with the plurality of supplementary pixel electrodes being interspersed within the matrix. The plurality of main pixels are larger in size than the plurality of supplementary pixels.

Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.

Abstract: Systems, devices and methods are provided for video encoding. For example, video data is encoded based at least in part on a preset encoding algorithm to obtain a video encoding stream that comprises a plurality of coding frames. A stream tag is added for the video encoding stream, and a frame tag is added for each coding frame in the video encoding stream. The stream tag includes information characterizing whether the stream tag is added into the video encoding stream. The frame tag includes type information of the coding frame.

Abstract: A display apparatus includes a display panel to display an image, a first frame counter to count a first number of frames during a first duration and to be reset when the first number reaches a first reference number, a second frame counter to count a second number of the frames during a second duration and to be reset when the second number reaches a second reference number, wherein the second duration occurs after and is shorter than the first duration, a level counter to hold a count value at a first count value during the first duration, to change the count value when the first frame counter is reset, and to change the count value when the second frame counter is reset, and a common voltage generator to control a level of a common voltage to correspond to the count value and to output the common voltage.

Abstract: A method of driving a display panel and a display apparatus having a plurality of gate lines and a plurality of data lines that cross the gate lines. The method includes determining whether to compensate a gate signal or not according to input image data displayed on a display panel, transmitting a first gate signal having a first falling waveform to a first gate line and a second gate signal having a second falling waveform different from the first falling waveform to the second gate line. A first gate clock signal may be adjusted when the gate signal is determined to be compensated. A timing controller may compensate the first gate signal when an artifact would be displayed based on a variation in brightness when a first subpixel row to which the first gate signal is applied is brighter than a second subpixel row for a same target luminance.

Abstract: The present disclosure provides a shift register unit, a gate scanning circuit, a driving method, and a display apparatus.

Abstract: A projector includes an input unit configured to receive an image signal, a display configured to display an image based on the image signal received by the input unit, an image displacement unit configured to change a position of the image to be displayed by the display, and a control unit configured to control a driving signal to drive the image displacement unit. An output timing of the driving signal is changed based on a frequency of the image signal.