Abstract: A system is presented for interconnecting a single user console having user interface devices, including a console keyboard, a console video display unit, a console mouse, and speakers, to a plurality of host computers each capable of using user interface devices, including a keyboard, a video display unit, and a mouse, and allowing the user to access one or more of the host computers from the single user console. The video output from each of the host computers is scaled and cropped as appropriate so that the video output of each host may be simultaneously displayed as host computer “windows” on the console video display unit or overlaid with the background suppressed to display application windows from multiple hosts on a single screen.

Abstract: The present invention provides a gate driving circuit applied for 2D-3D signal setting, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part, a pull-down holding part and a pull-up compensation part; on the basis of the gate driving circuit utilizing the present GOA skill, the present invention adds a pull-up compensation part to compensate the leakage gap existing in the 2D signal transmission to ensure that the voltage level of the gate signal point Q(N) will not descend in leakage gap period; by introducing an additional DC control signal source DC to control the activation and deactivation of the pull-up compensation part for activating it in 2D mode to realize co

Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.

Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Abstract: A gate driver on array (GOA) circuit for an LCD includes multiple cascaded GOA units. A Nth stage GOA unit controls a charging of a Nth stage horizontal scanning line. The Nth stage GOA unit includes a pull-up circuit, a pull-down circuit, a first pull-down holding circuit, a second pull-down holding circuit, a bridge circuit, a pull-up control circuit, a transfer circuit, and a boast capacitor. A seventh TFT connects in parallel with a third TFT of the first pull-down holding circuit. A fourteenth TFT connects in parallel with a tenth TFT of the second pull-down holding circuit. The gate of the seventh TFT and the gate of the fourteenth TFT are connected, and both connected to a starting signal from (N?1)th GOA unit or a (N?1)th stage horizontal scanning line. An LCD device also uses the GOA circuit to reduce the delay of the gate signal output.

Abstract: A liquid crystal display (LCD) monitor including an LCD display panel for displaying a frame, a timing controller for generating a polarity control signal and a latch signal, and a driving circuit including a plurality of source drivers, each of the plurality of source drivers including a comparison unit for comparing a common electrode voltage with a first and a second reference voltages to generate a comparison result, an enabling unit for generating an enabling signal according to the comparison result, a source driving signal and a reset signal, a horizontal dot inversion control unit for generating a horizontal dot inversion control signal according to the enabling signal, and a polarity control unit for generating a polarity inversion control signal and the reset signal according to the enabling signal, the polarity control signal and the latch signal.

Abstract: According to various embodiments of the invention, gamma curves for multiple pixel groups can be calibrated using look-up tables or by using reference voltage groups provided by gamma voltage generators so that the pixels can display multiple images with correct gray levels at different view angles. Therefore, color shift can be avoided or lessened without necessarily using extra circuitry on the display panel. Also, any related light transmittance or light utilization efficiency reduction may be decreased or eliminated.

Abstract: A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.

Abstract: A voltage generating circuit includes a voltage dividing part connected between a main voltage source and a ground configured to divide a main voltage into a plurality of driving voltages and output the plurality of driving voltages, a delay part connected between a driving voltage source and the ground, and configured to delay a driving voltage by a predetermined period and apply the driving voltage to an input terminal of a driver circuit, and a discharge part connected between the voltage dividing part and the delay part, and configured to discharge a voltage charged in the delay part to a ground when the driving voltage is blocked. The discharge part comprises an amplifier, an inverting input of the amplifier being connected to the driving voltage source and a non-inverting input of the amplifier being connected to an output terminal of the delay part.

Abstract: A flat panel display device, which can reduce manufacturing costs is disclosed. The flat panel display device includes a display panel for displaying images and a plurality of driving integrated circuits for driving the display panel. Each of the plurality of driving integrated circuits includes a timing controller for arranging input image data such that the image data is suitable for driving of the display panel and generating a plurality of data control signals and a data driver for converting the image data provided from the timing controller into data voltages in response to the plurality of data control signals. Intervals during which the timing controllers of the driving integrated circuits supply clock signals to the data drivers of the corresponding driving integrated circuits are different.

Abstract: There is provided a drive control apparatus that includes a horizontal control section, and a vertical control section. The horizontal control section controls a scanning mirror for horizontal scanning with laser light, the scanning mirror being driven at a fixed frequency in a horizontal direction. The vertical control section controls the scanning mirror for vertical scanning based on the frequency at which the horizontal control section drives the scanning mirror in the horizontal direction, the vertical control section outputting a vertical drive signal to control the scanning mirror for vertical scanning, the vertical drive signal including an interval in which the laser light is directed vertically from top to bottom and an interval in which the laser light is directed vertically from bottom to top, the intervals alternately producing an output of a predetermined amount.

Abstract: A method and a device for synchronizing an image display, a first image signal being provided by a first device and a second image being provided by a second device being brought together for display, the first device and the second device being time-controlled independently of each other. The second image signal is synchronized with the first image signal by modifying a blanking interval of the second image signal.

Abstract: An organic light-emitting diode display panel is disclosed herein. The organic light-emitting diode display panel includes display units. Each of display units includes an organic light-emitting element, a light-driving circuit and stages of shift register connected in series. The light-driving circuit drives the organic light-emitting element according to a light-emitting control signal. Each of the stages of the shift register includes a shift register circuit and a control signal output circuit. The shift register circuit generates a current stage shift signal according to a previous stage shift signal and a first clock signal. The control signal output circuit outputs the light-emitting control signal according to the current stage shift signal and a previous stage carry signal. The enabling period of the light-emitting control signal is determined by the time period between the enabling period of the current stage shift signal and the previous stage carry signal.

Abstract: The present invention discloses a display device comprising the structure. The pixel structure comprises multiple pixel units arranged in a matrix form, and multiple gate lines and data lines for providing drive to the multiple pixel units, wherein the multiple pixel units are scanned progressively in unit of L rows; the L rows of pixel units being simultaneously scanned among the plurality of pixel units are configured as a pixel block; and at least two adjacent rows of pixel units in the L rows of pixel units being used for displaying different images, wherein L?3. By adopting the pixel structure, the problems of undercharge of a storing capacitor Cs and RC delay of the data lines are alleviated, thus the display uniformity and the display quality of the display device is ensured. The pixel structure is particularly suitable to a large-size ultra-high-resolution display device.

Abstract: Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed.

Abstract: A display panel and a scanning circuit are disclosed herein. The scanning circuit includes a plurality of shift registers. Each of the shift registers includes a driving unit, a control unit, and an operating unit. The driving unit is configured to receive a start signal and a driving clock signal, and provide a scan signal to an output end according to the start signal and the driving clock signal. The control unit is configured to provide a second voltage to the output end according to a first voltage on a control node, and to provide the second voltage to a driving end according to the first voltage on the control node. The operating unit is configured to operatively provide the first voltage to the control node according to an operating clock signal after the scan signal is outputted.

Abstract: A conversion circuit includes: a conversion section configured to convert each of analog pixel signals into digital pixel data; a timing acquisition section configured to acquire specified timing, in which the specified timing defines a display period during which display of each of the analog pixel signals is performed in a cycle of a synchronization signal; a timing setting section configured to set timing that defines an extension period that is longer than the display period, in which the timing is other than the specified timing; an enable signal generation section configured to generate an enable signal, in which the enable signal indicates the extension period as a period during which the digital pixel data is valid; and an output section configured to output the digital pixel data that is valid, in accordance with the enable signal.

Abstract: A liquid crystal display device is disclosed. The display device includes gate drive ASG circuits, and a driver integrated circuit configured to connect wires from gate line output terminals of the ASG circuits with a client system. The ASG circuits output level signals to the client system, and the client system is configured to determine a duration time during which the level signals from the ASG circuits exceed a preset level signal threshold value, and in response to the duration time being less than the preset time threshold value, the driver integrated circuit receives an adjusted signal code required for operation of the ASG circuits, and the driver integrated circuit drives the ASG circuits according to the adjusted signal code required for operation of the ASG circuits.

Abstract: A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, includes adjusting a selecting signal according to a clock signal; selecting one of a plurality of scrambling generating units according to the selecting signal to generate a timing scrambling signal; and generating scrambling data for the plurality of source driving devices according to the timing scrambling signal.

Abstract: A display panel driving device is provided. The display panel driving device includes a host and a driving chip. The driving chip includes a store unit, a driving module and a transmitting interface unit. The host controls the transmitting interface unit to switch sources of image data received by the driving module according to content of the image data, so as to determine whether the driving module receives the image data from the store unit or not.

Abstract: An image display apparatus has an A/D converter for sampling an analog video signal whose signal level changes at a frequency higher than the frequency of a synchronizing signal, based on a reproduced dot clock, and converting the sampled analog video signal into a digital video signal, a clock adjusting circuit for generating a clock in synchronism with the synchronizing signal, delaying the phase of the clock according to set delays, and outputting the delayed clock as the reproduced dot clock, a controller for dividing an area of an image displayed based on the converted digital video signal, into a plurality of image areas defined by display lines in a horizontal direction, and establishing different delays for the divided image areas, and a delay evaluating circuit for converting differential data between adjacent signal levels on the display lines for the respective image areas, into absolute values and accumulatively adding the absolute values, thereby producing accumulated sums.

Abstract: The claimed invention is related to a self-healing gate driving circuit. The self-healing gate driving circuit includes a plurality of GOA units connected in cascade. The N-th level GOA unit includes a pull-up control circuit 100, a pull-up circuit 200, a transfer-down circuit 300, a pull-down circuit 400, a boast capacitor 500, a first pull-down holding circuit 600, a second pull-down holding circuit 700 and a bridge circuit 500. The bridge circuit 800 includes the first TFT T55, and the gate of the TFT T55 connects to the gate signal point Q(N), and the drain and the source of the TFT T55 respectively connects to the first circuit point K(N) and the second circuit point P(N). During the operation, the first circuit point K(N) and the second circuit point P(N) are alternatively configured to be at a high potential.

Abstract: A display device includes a clock oscillator, a register, and a data driver. The clock oscillator generates a clock signal. The register stores a clock signal parameter for the clock signal. The data driver determines a number of clock signals in 1 horizontal period based on the clock signal parameter, and applies data signals to data lines connected to a plurality of pixels based on the 1 horizontal period.

Abstract: A control system with a serial interface is provided. The control system includes a programmable database, a first driver, at least one second driver, and a controller. A data is written into the programmable database through a programming method. The first driver is coupled to the programmable database via the serial interface. The at least one second driver is coupled with the first driver. The controller is coupled with the serial interface and accordingly coupled to the programmable database and the first driver via the serial interface. The controller captures the data from the programmable database through the serial interface and adjusts parameters of the first driver and the at least one second driver according to the data.

Abstract: A display panel is provided, including an image data storage capacitor, a capacitive element, and four switches. The image data storage capacitor stores an image data. The sample unit has a control terminal for receiving a sample control signal. The capacitive element has a first terminal coupled to a pixel electrode of the image data storage capacitor via the sample unit. The first refresh unit has a control terminal coupled to the first terminal. The second refresh unit has a control terminal for receiving a refresh control signal. The third and first refresh units are serially coupled with each other between a corresponding source line and the image data storage capacitor for receiving a data signal. The shunt unit has a control terminal coupled to the pixel electrode, a data terminal coupled to the first terminal, and another data terminal for receiving a shunt control signal.

Abstract: Systems, methods, and assemblies to provide clock signals to electrical components of downhole tools are provided. In one example, an oscillator assembly may include a silicon-based oscillator having a variable capacitor circuit. The silicon-based oscillator may provide an output signal at a frequency within a range of frequencies. The oscillator assembly may also include control circuitry electrically coupled to the silicon-based oscillator. Moreover, the control circuitry may include a temperature input that receives a temperature corresponding to the silicon-based oscillator. The control circuitry may also include a control signal output electrically coupled to the silicon-based oscillator. The control signal output may be used to change a capacitance of the variable capacitor circuit based on the temperature received by the temperature input to maintain the output signal of the silicon-based oscillator within the range of frequencies.

Abstract: A display apparatus includes: a pixel array section including a row of scanning lines, a column of signal lines, and pixels in a matrix, each of the pixels disposed at an intersection of both of the lines; and a drive section. The drive section performs line progressive scanning on the pixels. The pixel includes a light emitting device, a sampling transistor, a driving transistor, a switching transistor, and a holding capacitor. The sampling transistor samples a video signal in the holding capacitor, the driving transistor changes the device to a luminous state, the switching transistor becomes ON in advance of the sampling of the video signal to change the light emitting device to a non-luminous state, and the sampling transistor takes in the OFF voltage from the signal line to the driving transistor, thereby preventing a penetration current from flowing from the power source toward the fixed potential.

Abstract: Liquid Crystal Display (LCD), 3D imaging apparatus and operating methods thereof are disclosed. The operating method for the disclosed LCD includes the steps of: driving a pixel array of the LCD to display a frame of data by a first frame scan and a second frame scan; and, controlling a backlight module of the LCD in accordance with the first frame scan and the second frame scan. In the first frame scan, the scan lines of pixel array are driven in groups, wherein, in each group, all rows corresponding thereto are driven by identical data. The rows which have not been driven by correct data in the first frame scan are driven again and corrected in the second frame scan.

Abstract: Image signal line driving circuits each include a timing controller that generates a control signal to control the image signal line driving circuit itself and a different image signal line driving circuit. A master belonging to the image signal line driving circuits has a function of applying the control signal to a slave belonging to the image signal line driving circuits. The image signal line driving circuits each include an abnormality detecting circuit that detects an operation abnormality in the image signal line driving circuit itself, and a master/slave switching circuit that sets the image signal line driving circuit itself as the master or slave image signal line driving circuit. When detecting an abnormality, the abnormality detecting circuit outputs a master/slave switching signal, thereby switching the slave image signal line driving circuit to the master and switching the master image signal line driving circuit to the slave.

Abstract: Each of image-signal-line drive circuits includes a timing controller that generates a control signal controlling itself and other image-signal-line drive circuit, and a master/slave selection circuit that sets itself as a master mode image-signal-line drive circuit or a slave mode image-signal-line drive circuit based on a selection signal to be given from outside. From among the plurality of image-signal-line drive circuits, the master mode image-signal-line drive circuit gives the control signal to the slave mode image-signal-line drive circuit.

Abstract: The present invention provides a liquid crystal display (LCD) panel and a display apparatus using the same. The LCD panel comprises a first substrate, a second substrate and a liquid crystal layer. The second substrate comprises pixels, wherein, when images are displayed by the pixels, a voltage difference between a first voltage of the first sub-pixels and a second voltage of the second sub-pixels is inversely proportional to a grayscale of the images displayed by the pixels, and the first voltage is higher than the second voltage. The present invention can mitigate the viewing angle problem of the pixels.

Abstract: A transmission method for a display device is provided. The display device includes a one-to-many timing controller and a plurality of source drivers. The transmission method includes determining whether the plurality of source drivers being operated in different operational modes are switched on or off according to a command signal, to receive a display information of the one-to-many timing controller. The display information comprises at least a first control triggering signal, a first control signal, a first display information triggering signal, a first display signal, a second display information triggering signal and a second display signal, and the command signal is an internal setting signal or an external setting signal.

Abstract: Methods and devices are provided for controlling the brightness of a display for an electronic device based on ambient light conditions. In one embodiment, an electronic device may employ one or more brightness adjustment profiles that define response rates for changing brightness levels based on ambient light levels. The response rates may vary depending on the magnitude and/or direction of change in the ambient light levels. In certain embodiments, the response rates may be designed to approximate the physical response of the human vision system. Further, in certain embodiments, noise reduction techniques may be employed by adjusting the response rates based on the magnitude of the change in the ambient light level and/or based on whether the display is operating at steady state or executing a brightness adjustment.

Abstract: A method and evaluation device for checking plausibility of an incremental counter, wherein counting pulses are detectable via the incremental counter, and wherein a dynamic system generates the counting pulses with a clock rate corresponding to a state of the dynamic system. Here, a minimum value and a maximum value for a possible or permitted change in the clock rate per time unit is predefined based on operating limits of the dynamic system, wherein a current clock rate is calculated in each case from two counting pulses respectively detected last, and wherein at each newly detected counting pulse the counting pulse is checked to determine if the difference between the clock rate calculated in the course of the newly detected counting pulse and a clock rate calculated immediately beforehand is within the limits defined by the minimum value and maximum value, wherein otherwise implausibility is detected.

Abstract: A stereoscopic image display device includes a scan driver, a data driver, a light emission control driver, a display unit including a plurality of pixels, and a controller controlling the scan driver, the data driver, and the light emission control driver. The controller generates image data signals corresponding to a left-eye image display period, a right-eye image display period, and a black image display period during one frame and supplies the image data signals to the data driver. The black image display period, in which a black image according to the black data signal is displayed, and a shutter stabilization period, in which a left eye glass and a right eye glass of shutter spectacles are opened/closed, overlap each other between the left-eye image display period and the right-eye image display period.

Abstract: Disclosed is a liquid crystal display device and a method of driving the same, which prevent image-quality defects due to charge variation. In the method of driving the liquid crystal display device including a pixel consisting of first to third sub-pixels which share one data line and are connected to first to third gate lines, one sub-pixel is turned off on a per frame basis, another sub-pixel is charged with a polarity inverted data voltage for a first charge time including a charge time of the turned-off sub-pixel, and the other sub-pixel is charged with a data voltage having the same polarity as a previous data voltage for a second charge time less than the first charge time. The turned-off sub-pixel, the sub-pixel charged with the polarity inverted data voltage, and the sub-pixel charged with the polarity maintained data voltage alternately vary on a per frame basis.

Abstract: According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Abstract: In one embodiment, a display panel includes a plurality of display elements, and image control circuitry coupled to the display elements. A power supply circuitry is coupled to the display elements. A housing encloses the display elements and the image control circuitry. The housing is sealed with respect to external elements. A first integrated data and power cable extends from outside the housing, through a housing wall and electrically connected to the image control circuitry and the power circuitry. A second integrated data and power cable extends from outside the housing, through the housing wall and electrically connected to the image control circuitry and the power circuitry.

Abstract: Provided is an apparatus and method for electrical stability compensation. The apparatus includes a drive transistor connecting a power supply to a load, a first variable capacitor having a gate and a source, and a switch transistor for controlling a connection between a programming signal source and a gate of the drive transistor. The gate of the first variable capacitor is connected to the gate of the drive transistor. The first variable capacitor is configured to draw a charge from the gate of the drive transistor during a driving phase for the load.

Abstract: Disclosed is a technique, in which when driving chips are used in which control units are respectively merged in driving devices, all modes of the other driving chips are simultaneously converted into a fail safe mode when one driving chip detects a non-signal state. A circuit for controlling a non-signal of a flat panel display device includes a plurality of driving chips. When detecting a non-signal state that the normal signal (LVDS) is not inputted from an outside, each of the plurality of driving chips simultaneously changes potentials of non-signal detection pads of its own driving chip and another driving chip so that all the driving chips are operated in the fail safe mode.

Abstract: A method for creating a distance dependent display that comprises providing an image separating mask having a plurality precision slits arranged in a pattern, generating an interlaced image from a plurality of images according to the pattern, and combining the interlaced image and the image separating mask to allow an observer to view substantially separately each the image from a respective of a plurality of different distances from the image separating mask.

Abstract: A display device includes: a display panel comprising a plurality of pixels coupled to a plurality of gate lines and a plurality of data lines, respectively; a gate driver configured to drive the plurality of gate lines; a data driver configured to drive the plurality of data lines; and a timing controller configured to control the gate driver and the data driver and to provide the data driver with a data signal generated by compressing an image signal received from an external device, wherein the timing controller is configured to compress the image signal according to a first compression scheme and a second compression scheme to generate a first compression signal and a second compression signal, respectively, and wherein the timing controller is configured to select whichever one, from among the first compression signal and the second compression signal, that has a relatively narrower bit width as the data signal.

Abstract: Disclosed is an organic light-emitting display device and operating method thereof that may include an organic light-emitting diode, a first transistor controlled by a sensing signal and connected to a data line, a second transistor controlled by a scanning signal and connected to the data line, and a driving transistor having first to third nodes, wherein a reference voltage is applied to the first node through the first transistor, a data voltage is applied to the second node through the second transistor, and the third node is connected to a driving voltage line.

Abstract: Low power consumption is realized focusing on the refresh interval of a low leakage display panel. Display systems and microcomputers are described herein. One embodiment of a display system includes a display driver. The driver receives an enable signal from the outside, stops the display operation of an internal circuit in an inactive state of the enable signal, and resumes the display operation of the internal circuit in an active state. Instead of the enable signal, a command supplied from the outside may be used. When resuming the display operation, the display driver performs control to make the start timing of the display operation earlier for a circuit that requires a long time for activation. A microcomputer that outputs an enable signal or a command controls the output or the output stop of display data according to the state of the enable signal or the command.

Abstract: A three-dimensional image display apparatus includes a display panel configured to display an image and including gate lines, data lines, and pixels connected to the gate lines and the data lines, a data driver configured to drive the data lines, a gate driver configured to drive the gate lines, a lens panel configured to refract light of the image displayed by the display panel, a lens driver configured to drive the lens panel, a lens controller configured to control the lens driver, and a timing controller configured to control the data driver, the gate driver, and the lens driver in response to an image signal and a control signal. The lens controller and the timing controller are mounted on the same control board.

Abstract: A method of driving a display device includes a writing operation and a reading operation. The writing operation includes writing first to Mth frame data in a first frame memory during first to Mth frame periods. The reading operation includes reading (L?M)th and (L?M+1)th frame data among the first to Mth frame data from the first frame memory during an Lth frame period. M may be three or more, and L may be an integer ranging from (M+1) to (2M?1). The frame data read from the first frame memory corresponds to an image to be displayed. Reading and writing operations are further performed for remaining ones of the frame memories.

Abstract: A display unit includes a display panel and a drive circuit, the display panel including pixels, each pixel including a light emitting element and a pixel circuit, wherein the pixel circuit includes a first transistor being configured to sample a voltage of a signal line, a second transistor being configured to control a current applied to the light emitting element, a third transistor being connected to the source of the second transistor, and a holding capacitor configured to hold the voltage sampled by the first transistor, the drive circuit being configured to, when pixel rows are grouped into units, sequentially perform correction of adjusting a gate-to-source voltage of the second transistor to be close to a threshold voltage of the second transistor for each of the units, being configured to sequentially output a fixed voltage to a source of the second transistor before performing the correction.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: A display driving device and a method for driving a display are provided. The display driving device includes a host and a driving chip. The host transmits an image data and a synchronization signal. The driving chip receives the image data and the synchronization signal and drives a display panel to display frames. The driving chip includes a storage unit, a driving module, and a control circuit. The storage unit stores the image data. The driving module drives the display panel to display the frames according to the image data from the host and a timing generator frequency of the driving module. The control circuit detects a target frequency of the synchronization signal and the timing generator frequency of the driving module, compares the target frequency and the timing generator frequency, outputs an adjustment value according to the comparison result, and adjusts the timing generator frequency of driving module.

Abstract: An organic light emitting diode (OLED) display and driving method thereof are disclosed. One inventive aspect includes a plurality of pixels, a scan driver, first and second power generation unit and a data driver. The scan driver supplies a first scan signal to odd-numbered scan lines during a first period and a second scan signal to even-numbered scan lines during a second period. The first and second power generation units set the pixels in a non-emission state during at least one frame of the first and second periods. The data driver supplies a data signal to data lines synchronous to the first and second scan signal.