Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.

Abstract: An electronic device. The electronic device includes a first processor configured to generate a first display signal, and a second processor configured to generate a second display signal and output to a display area. The second processor includes a forwarding module, the first processor is connected to the forwarding module, and the first display signal generated by the first processor is output to the display area through the forwarding module.

Abstract: Power demand reduction for image generation for displays skips rendering of frames that are highly similar based on a comparison of certain parameters associated with draw calls. A first set of draw calls is received from a game engine by a central processing unit (CPU) circuit and then a second set of draw calls are provided to the CPU circuit. The CPU circuit compares the second set of draw calls to the first set of draw calls. If there is a change in at least one parameter that exceeds a threshold, then the CPU circuit sends the second set of draw calls to a graphics processing unit (GPU) circuit for rendering. If, however, the change in selected parameters is below the threshold, then the CPU circuit sends an earlier rendered image to the display for presentation to the user, effectively omitting usage of the GPU circuit for that frame.

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

Abstract: A computing system and methods are provided for georeferencing stabilization. An exemplary method includes: obtaining a video stream capturing an area from a camera of a drone, where the video stream includes a plurality of frames, each including a field of view of the image capturing device and metadata of the image capturing device when the frame is captured; constructing a geographic (geo) lattice for the field of view in each of the plurality of frames, the geo lattice comprises a plurality of points, each being associated with raw coordinates determined based on the corresponding metadata; and building a lattice map with stabilized geo coordinates by (1) aligning the frames, (2) averaging the raw geo coordinates for given intersection points, and (3) building the lattice map based on the averaged geo coordinates of the intersection points.

Abstract: According to certain embodiments, an electronic device comprises: a communication module; and a processor operatively connected to the communication module and configured to transmit and receive data to and from external electronic devices through the communication module, and wherein the processor is configured to: receive a preview source image from a first external electronic device; performing a first image processing on the preview source image, thereby resulting in a preview image; transmitting the preview image to a second external electronic device and a third external electronic device; receive a request for second image processing from the second external electronic device; transmit a first modified preview image obtained by performing the second image processing on the preview image to the second external electronic device in response to the request; receive a request for third image processing form the third external electronic device; transmit a second modified preview image obtained by performin

Abstract: Disclosed is a system for analysis of microscopic image data acquired from biological cells. The system includes a data processing system which is configured to read the image data and determine a plurality of vertices, wherein each of the vertices represents a location of an entity of interest within a region of interest of the image data. The data processing system generates a plurality of graphs, wherein for each of the graphs, the generation of the respective graph includes generating a plurality of edges, wherein each of the edges has two of the plurality of vertices associated therewith. For each of the graphs one or more vertex sets are identified, each of which consisting of one or more of the plurality of vertices. The data processing system further determines, for each of the graphs, a number of the identified vertex sets.

Abstract: A disclosed system may include a disaggregated artificial intelligence (AI) operation accelerator including a dense AI operation accelerator configured to accelerate dense AI operations and a sparse AI operation accelerator, physically separate from the dense AI operation accelerator, configured to accelerate sparse AI operations. The system may also include a scheduler that includes (1) a receiving module that receives an AI operation, (2) an identifying module that identifies the AI operation as a dense AI operation or sparse AI operation, and (3) a directing module that directs (a) the dense AI operation accelerator to accelerate identified dense AI operations, and (b) the sparse AI operation accelerator to accelerate identified sparse AI operations. The system may also include a physical processor that executes the receiving module, the identifying module, and the directing module. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method is disclosed for receiving a synchronization signal from a display circuit configured to display a series of frames, each frame comprising a plurality of tiles of pixels, determining, based on the received synchronization signal, that the display circuit has consumed data corresponding to one or more tiles of a frame, identifying a predetermined number of tiles that are subsequent to the one or more tiles consumed by the display circuit based on the synchronization signal, determining that one or more tiles of the identified tiles require an update, selectively rendering the determined tiles, and transmitting the rendered tiles to the display circuit.

Abstract: A system and method for synchronizing two or more display elements of a multiple element display, is disclosed. The method includes embedding a frame count signal into the blanking portion of a video frame for each data stream received by the multiple display elements. Upon displaying the pixel data from a video frame, a frame count signal containing an identifying frame count is transmitted back to the computer. The computer compares the frame count signals to determine if the multiple display elements are synchronized. Upon a determination that the multiple display elements are not synchronized, the data stream for one or more display elements are adjusted accordingly. The system may be configurated as a federated system with two or more computers each communicatively coupled to each display element in a hierarchal system, where a secondary computer can control a display element if the primary computer or primary computer link fails.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: A method for order independent transparency is described. The method includes rendering objects into an A-buffer by a GPU. A CPU performs dynamic memory allocation to allocate the A-Buffer based on a size of the previous frames A-Buffer. By allocating the A-Buffer based on a previous frame, a GPU-to-CPU synch point may be removed. Depending upon a size of the A-Buffer, not all objects may fit into the A-Buffer. The method may additionally include creating an R-Buffer with the identification of partially stored objects and removing the partially stored objects from the A-Buffer prior to blending.

Abstract: A method renders photorealistic images in a web browser. The method is performed at a computing device having a general purpose processor and a graphics processing unit (GPU). The method includes obtaining an environment map and images of an input scene. The method also includes computing textures for the input scene including by encoding an acceleration structure of the input scene. The method further includes transmitting the textures to shaders executing on a GPU. The method includes generating samples of the input scene, by performing at least one path tracing algorithm on the GPU, according to the textures. The method also includes lighting or illuminating a sample of the input scene using the environment map, to obtain a lighted scene, and tone mapping the lighted scene. The method includes drawing output on a canvas, in the web browser, based on the tone-mapped scene to render the input scene.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: A vehicle apparatus according to one embodiment of the present invention comprises: a first control unit for executing a first application for a display, wherein the first control unit transmits display information about the first application to a first display unit; a second control unit for executing a second application for the display, wherein the second control unit transmits display information about the second application to a second display unit; a first switch unit connected to the first control unit and the second control unit, wherein the first switch unit receives the display information about the first application and the display information about the second application from the first control unit and the second control unit so as to transmit the display information about the first application and the display information about the second application to the first display unit and the second display nit, respectively; and a second switch unit for receiving the display information about the first ap

Abstract: A method for graphics processing. The method including rendering graphics for an application using graphics processing units (GPUs). The method including using the plurality of GPUs in collaboration to render an image frame including a plurality of pieces of geometry. The method including during the rendering of the image frame, subdividing one or more of the plurality of pieces of geometry into smaller pieces, and dividing the responsibility for rendering these smaller portions of geometry among the plurality of GPUs, wherein each of the smaller portions of geometry is processed by a corresponding GPU. The method including for those pieces of geometry that are not subdivided, dividing the responsibility for rendering the pieces of geometry among the plurality of GPUs, wherein each of these pieces of geometry is processed by a corresponding GPU.

Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network. The method loads a first set of inputs into an input buffer and computes a first dot product between the first set of inputs and a set of weights. The method shifts the first set of inputs in the buffer while loading a second set of inputs into the buffer such that a first subset of the first set of inputs is removed from the buffer, a second subset of the first set of inputs is moved to new locations in the buffer, and a second set of inputs are loaded into locations in the buffer vacated by the shifting. The method computes a second dot product between (i) the second set of inputs and the second subset of the first set of inputs and (ii) the set of weights.

Abstract: A computer-implemented method, a computer program product, and a computer processing system are provided for selecting from among multiple Graphics Processing Unit (GPU) execution modes for a Neural Network (NN) having a size greater than a threshold size. The multiple GPU execution modes include a normal memory mode, an Out-of-Core (OoC) execution mode, and a Unified Memory (UM) mode. The method includes starting an execution on the NN with the UM mode and measuring the memory usage for each of layers of the NN. The method further includes selecting an execution mode based on the memory usage of all of the layers.

Abstract: Systems and methods are described for providing auxiliary functions in an on-demand code execution system in a manner that enables efficient execution of code. A user may generate a task on the system by submitting code. The system may determine the auxiliary functions that the submitted code may require when executed on the system, and may provide these auxiliary functions by provisioning or configuring sidecar virtualized execution environments that work in conjunction with the main virtualized execution environment executing the submitted code. Sidecar virtualized execution environments may be identified and obtained from a library of preconfigured sidecar virtualized execution environments, or a sidecar agent that provides the auxiliary function may be identified from a library, and then a virtualized execution environment may be provisioned with the agent and/or configured to work in conjunction with the main virtualized execution environment.

Abstract: Provided is a PUF by which an identification key is generated according to a random event caused by a semiconductor process variation. The PUF can provide the identification key as a result of electrical differences among elements. According to one embodiment, the PUF can accumulate the electrical differences and/or instantaneous values without generating the identification key by using the instantaneous values caused by the electrical differences. The accumulation may be the accumulation of a discrete iteration and the result thereof. However, according to another embodiment, the accumulation may be a continuation of the accumulation result during time intervals.

Abstract: A recording and reproduction control device includes a moving image data acquisition unit configured to acquire a first video stream from a camera which images a moving image at a predetermined frame rate, a trigger signal acquisition unit configured to acquire a trigger signal from an external device, a captured image generator configured to generate a captured image by one frame from the first video stream at a timing at which the trigger signal is acquired, a storage controller configured to sequentially record the captured images as a second video stream in a storage, a reproduction controller configured to reproduce the second video stream, and a frame interpolation unit configured to interpolate at least one frame image at the predetermined between the captured images and output the captured images and the interpolated frame images which are recorded in array as a third video stream in the storage.

Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

Abstract: A multiple-processor system for a multiple-lens camera is disclosed. The system comprises multiple processor components (PCs) and multiple links. Each PC comprises multiple I/O ports and a processing unit. The multiple-lens camera captures a X-degree horizontal field of view and a Y-degree vertical field of view, where X<=360 and Y<180. Each link conjects one of the I/O ports of one of the PCs to one of the I/O ports of another one of the PCs such that each PC is conjected by two or more respective links to one or two neighboring PCs. Each link is configured to transfer data in one direction.

Abstract: A nonvolatile memory device including a memory cell array including a plurality of nonvolatile memory cells and a row decoder connected with the memory cell array through wordlines may be provided. The row decoder may be configured to precharge a first wordline corresponding to a first row address from among the wordlines, in response to receiving the first row address together with a first command, and maintain a precharge state of the first wordline, in response to receiving a second row address being identical to the first row address together with a second command following the first command.

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path.

Abstract: The present disclosure advantageously provides a hardware accelerator for a natural language processing application including a first memory, a second memory, and a computing engine (CE). The first memory is configured to store a configurable NLM and a set of NLM fixed weights. The second memory is configured to store an ANN model, a set of ANN weights, a set of NLM delta weights, input data and output data. The set of NLM delta weights may be smaller than the set of NLM fixed weights, and each NLM delta weight corresponds to an NLM fixed weight. The CE is configured to execute the NLM, based on the input data, the set of NLM fixed weights and the set of NLM delta weights, to generate intermediate output data, and execute the ANN model, based on the intermediate output data and the set of ANN weights, to generate the output data.

Abstract: A digital certification system (or “analyzer”) provides protection for digital content stored on servers, file sharing systems, hard drives and USB enabled external drives or other digital repositories. The analyzer prevents unauthorized access from both owners/administrators and recipients of digital content being shared through a web based or file sharing type service. The analyzer protects the owner of the shared digital content from unauthorized access, while allowing multiple protection instances to be applied to multiple digital content shares within a digital file hosting and sharing environment. Timers are provided to limit access to digital content at the discretion of the owner of the digital content.

Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.

Abstract: A display control device that controls a display device including a display panel on which an image is rendered to display the image, the display control device includes: a host controller that obtains or generates image data of the image; and a display controller that outputs the image data to the display panel, wherein the host controller issues a request for rendering update of the image to the display controller, and transfers the image data to the display controller at a predetermined frequency; and when the display controller outputs first image data to the display panel, and then second image data is transferred from the host controller to the display controller, the display controller determines whether the first image data and the second image data are same or different from each other to determine whether or not the second image data is to be output to the display panel.

Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.

Abstract: A method, a device and a medium for allocating a resource based on a type of a PCI device are provided. In a case of running a BIOS program during a start-up process, information of a Switch chip captured by a PCI enumeration operation is acquired. It is determined whether the PCI device is connected to a GPU server based on the information of the Switch chip. An operation of allocating the PCI device with an IO resource is cancelled in a case that the PCI device is connected to the GPU server, and the PCI device is allocated with an IO resource and a memory resource based on a preset allocation rule in a case that the PCI device is not connected to the GPU server.

Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: Methods and systems for multiple-buffered display rendering without the use of hardware or software interrupts. In a first repeating process, a processor writes data for a frame a selected frame buffer and, upon completion of the frame, a swap buffer signal is transmitted. In response to the swap buffer signal, the GPU updates a memory register of the display controller to indicate that the selected frame buffer can be used in the next display synchronization interval. In a separate repeating process, the display controller monitors memory register and, in a display synchronization interval, identifies the frame buffer to use for display.

Abstract: A system includes a memory buffer, a first data processor, a second data processor, and a controller. The first data processor performs a write operation to write data into the memory buffer and provides a first reference indicating a status or progress of the write operation. The controller provides a second reference indicating a buffer block in the memory buffer. The second data processor receives the first reference and the second reference, uses a threshold and the first reference to determine whether the buffer block contains enough data to be processed by the second data processor, obtains data to be processed from the buffer block using the second reference if the buffer block contains enough data to be processed, and processes the data obtained from the buffer block.

Abstract: Fidelity-driven runtime thermal management for near-sensor architectures is provided. In this regard, a runtime controller is provided for controlling an operational mode of a vision or imaging system driven by fidelity demands. The runtime controller is responsible for guaranteeing the fidelity demands of a vision application and coordinating state transfer between operating modes to ensure a smooth transition. Under this approach, the vision application only needs to provide the runtime controller with high-level vision/imaging fidelity demands and when to trigger them. The runtime controller translates these demands into effective thermal management. To do this, the runtime controller applies application-specific requirements into appropriate policy parameters and activates temperature reduction mechanisms, such as clock gating and task offload.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enabling a variable refresh rate on a display. One of the methods includes receiving, from a content presentation device, a first signal set to a first value; completing generation of first visual content; and after completing the generation of the first visual content, determining that the first signal is set to the first value and a second threshold duration of time has not expired; sending, to the content presentation device, the first visual content, wherein sending the first visual content causes the content presentation device to change the first signal from the first value to the second value; and after sending the first visual content, receiving, from the content presentation device, the first signal set to the second value.

Abstract: Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface (“API”), direct access to non-volatile storage independent of a host central processing unit (“CPU”) on a control path or data path to perform a read operation and write operation of data.

Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Abstract: The present disclosure is directed to a method to increase virtual machine density on a server system through adaptive rendering by dynamically determining when to shift video rendering tasks between the server system and a client computing device. In another embodiment, the adaptive rendering, using various parameters, can select one or more encoding and compression algorithms to use to prepare and process the video for transmission to the client computing device. In another embodiment, a video rendering system is disclosed that can adaptively alter how and where a video is rendered, encoded, and compressed.

Abstract: An apparatus is provided to improve external graphics processing unit management. The apparatus includes a request information acquisition unit configured to acquire disconnection request information for requesting disconnection of an external signal processing device, where the external signal processing device is configured to execute at least part of signal processing in processing performed by running the application. The apparatus also includes a storage unit capable of storing files utilized by the application, and an exit control unit configured to issue a first command, the first command indicative of an instruction to exit after saving working files to the storage unit, to an application using signal processing by the signal processing device among running applications in response to the request information acquisition unit receiving the disconnection request information.

Abstract: A method for displaying a display element on at least one vehicle-side display device of a vehicle includes: transmitting, from the vehicle to a terminal via a data link, information about a size of the vehicle-side display device; providing, by the terminal, data for displaying the display element, as a function of the transmitted information about the size of the display device; and transmitting, from the terminal to the vehicle via the data link, the data for displaying the display element.

Abstract: In accordance with embodiments of the present disclosure, a method may include responsive to issuance of, by an application executing on a virtual machine of a hypervisor executing on a processor subsystem of an information handling system, an instruction triggering a virtual machine exit of the virtual machine, invoking a virtual machine exit handler of the hypervisor to handle the instruction. The method may also include determining by the virtual machine exit handler whether the instruction has a characteristic indicating that the instruction should be handled by a hardware accelerator device of the information handling system communicatively coupled to the processor subsystem and responsive to determining that the instruction has a characteristic indicating that the instruction should be handled by the hardware accelerator device, offloading by the virtual machine exit handler processing of the instruction to the hardware accelerator device.

Abstract: Embodiments of the present disclosure provide a method, a server system and a computer program product of managing resources. The method may comprise receiving a request for a first amount of resources of the dedicated processing unit from an application with an assigned priority. The method may further comprise determining a total amount of resources of the dedicated processing unit to be occupied by the application based on the request. The method may also comprise in response to the total amount approximating or exceeding a predetermined quota associated with the priority, allocating the first amount of resources of the general-purpose processing unit to the application.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

Abstract: A set of plural primitives to be processed (140) for a frame for output in a graphics processing system is divided into plural subsets of primitives (141), such that each primitive is allocated into one subset of primitives only, and each subset of primitives contains only contiguous primitives. For each subset of primitives that the set of primitives has been divided into, data representative of the primitives of the subset of primitives, and data indicating the volume of space that the subset of primitives falls within, is generated and stored (143). This data is stored as a tree representation of the set of primitives with each leaf node of the tree representing a respective sub-set of primitives that the set of primitives has been divided into (142). The tree representation of the subsets of primitives is then used, e.g., to determine respective sets of subsets of primitives that could cast a shadow from a light source for respective regions of an output frame to be generated.

Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.

Abstract: An image receiving device includes an image processing unit that rotates at least one of first and second images in a process of restoring the first and second images if an image transfer signal received by the image receiving device includes the first and second images in which a direction in which a scan line of the first image extends is different from a direction in which a scan line of the second image extends.

Abstract: A method of processing an image data for an image processing device includes a plurality of steps. The steps include receiving the image data; storing the image data in a frame buffer of the image processing device; performing a signal processing procedure on the image data obtained from the frame buffer, to generate a final display data; restoring the final display data in the frame buffer; and entering a power saving mode after the final display data is restored in the frame buffer. In the power saving mode, the image processing device performs the following steps: turning off the signal processing circuit; and outputting the final display data restored in the frame buffer, to display the final display data.

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.