Coprocessor (e.g., Graphic Accelerator) Patents (Class 345/503)
  • Patent number: 11922535
    Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Patent number: 11900004
    Abstract: A vehicle apparatus according to one embodiment of the present invention comprises: a first control unit for executing a first application for a display, wherein the first control unit transmits display information about the first application to a first display unit; a second control unit for executing a second application for the display, wherein the second control unit transmits display information about the second application to a second display unit; a first switch unit connected to the first control unit and the second control unit, wherein the first switch unit receives the display information about the first application and the display information about the second application from the first control unit and the second control unit so as to transmit the display information about the first application and the display information about the second application to the first display unit and the second display nit, respectively; and a second switch unit for receiving the display information about the first ap
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 13, 2024
    Assignee: LG Electronics Inc.
    Inventors: Hyoungkyu Choi, Jaegu Yoon, Sangwoo Han, Junbum Park
  • Patent number: 11900500
    Abstract: A method for graphics processing. The method including rendering graphics for an application using graphics processing units (GPUs). The method including using the plurality of GPUs in collaboration to render an image frame including a plurality of pieces of geometry. The method including during the rendering of the image frame, subdividing one or more of the plurality of pieces of geometry into smaller pieces, and dividing the responsibility for rendering these smaller portions of geometry among the plurality of GPUs, wherein each of the smaller portions of geometry is processed by a corresponding GPU. The method including for those pieces of geometry that are not subdivided, dividing the responsibility for rendering the pieces of geometry among the plurality of GPUs, wherein each of these pieces of geometry is processed by a corresponding GPU.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 13, 2024
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Mark E. Cerny
  • Patent number: 11886979
    Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network. The method loads a first set of inputs into an input buffer and computes a first dot product between the first set of inputs and a set of weights. The method shifts the first set of inputs in the buffer while loading a second set of inputs into the buffer such that a first subset of the first set of inputs is removed from the buffer, a second subset of the first set of inputs is moved to new locations in the buffer, and a second set of inputs are loaded into locations in the buffer vacated by the shifting. The method computes a second dot product between (i) the second set of inputs and the second subset of the first set of inputs and (ii) the set of weights.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 30, 2024
    Assignee: PERCEIVE CORPORATION
    Inventors: Kenneth Duong, Jung Ko, Steven L. Teig
  • Patent number: 11880762
    Abstract: A computer-implemented method, a computer program product, and a computer processing system are provided for selecting from among multiple Graphics Processing Unit (GPU) execution modes for a Neural Network (NN) having a size greater than a threshold size. The multiple GPU execution modes include a normal memory mode, an Out-of-Core (OoC) execution mode, and a Unified Memory (UM) mode. The method includes starting an execution on the NN with the UM mode and measuring the memory usage for each of layers of the NN. The method further includes selecting an execution mode based on the memory usage of all of the layers.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yasushi Negishi, Haruki Imai, Taro Sekiyama, Tung D. Le, Kiyokuni Kawachiya
  • Patent number: 11875173
    Abstract: Systems and methods are described for providing auxiliary functions in an on-demand code execution system in a manner that enables efficient execution of code. A user may generate a task on the system by submitting code. The system may determine the auxiliary functions that the submitted code may require when executed on the system, and may provide these auxiliary functions by provisioning or configuring sidecar virtualized execution environments that work in conjunction with the main virtualized execution environment executing the submitted code. Sidecar virtualized execution environments may be identified and obtained from a library of preconfigured sidecar virtualized execution environments, or a sidecar agent that provides the auxiliary function may be identified from a library, and then a virtualized execution environment may be provisioned with the agent and/or configured to work in conjunction with the main virtualized execution environment.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 16, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Niall Mullen, Philip Daniel Piwonka, Timothy Allen Wagner, Marc John Brooker
  • Patent number: 11849034
    Abstract: Provided is a PUF by which an identification key is generated according to a random event caused by a semiconductor process variation. The PUF can provide the identification key as a result of electrical differences among elements. According to one embodiment, the PUF can accumulate the electrical differences and/or instantaneous values without generating the identification key by using the instantaneous values caused by the electrical differences. The accumulation may be the accumulation of a discrete iteration and the result thereof. However, according to another embodiment, the accumulation may be a continuation of the accumulation result during time intervals.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: December 19, 2023
    Assignees: ICTK Holdings Co., Ltd., IUCF-BYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Byong Deok Choi, Dong Kyue Kim
  • Patent number: 11812140
    Abstract: A recording and reproduction control device includes a moving image data acquisition unit configured to acquire a first video stream from a camera which images a moving image at a predetermined frame rate, a trigger signal acquisition unit configured to acquire a trigger signal from an external device, a captured image generator configured to generate a captured image by one frame from the first video stream at a timing at which the trigger signal is acquired, a storage controller configured to sequentially record the captured images as a second video stream in a storage, a reproduction controller configured to reproduce the second video stream, and a frame interpolation unit configured to interpolate at least one frame image at the predetermined between the captured images and output the captured images and the interpolated frame images which are recorded in array as a third video stream in the storage.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: November 7, 2023
    Assignee: JVCKENWOOD Corporation
    Inventors: Hiroshi Takeshita, Yutaka Kuramochi
  • Patent number: 11775320
    Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Brian Lewis Brown
  • Patent number: 11755336
    Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey
  • Patent number: 11743600
    Abstract: A multiple-processor system for a multiple-lens camera is disclosed. The system comprises multiple processor components (PCs) and multiple links. Each PC comprises multiple I/O ports and a processing unit. The multiple-lens camera captures a X-degree horizontal field of view and a Y-degree vertical field of view, where X<=360 and Y<180. Each link conjects one of the I/O ports of one of the PCs to one of the I/O ports of another one of the PCs such that each PC is conjected by two or more respective links to one or two neighboring PCs. Each link is configured to transfer data in one direction.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: August 29, 2023
    Assignee: ASPEED TECHNOLOGY INC.
    Inventor: Chung-Yen Lu
  • Patent number: 11727965
    Abstract: A nonvolatile memory device including a memory cell array including a plurality of nonvolatile memory cells and a row decoder connected with the memory cell array through wordlines may be provided. The row decoder may be configured to precharge a first wordline corresponding to a first row address from among the wordlines, in response to receiving the first row address together with a first command, and maintain a precharge state of the first wordline, in response to receiving a second row address being identical to the first row address together with a second command following the first command.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: August 15, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunji Lee, Suk-Soo Pyo
  • Patent number: 11537543
    Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: December 27, 2022
    Assignee: Arm Limited
    Inventors: Ashok Kumar Tummala, Jamshed Jalal, Antony John Harris, Jeffrey Carl Defilippi, Anitha Kona, Bruce James Mathewson
  • Patent number: 11507841
    Abstract: The present disclosure advantageously provides a hardware accelerator for a natural language processing application including a first memory, a second memory, and a computing engine (CE). The first memory is configured to store a configurable NLM and a set of NLM fixed weights. The second memory is configured to store an ANN model, a set of ANN weights, a set of NLM delta weights, input data and output data. The set of NLM delta weights may be smaller than the set of NLM fixed weights, and each NLM delta weight corresponds to an NLM fixed weight. The CE is configured to execute the NLM, based on the input data, the set of NLM fixed weights and the set of NLM delta weights, to generate intermediate output data, and execute the ANN model, based on the intermediate output data and the set of ANN weights, to generate the output data.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 22, 2022
    Assignee: Arm Limited
    Inventors: Urmish Ajit Thakker, Ganesh Suryanarayan Dasika
  • Patent number: 11442624
    Abstract: A digital certification system (or “analyzer”) provides protection for digital content stored on servers, file sharing systems, hard drives and USB enabled external drives or other digital repositories. The analyzer prevents unauthorized access from both owners/administrators and recipients of digital content being shared through a web based or file sharing type service. The analyzer protects the owner of the shared digital content from unauthorized access, while allowing multiple protection instances to be applied to multiple digital content shares within a digital file hosting and sharing environment. Timers are provided to limit access to digital content at the discretion of the owner of the digital content.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: September 13, 2022
    Inventor: Anthony Tan
  • Patent number: 11386518
    Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: July 12, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael Mantor, Alexander Fuad Ashkar, Randy Ramsey, Mangesh P. Nijasure, Brian Emberling
  • Patent number: 11307822
    Abstract: A display control device that controls a display device including a display panel on which an image is rendered to display the image, the display control device includes: a host controller that obtains or generates image data of the image; and a display controller that outputs the image data to the display panel, wherein the host controller issues a request for rendering update of the image to the display controller, and transfers the image data to the display controller at a predetermined frequency; and when the display controller outputs first image data to the display panel, and then second image data is transferred from the host controller to the display controller, the display controller determines whether the first image data and the second image data are same or different from each other to determine whether or not the second image data is to be output to the display panel.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 19, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tatsuya Kambe
  • Patent number: 11295660
    Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 5, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Anthony W L Koo, Syed Athar Hussain
  • Patent number: 11275618
    Abstract: A method, a device and a medium for allocating a resource based on a type of a PCI device are provided. In a case of running a BIOS program during a start-up process, information of a Switch chip captured by a PCI enumeration operation is acquired. It is determined whether the PCI device is connected to a GPU server based on the information of the Switch chip. An operation of allocating the PCI device with an IO resource is cancelled in a case that the PCI device is connected to the GPU server, and the PCI device is allocated with an IO resource and a memory resource based on a preset allocation rule in a case that the PCI device is not connected to the GPU server.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 15, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Xiuqiang Sun
  • Patent number: 11188999
    Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 30, 2021
    Assignee: ARM NORWAY AS
    Inventors: Jorn Nystad, Edvard Sorgard, Borgar Ljosland, Mario Blazevic
  • Patent number: 11164496
    Abstract: Methods and systems for multiple-buffered display rendering without the use of hardware or software interrupts. In a first repeating process, a processor writes data for a frame a selected frame buffer and, upon completion of the frame, a swap buffer signal is transmitted. In response to the swap buffer signal, the GPU updates a memory register of the display controller to indicate that the selected frame buffer can be used in the next display synchronization interval. In a separate repeating process, the display controller monitors memory register and, in a display synchronization interval, identifies the frame buffer to use for display.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 2, 2021
    Assignee: Channel One Holdings Inc.
    Inventor: Tomislav Malnar
  • Patent number: 11138052
    Abstract: A system includes a memory buffer, a first data processor, a second data processor, and a controller. The first data processor performs a write operation to write data into the memory buffer and provides a first reference indicating a status or progress of the write operation. The controller provides a second reference indicating a buffer block in the memory buffer. The second data processor receives the first reference and the second reference, uses a threshold and the first reference to determine whether the buffer block contains enough data to be processed by the second data processor, obtains data to be processed from the buffer block using the second reference if the buffer block contains enough data to be processed, and processes the data obtained from the buffer block.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Dong Qin, Mingli Cui, Jin Xie, Shengbao Yin
  • Patent number: 11107181
    Abstract: Fidelity-driven runtime thermal management for near-sensor architectures is provided. In this regard, a runtime controller is provided for controlling an operational mode of a vision or imaging system driven by fidelity demands. The runtime controller is responsible for guaranteeing the fidelity demands of a vision application and coordinating state transfer between operating modes to ensure a smooth transition. Under this approach, the vision application only needs to provide the runtime controller with high-level vision/imaging fidelity demands and when to trigger them. The runtime controller translates these demands into effective thermal management. To do this, the runtime controller applies application-specific requirements into appropriate policy parameters and activates temperature reduction mechanisms, such as clock gating and task offload.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 31, 2021
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Venkatesh Kodukula, Saad Katrawala, Britton Jones, Robert LiKamWa
  • Patent number: 11094296
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enabling a variable refresh rate on a display. One of the methods includes receiving, from a content presentation device, a first signal set to a first value; completing generation of first visual content; and after completing the generation of the first visual content, determining that the first signal is set to the first value and a second threshold duration of time has not expired; sending, to the content presentation device, the first visual content, wherein sending the first visual content causes the content presentation device to change the first signal from the first value to the second value; and after sending the first visual content, receiving, from the content presentation device, the first signal set to the second value.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 17, 2021
    Assignee: Google LLC
    Inventors: Wonjae Choi, Daniel Solomon, John Kaehler
  • Patent number: 11048447
    Abstract: Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface (“API”), direct access to non-volatile storage independent of a host central processing unit (“CPU”) on a control path or data path to perform a read operation and write operation of data.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zaid Qureshi, I-Hsin Chung, Wen-Mei Hwu, Jinjun Xiong
  • Patent number: 11016790
    Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Brian Lewis Brown
  • Patent number: 11012694
    Abstract: The present disclosure is directed to a method to increase virtual machine density on a server system through adaptive rendering by dynamically determining when to shift video rendering tasks between the server system and a client computing device. In another embodiment, the adaptive rendering, using various parameters, can select one or more encoding and compression algorithms to use to prepare and process the video for transmission to the client computing device. In another embodiment, a video rendering system is disclosed that can adaptively alter how and where a video is rendered, encoded, and compressed.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 18, 2021
    Assignee: Nvidia Corporation
    Inventors: Rouslan Dimitrov, Chris Amsinck, Viktor Vandanov, Santanu Dutta, Walter Donovan, Olivier Lapicque
  • Patent number: 10970806
    Abstract: An apparatus is provided to improve external graphics processing unit management. The apparatus includes a request information acquisition unit configured to acquire disconnection request information for requesting disconnection of an external signal processing device, where the external signal processing device is configured to execute at least part of signal processing in processing performed by running the application. The apparatus also includes a storage unit capable of storing files utilized by the application, and an exit control unit configured to issue a first command, the first command indicative of an instruction to exit after saving working files to the storage unit, to an application using signal processing by the signal processing device among running applications in response to the request information acquisition unit receiving the disconnection request information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Lenovo (Singapore) PTE. LTD.
    Inventor: Yasushi Tsukamoto
  • Patent number: 10936273
    Abstract: A method for displaying a display element on at least one vehicle-side display device of a vehicle includes: transmitting, from the vehicle to a terminal via a data link, information about a size of the vehicle-side display device; providing, by the terminal, data for displaying the display element, as a function of the transmitted information about the size of the display device; and transmitting, from the terminal to the vehicle via the data link, the data for displaying the display element.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 2, 2021
    Assignee: VOLKSWAGEN AG
    Inventors: Patrick Lünnemann, Christopher Seubert
  • Patent number: 10936353
    Abstract: In accordance with embodiments of the present disclosure, a method may include responsive to issuance of, by an application executing on a virtual machine of a hypervisor executing on a processor subsystem of an information handling system, an instruction triggering a virtual machine exit of the virtual machine, invoking a virtual machine exit handler of the hypervisor to handle the instruction. The method may also include determining by the virtual machine exit handler whether the instruction has a characteristic indicating that the instruction should be handled by a hardware accelerator device of the information handling system communicatively coupled to the processor subsystem and responsive to determining that the instruction has a characteristic indicating that the instruction should be handled by the hardware accelerator device, offloading by the virtual machine exit handler processing of the instruction to the hardware accelerator device.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 2, 2021
    Assignee: Dell Products L.P.
    Inventors: Shyam T. Iyer, Gaurav Chawla
  • Patent number: 10897428
    Abstract: Embodiments of the present disclosure provide a method, a server system and a computer program product of managing resources. The method may comprise receiving a request for a first amount of resources of the dedicated processing unit from an application with an assigned priority. The method may further comprise determining a total amount of resources of the dedicated processing unit to be occupied by the application based on the request. The method may also comprise in response to the total amount approximating or exceeding a predetermined quota associated with the priority, allocating the first amount of resources of the general-purpose processing unit to the application.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 19, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Junping Zhao, Fan Guo, Kun Wang
  • Patent number: 10891223
    Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Graziano Mirichigni, Danilo Caraccio
  • Patent number: 10839600
    Abstract: A set of plural primitives to be processed (140) for a frame for output in a graphics processing system is divided into plural subsets of primitives (141), such that each primitive is allocated into one subset of primitives only, and each subset of primitives contains only contiguous primitives. For each subset of primitives that the set of primitives has been divided into, data representative of the primitives of the subset of primitives, and data indicating the volume of space that the subset of primitives falls within, is generated and stored (143). This data is stored as a tree representation of the set of primitives with each leaf node of the tree representing a respective sub-set of primitives that the set of primitives has been divided into (142). The tree representation of the subsets of primitives is then used, e.g., to determine respective sets of subsets of primitives that could cast a shadow from a light source for respective regions of an output frame to be generated.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventor: Graham Paul Hazel
  • Patent number: 10732978
    Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Mark Underwood, Hakan Lars-Goran Persson
  • Patent number: 10657929
    Abstract: An image receiving device includes an image processing unit that rotates at least one of first and second images in a process of restoring the first and second images if an image transfer signal received by the image receiving device includes the first and second images in which a direction in which a scan line of the first image extends is different from a direction in which a scan line of the second image extends.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Ken Sumitani
  • Patent number: 10636341
    Abstract: A method of processing an image data for an image processing device includes a plurality of steps. The steps include receiving the image data; storing the image data in a frame buffer of the image processing device; performing a signal processing procedure on the image data obtained from the frame buffer, to generate a final display data; restoring the final display data in the frame buffer; and entering a power saving mode after the final display data is restored in the frame buffer. In the power saving mode, the image processing device performs the following steps: turning off the signal processing circuit; and outputting the final display data restored in the frame buffer, to display the final display data.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 28, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chia-Hsin Tung, Yung-Chien Fan, Wen-Kai Hsieh, Shu-Yuan Hsu
  • Patent number: 10606760
    Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elona Erez, Avner Dor, Moshe Twitto, Jun Jin Kong
  • Patent number: 10558599
    Abstract: An apparatus for performing a method for loading a matrix into an accelerator includes an augmented direct memory access controller reading a matrix, in a data stream, from a first memory associated with a system processor and sending the matrix, in the data stream, to a second memory associated with the accelerator. The method further includes the augmented direct memory access controller extracting individual matrix elements from the data stream as the data stream is being sent to the second memory and analyzing the extracted individual matrix elements to determine if the matrix is any of a plurality of tested matrix class types as the data stream is being sent to the second memory.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 11, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael Andreas Staudenmaier, Leonardo Surico, Maik Brett
  • Patent number: 10496351
    Abstract: Automatic display unit backup during failures of one more display units through the utilization of graphic user interface objects defined for control transfer and reversion after resolution of the failures is provided herein. A system can comprise a memory operatively coupled to a processor that executes stored executable components comprising a first controller, a second controller, and a failure indication component that provides a first notification based on a first detection of a first failure at the second controller, and a second notification based on a second detection of a second failure at the first controller. Further, the executable components can comprise a control transfer component that automatically transfers control of a second display unit from the v controller to the first controller based on the first notification, or control of a first display unit from the first controller to the second controller based on the second notification.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 3, 2019
    Assignee: GE Aviation Systems LLC
    Inventor: David Allen Fairchild
  • Patent number: 10452581
    Abstract: Memory descriptor list caching and pipeline processing techniques are described. In one or more examples, a method is configured to increase efficiency of buffer usage within a pipeline of a computing device. The method includes creation of a buffer in memory of the computing device and caching of a memory descriptor list by the computing device that describes the buffer in a buffer information cache and has associated therewith a handle that acts as a lookup to the memory descriptor list. The method also includes passing the handle through the pipeline of the computing device for processing of data within the buffer by one or more stages of the pipeline such that access to the data is obtained by the one or more stages by using the handle as the lookup as part of a call to obtain the memory descriptor list for the buffer from the buffer information cache.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mei L. Wilson, Jitesh Krishnan, Sathyanarayanan Karivaradaswamy
  • Patent number: 10446118
    Abstract: An apparatus and method are described for subdividing swap chains using partitions. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; partition management logic to subdivide each of the image frames into at least two partitions and to designate each partition in each image frame as being in a front buffer or in a back buffer; the GPU to perform rendering operations to partitions designated as being in the back buffer; and a display link to concurrently perform a scan-out of scan lines from partitions designated as being in a front buffer.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Robert M. Toth
  • Patent number: 10437739
    Abstract: Methods, apparatus and associated techniques and mechanisms for reducing latency in accelerators. The techniques and mechanisms are implemented in platform architectures supporting shared virtual memory (SVM) and includes use of SVM-enabled accelerators, along with translation look-aside buffers (TLBs). A request descriptor defining a job to be performed by an accelerator and referencing virtual addresses (VAs) and sizes of one or more buffers is enqueued via execution of a thread on a processor core. Under one approach, the descriptor includes hints comprising physical addresses or virtual address to physical address (VA-PA) translations that are obtained from one or more TLBs associated with the core using the buffer VAs. Under another approach employing TLB snooping, the buffer VAs are used as lookups and matching TLB entries ((VA-PA) translations) are used as hints. The hints are used to speculatively pre-fetch buffer data and speculatively start processing the pre-fetched buffer data on the accelerator.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventor: Vinodh Gopal
  • Patent number: 10424253
    Abstract: A display device and a power monitoring circuit. The power monitoring circuit monitors whether or not first power is ordinarily output from a power management integrated circuit (PMIC). When the first power is not ordinarily output, the power monitoring circuit outputs an error detection signal indicative of an abnormality in the PMIC to a main controller. The display device includes the power monitoring circuit. The operating state of the PMIC supplying power required for the driving of a display panel can be monitored.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: September 24, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sangyong Kim, Moo Kyoung Hong
  • Patent number: 10402119
    Abstract: The present disclosure provides a data format conversion apparatus and method, and a buffer chip. The data format conversion apparatus is disposed on the buffer chip in a memory; a control module is disposed for sending a control instruction to a conversion module when obtaining a data copy command; and a conversion module is disposed for completing data format conversion and storage address mapping on to-be-converted data according to the received control instruction. In this way, a prior-art problem of additionally occupying computing resources and computation time of an accelerated computation unit due to a data format conversion unit disposed in the accelerated computation unit is avoided, the amount of data transmission between a main memory and a device memory is reduced without additionally occupying computing resources, and the computation precision is ensured while the computation efficiency is improved.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 3, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shougang Chai, Wenliang Liang, Liang Zhuang
  • Patent number: 10403027
    Abstract: The present disclosure describes a new global illumination ray tracing, applied to augmented reality and virtual reality. The Acceleration Structures of prior art are replaced by a new and novel device—a Dynamically Aligned Structure (DAS), a means for carrying out the intersection between secondary rays and scene geometry in large groups of rays, gaining high speed and lowering computational complexity. Its reduced power consumption is suitable to consumer level computing devices.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: September 3, 2019
    Assignee: ADSHIR LTD.
    Inventors: Reuven Bakalash, Elad Haviv
  • Patent number: 10402934
    Abstract: Disclosed is a system for producing images including techniques for reducing the memory and processing power required for such operations. The system provides techniques for programmatically representing a graphics problem. The system further provides techniques for reducing and optimizing graphics problems for rendering with consideration of the system resources, such as the availability of a compatible GPU.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 3, 2019
    Assignee: Apple Inc.
    Inventors: John Harper, Ralph Brunner, Peter Graffagnino, Mark Zimmer
  • Patent number: 10395416
    Abstract: The present disclosure describes a new method for rendering ray traced reflections, applied to augmented reality and virtual reality. The intersections between secondary rays and scene geometry are done in large groups of rays, gaining high speed and lowering the computational complexity. Its reduced power consumption is suitable to consumer class of computing devices.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 27, 2019
    Assignee: ADSHIR LTD.
    Inventor: Reuven Bakalash
  • Patent number: 10387343
    Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chachi Ching, John A. Flanders, Michael J. Healy, Kevin J. Twilliger, Jason A. Viehland
  • Patent number: 10347043
    Abstract: Improved techniques of managing graphical user interface (GUI) objects based on portal layers (or simply portals) are described. A portal refers to a logical reference to a GUI object specified by an application that enables an operating system to access and process the specified GUI object without affecting any of the rules/assumptions required by the application for the specified GUI object. Portals can assist with reducing computational resources required for rendering by assisting with reducing or eliminating the use of snapshots for rendering. One embodiment includes generating a layer tree; identifying a first sub-tree of the layer tree as portal content; establishing a portal as a reference to the portal content in a second sub-tree of the layer tree; generating a render tree based on the layer tree; rendering the render tree to create an image; and presenting the image on a display.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: Bartosz Ciechanowski, Chendi Zhang
  • Patent number: 10346941
    Abstract: Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: Richard W. Schreyer, Kenneth C. Dyke, Alexander K. Kan