Abstract: A method may include during a pre-operating system environment writing user graphics data to a discrete graphics controller and an embedded graphics controller of a service processor integral to the information handling system and storing user graphics data written to the embedded graphics controller in a frame buffer such that a remote management information handling system remotely coupled to the information handling system via the service processor may receive user graphics data from the frame buffer.

Abstract: An accelerator work allocation mechanism determines at run-time which functions to allocate to a hardware accelerator based on a defined accelerator policy, and based on an analysis performed at run-time. The analysis includes reading the accelerator policy, and determining whether a particular function satisfies the accelerator policy. If so, the function is allocated to the hardware accelerator. If not, the function is allocated to the processor.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: An accelerator work allocation mechanism determines at run-time which functions to allocate to a hardware accelerator based on a defined accelerator policy, and based on an analysis performed at run-time. The analysis includes reading the accelerator policy, and determining whether a particular function satisfies the accelerator policy. If so, the function is allocated to the hardware accelerator. If not, the function is allocated to the processor.

Abstract: The present invention extends to methods, systems, and computer program products for para-virtualized GPGPU computation and GDI acceleration. Some embodiments provide a compute shader to a guest application within a para-virtualized environment. A vGPU in a child partition presents compute shader DDIs for performing GPGPU computations to a guest application. A render component in a root partition receives compute shader commands from the vGPU and schedules the commands for execution at the physical GPU. Other embodiments provide GPU-accelerated GDI rendering capabilities to a guest application within a para-virtualized environment. A vGPU in a child partition provides an API for receiving GDI commands, and sends GDI commands and data to a render component in a root partition. The render component schedules the GDI commands on a 3D rendering device. The 3D rendering device executes the GDI commands at the physical GPU using a sharable GDI surface.

Abstract: Frames are rendered by multiple graphics processors (GPUs), which may be heterogeneous. Graphics processors split the execution of the command in a push buffer of a frame. One GPU begins rendering a frame, and a second GPU takes over rendering that frame after the second GPU is done rendering a previous frame. The second GPU may then begin rendering a subsequent frame.

Abstract: A scalable discrete graphics system (DGS) is disclosed. The DGS includes a serial bus bridge configured to couple a plurality of GPUs to a serial bus. A serial bus connector is coupled to the serial bus bridge. A system chassis coupled to the serial bus bridge and the serial bus connector and configured to house the GPUs. The serial bus connector is configured to removably connect to a computer system. The GPUs access the computer system via the serial bus bridge and the serial bus connector to cooperatively execute 3-D graphics instructions from the computer system.

Abstract: An image-displaying device includes a first storage section, an image data generation section, a timing information acquisition section and a display control section. The image data generation section is configured to output the image data to the first storage section with the image data being composed of a plurality of predetermined data units. The timing information acquisition section is configured to acquire timing information indicative of a timing related to generation and output of the image data to the first storage section with respect to each of the predetermined data units. The display control section is configured to control a display section to read and display an Nth one of the predetermined data units after output of an (N+i)th one of the predetermined data units to the first storage section is completed according to the timing information, where N is a natural number and i is a nonnegative integer.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: Apparatuses and methods for prioritizing the allocation of video acceleration hardware in video playback systems. Smooth, high-definition video playback may be provided with a system that may include multiple web browsers, web browser tabs, video players, or media players by allocating hardware acceleration resources to for individual videos based on each video's priority in a predefined priority configuration. Priority of an individual video may be based on the visibility of the video to a system user or the order in which a video was requested by a user. Videos that are visible on a display screen may have a higher priority than videos that are hidden or obscured. Videos that are started or opened more recently than other videos may have a higher priority. A priority management unit may coordinate the allocation of video playback acceleration resources dynamically as the priority ranking of videos change in response to user input.

Abstract: An image processing apparatus and an image processing method are provided. Each of the image processing apparatus and the image processing method sets to a first setting data storage area an address enabling an access, for each one of sets of application software, to an address window in memory space accessible by a first processor, sets to a second setting data storage area an address of an address window in memory space of a second memory, for each one of the sets of application software, and transfers image data drawn on a first memory to the second memory via an address window specified by the application software, where the first setting data storage area and the second setting memory are included in a second processor and provided for each one of the sets of application software.

Abstract: Embodiments of a system and method for enhanced video performance in a video playback system are generally described herein. In some embodiments, a video frame from a video element in a web page, which is to be presented in a web browser and is unobscured by any other elements associated with the web page, the web browser, or a user interface, is directly rendered by a hardware decoder and composited with any associated web content or other elements directly to a video playback display device. When a video frame from the video element is obscured by another element the video frame is rendered by a processor in the video playback display device in order to incorporate the non-video graphics element on the video playback device.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: A terminal equipped with a central processing unit (CPU) and a graphics processing unit (GPU) performs a method for executing applications in adaptation to the load of the CPU and GPU. The application execution method of the present invention includes checking, when a code of application to be executed is input, workloads of a central processing unit and a graphics processing unit. The method also includes comparing the workloads of the central processing unit and the graphics processing unit with respective workload threshold values, and compiling the code according to comparison result. The method further includes generating a binary for executing the application at one of the central processing unit and the graphics processing unit using the compiled code, and executing the application with the generated binary. The method reduces application execution time by adjusting the workloads of the CPU and GPU according to the total workload, thereby saving power.

Abstract: Disclosed are methods and systems for multimedia scripting, including evaluating a script at runtime and invoking a process for editing multimedia in dependence upon the script. Multimedia may include a still image and video images. Multimedia scripting may also include accepting text entered into a text-input graphical user interface as a script for runtime evaluation, accepting from a non-text-based graphical user interface a designation of scripts for runtime evaluation, and effecting a disposition of the edited multimedia in dependence upon a script, such as storing the multimedia as a file, presenting the multimedia, or encoding the edited multimedia as an email attachment.

Abstract: The present disclosure relates to a system for routing data across a multicore processing network. The system includes a multicore processing array having a plurality of processing cores, a memory for storing data relating to an object being modeled, the data being associated with coordinate information relating to the object within a coordinate system, and a controller for routing the data from the memory to one or more of the plurality of processing cores of the multicore processing array based on the coordinate information associated with the data. The present disclosure also relates to a method for routing data across a multicore processing network and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for routing data across a multicore processing network.

Abstract: A method for offloading remote terminal services processing tasks to a peripheral device that would otherwise be performed in a computer system's processor and memory. In one embodiment, the disclosed method is utilized in a layered network model, wherein computing tasks that are typically performed in network applications are instead offloaded to a peripheral such as a network interface card (NIC).

Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.

Abstract: In embodiments of display co-processing, a computing device includes a display, a full-power processor, and a low-power processor that can alter visual content presented by the display without utilizing the full-power processor. The low-power processor can, responsive to a request from the full-power processor, generate additional display data to update display data stored in a frame-buffer of the display. The low-power processor can then transmit the additional display data to the frame-buffer effective to alter at least a portion of the visual content presented by the display. In some embodiments, the additional display data is transmitted via a protocol converter that forwards the display data to the display using a display-specific communication protocol.

Abstract: A display system and method for displaying an image on a non-planar display that allows the images to be mapped by image mappers while encompassing image data of an adjacent sub-image or sub-images. This allows a single unified image to be displayed in real time without any tearing or positional/angular artifacts at the image boundaries.

Abstract: To realize effective load distribution and improve the performance in image formation processing, an image processing apparatus includes a first image processing unit configured to perform image processing on a drawing area, a second image processing unit configured to be differentiated from the first image processing unit, a load analysis unit configured to analyze a composition processing load of an object in the drawing area, a rotational angle analysis unit configured to analyze a rotational angle of the object in the drawing area, and a load distribution determination unit configured to determine whether to distribute a part of image formation processing to be applied on the drawing area from the first image processing unit to the second image processing unit based on the analyzed composition processing load of the object and the analyzed rotational angle of the object.

Abstract: Graphics processing units (GPUs) deployed in general purpose GPU (GPGPU) units are combined into a GPGPU cluster. Access to the GPGPU cluster is then offered as a service to users who can use their own computers to communicate with the GPGPU cluster. The users develop applications to be run on the cluster and a profiling module tracks the applications' resource utilization and can report it to the user and to a subscription server. The user can examine the report to thereby optimize the application or the cluster's configuration. The subscription server can interpret the report to thereby invoice the user or otherwise govern the users' access to the cluster.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria.

Abstract: An image data processing apparatus includes: a plurality of operational processing circuits each of which is configured to have a variable circuit configuration and to execute operational processing on image data; and a control section that controls each of the operational processing circuits such that each of the operational processing circuits executes one of a plurality of types of operational processing performed on image data in a predetermined order. The control section controls each of the operational processing circuits so that when image data to be newly given to one of the operational processing circuits is interrupted, said one of the operational processing circuits and another one of the operational processing circuits execute operational processing by taking partial charge of the operational processing.

Abstract: The disclosed embodiments provide a system that facilitates seamlessly switching between graphics-processing units (GPUs) to drive a display. In one embodiment, the system receives a request to switch from using a first GPU to using a second GPU to drive the display. In response to this request, the system uses a kernel thread which operates in the background to configure the second GPU to prepare the second GPU to drive the display. While the kernel thread is configuring the second GPU, the system continues to drive the display with the first GPU and a user thread continues to execute a window manager which performs operations associated with servicing user requests. When configuration of the second GPU is complete, the system switches the signal source for the display from the first GPU to the second GPU.

Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

Abstract: Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data producer and a co-processor graphic data consumer via a direct link without passing such communications through the central processing unit.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.

Abstract: A method for tag logic score boarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality of pixels of pixels related to the graphics primitive. The method further includes accounting for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics pipeline and accounting for a completion of parameter evaluation for each of the plurality of pixels as the pixels complete processing in the subsequent stage of the graphics pipeline. Respective tag memory is allocated to track the initiation of parameter evaluation and the completion of parameter evaluation for each of the plurality of pixels.

Abstract: The specification and drawings present a new method, apparatus and software related product (e.g., a computer readable memory) for sequential rendering (including hardware acceleration) each primary color of a plurality of primary colors in each frame of an image separately in a space-time domain for displaying on field-sequential color (FSC) displays. Instead of rendering whole pixels, various embodiments provide rendering of each primary color plane separately in the space-time domain, and serializing/sequencing the colors of the the rendered data directly to the bus that is connecting a host (an operator device) and the FSC display. Generally the number of primary colors may be two or more. When displayed on a FSC display, motion quality may be largely improved.

Abstract: The present invention provides a method and system for coordinating graphics processing units in a single computing system. A method is disclosed which allows for the construction of a list of shared display modes that may be employed by both of the graphics processing units to render an output in a display device. By creating the list of shared commonly supportable display modes, the output displayed in the display device may advantageously provide a consistent graphical experience persisting through the use of alternate graphics processing units in the system. One method builds a list of shared display modes by compiling a list from a GPU specific base mode list and dynamic display modes acquired from an attached display device. Another method provides the ability to generate graphical output configurations according to a user-selected display mode that persists when alternate graphics processing units in the system are used to generate graphical output.

Abstract: Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.

Abstract: The present invention related to processing image frames through a pipeline of effects by breaking the image frames into multiple blocks of image data. The example method includes generating a plurality of blocks from each frame, processing each block through a pipeline of effects in a predefined consecutive order, and aggregating the processed blocks to produce an output frame by combining the primary pixels from each processed block. The pipeline of effects may be distributed over a plurality of processing nodes, and each effect may process a block, provided as input to the node. Each processing node may independently process a block using an effect.

Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Abstract: Encoding a graphical element for processing can utilize an edge pair format in which the graphical element is divided into multiple objects, where each object contains exactly two edges which do not cross or self-intersect. Another format is a run-length encoding (RLE) format in which the graphical element is divided into multiple lines, where the RLE format includes an X start position, a Y start position, a length of a first of the lines, and, for each subsequent line, indications of right and left edge steps relative to the immediately proceeding line.

Abstract: A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.

Abstract: A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.

Abstract: A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space.

Abstract: A multi-graphics processor system includes a CPU; a first GPU connected to the CPU via an input/output interface; and a second GPU connected to the first GPU via a second-GPU interface. The first GPU is provided with a second-GPU bus for communicating the CPU and the second GPU via the second-GPU interface. The CPU communicates with the second GPU via the second-GPU bus after receiving a signal indicating the timing of the data communication.

Abstract: A first GPU is provided with a digital video output terminal (Vout terminal) for connection to an external source. A digital video signal output from the Vout terminal is provided to a display device via a HDMI. The first GPU and a second GPU are connected to each other via a data bus for bidirectional data exchange. The second GPU applies a predetermined rendering process on data provided from the first GPU via a data input and output interface. The rendered data is returned to the first GPU via the data input and output interface. The first GPU processes the data returned from the second GPU as necessary and outputs a digital video signal via the Vout terminal and the HDMI.

Abstract: Disclosed is a system for producing images including an application program interface. The system includes an API and techniques for creating images by defining relationships between filters and images, such relationships programmatically assembled in an object by a cooperative session between a requesting application and a graphics services resource. The system also includes aspects regarding optimization of the programmatically assembled object and techniques for rendering in multi-processor environment.

Abstract: A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.