Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: Systems and methods for layering multiple graphics planes on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A composite graphics plane is received from a graphics processing path, wherein the composite graphics plane comprises a set of graphics macroblocks. The composite graphics plane comprises a plurality of layered graphics planes. The composite graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.

Abstract: A mapping engine maps general processing clusters (GPCs) within a parallel processing subsystem to screen tiles on a display screen based on the number of enabled streaming multiprocessors (SMs) within each GPC. A given GPC then generates pixels for the screen tiles to which the GPC is mapped. One advantage of the disclosed technique is a given GPC performs a fraction of the processing tasks associated with the parallel processing subsystem that is roughly proportional to the fraction of SMs included within the GPC.

Abstract: The present invention extends to methods, systems, and computer program products for providing asymmetric Graphical Processing Unit (“GPU”) processors in a para-virtualized environment. A virtual GPU (“vGPU”) within a child partition of the para-virtualized environment includes a kernel-mode driver (“KMD”) and a user-mode driver (“UMD”). The KMD includes a plurality of virtual nodes. Each virtual node performs a different type of operation in parallel with other types of operations. The KMD is declared as a multi-engine GPU. The UMD schedules operations for parallel execution on the virtual nodes. A render component within a root partition of the para-virtualized environment executes GPU commands received from the vGPU at the physical GPU. A plurality of memory access channels established between the KMD and the render component communicate GPU commands between a corresponding virtual node at the KMD and the render component.

Abstract: Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: An external support system and method for a mobile device are disclosed. The external support system can include, but is not limited to, processing support for computational intensive tasks such as graphics processing, additional memory for data storage and communications support (e.g., 4G LTE) to augment the mobile device capabilities.

Abstract: An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPU), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards (this includes but is not limited to PCI-Express, PCI-X, USB 2.0, or functionally similar technologies). The controller handles most of the primitive operations needed to set up and control GPU computation. As a result, the computer's central processing unit (CPU) is freed from this function and is dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are the information exchanged between CPU and the expansion card.

Abstract: The described embodiments provide a system that facilitates a switch from using a first graphics-processing unit (GPU) to using a second GPU to drive a display. During operation, upon generation of a request to switch from using the first GPU to using the second GPU as a signal source for driving the display, the system obtains a transform (such as a lookup table) that enables the displayed color output from the second GPU to substantially match the displayed color output from the first GPU. The system then makes the transform available for use by the second GPU in driving the display.

Abstract: One embodiment of a field changeable rendering system includes an output device interfaced to a motherboard, a fixed rendering device mounted to the motherboard for generating information to be output on said output device, a connector for attaching a field-changeable rendering card to the motherboard, said field-changeable rendering card capable of housing a discrete rendering device for generating information to be output on said output device and detection circuitry for detecting that a field-changeable rendering card housing a discrete rendering device is coupled to said connector and causing information from said field-changeable rendering card housing a discrete rendering device to be output on said output device. One advantage of the disclosed edge connector is that it is compatible with a plurality of graphics cards and systems, thereby enabling a computing device user to upgrade the existing device's graphics system.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: A message passing scheme for MAP inference on Markov Random Fields based on a message computation using an intermediate input vector I, an output message vector M, an auxiliary seed vector S, all of equal length N, and a pairwise function r=d(x,y), where r,x,y are real numbers, includes: for each element j of vector S, do S(j)=j consider an index distance ?=2?floor(log2(N)); repeat while ?>0 for each index of vector I, namely i, do in parallel: consider the set of all indices within distance A from a given i, augmented by i; for every k belonging to this set, calculate its distance from i using the function: d(i,k)+I(S(k)); find the minimum distance and call n the index corresponding to this minimum distance do S(i)=S(n) ?=floor (?/2) for each j of vector M, do M(j)=I(S(j))+d(j,S(j)).

Abstract: Apparatus having corresponding methods comprise a processing core performance monitoring module adapted to receive indications of performance levels of a plurality of processing cores, the plurality of processing cores comprising a central processing unit (CPU), a video accelerator, and a graphics accelerator; a video accelerator performance monitoring module adapted to receive an indication of a performance level of the video accelerator; a graphics accelerator performance monitoring module adapted to receive an indication of a performance level of the graphics accelerator; and a processor core management module adapted to dynamically allocate at least one of a pre-processing task and a post-processing task of a multimedia workload to any one of the video accelerator, the graphics accelerator, and the CPUprocessing cores based on the performance levels of the video accelerator, the graphics accelerator, and the CPU.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: In general, this disclosure relates to techniques for using graphics instructions and state information received from a graphics device to visually create a graphics image. Performance analysis may also be conducted to identify potential bottlenecks during instruction execution on the graphics device. One example device includes a display device and one or more processors. The one or more processors are configured to receive a plurality of graphics instructions from an external graphics device, wherein the graphics instructions are executed by the external graphics device to display a graphics image, and to receive state information from the external graphics device, wherein the state information is associated with execution of the graphics instructions on the external graphics device. The one or more processors are further configured to display, on the display device, a representation of the graphics image according to the graphics instructions and the state information.

Abstract: Backlit LCD displays are becoming commonplace within many vehicle applications. The unique advantage of this invention is that it optimizes system power savings for display of low dynamic range (LDR) images by dynamically controlling spatially adjustable backlighting. This is accomplishes through use of a control technique that takes into account the sequential nature of the video display process.

Abstract: A software layer is disposed between an application and a driver. In use, the software layer is adapted to receive an object from the application intended to be rendered by a first graphics processor. Such software layer, in turn, routes the object to a second graphics processor, based on a policy.

Abstract: A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A system and method force a display device to receive the output produced by a graphics processing unit that is configured as the video graphics array (VGA) boot device for display of critical system screens. A hybrid computer system that includes multiple graphics processors configures a display multiplexor to select image data from one of the multiple graphics processing units for output to the display device. When a critical system event occurs and the graphics processing unit that is selected is not configured as the VGA boot device, system basic input/output system (BIOS) interfaces are used to configure the multiplexor to select the one graphics processing unit that is configured as the VGA boot device to output the critical system screen to the display device.

Abstract: In processing a game scene for display, in one embodiment input controller position information from a host memory is provided directly to a graphics processor rather than first being processed by a 3D application in a host processor. This results in more direct and timely processing of position information and reduces the number of 3D processing pipeline steps the controller position information must pass through thus reducing the user's perceived latency between moving the input controller and seeing the displayed results. In another embodiment, the input controller position information is provided directly from an input controller to a graphics card or subsystem rather than first going through a host processor or memory. This results in even more direct and timely processing of position information by further reducing the number of 3D processing pipeline steps the controller position information must pass through thus further reducing the user's perceived latency.

Abstract: A method of server site rendering 3D images on a server computer coupled to a client computer wherein the client computer instructs a server computer to load data for 3D rendering and sends a stream of rendering parameter sets to the server computer, each set of rendering parameters corresponding with an image to be rendered; next the render computer renders a stream of images corresponding to the stream of parameter sets and the stream of images is compressed with a video compression scheme and sent from the server computer to the client computer where the client computer decompresses the received compressed video stream and displays the result in a viewing port. The rendering and communication chain is subdivided in successive pipeline stages that work in parallel on successive rendered image information.

Abstract: A method includes performing a task in response to a request of a secondary user interface of a secondary device. The method also includes calculating a utilization of a graphics processing unit of a machine based on the task performed by the graphics processing unit. The method further includes determining the utilization, through a processor, based on a comparison of a consumption of a computing resource of the graphics processing unit and a sum of the computing resource available. The method furthermore includes performing another task in response to the request of another secondary user interface of another secondary device. The method furthermore includes calculating another utilization of another graphics processing unit based on the another task performed by the another graphics processing unit. The method furthermore includes determining the another utilization based on the comparison of a consumption of the computing resource of the another graphics processing unit.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Abstract: The present invention extends to methods, systems, and computer program products for para-virtualized GPGPU computation and GDI acceleration. Some embodiments provide a compute shader to a guest application within a para-virtualized environment. A vGPU in a child partition presents compute shader DDIs for performing GPGPU computations to a guest application. A render component in a root partition receives compute shader commands from the vGPU and schedules the commands for execution at the physical GPU. Other embodiments provide GPU-accelerated GDI rendering capabilities to a guest application within a para-virtualized environment. A vGPU in a child partition provides an API for receiving GDI commands, and sends GDI commands and data to a render component in a root partition. The render component schedules the GDI commands on a 3D rendering device. The 3D rendering device executes the GDI commands at the physical GPU using a sharable GDI surface.

Abstract: An image processing system in the medical field is provided. The system for processing image data includes at lest two graphics processors, at least one renderer module for rendering image data and at least one reconstruction module for volume reconstruction. In a first operating mode of the system in which at least one reconstruction module is inactive, the instructions of at least one renderer module is able to be executed by at least two of the graphics processors. In a second operating mode of the system in which at least one reconstruction module is active, the instructions of at least one renderer module and the instructions of at least one reconstruction module is able to be executed separately on different graphics processors of the said graphics processors. During operation in one of the two operating modes, a switch can be made to the other operating mode in each case.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory to store corresponding data; a first processor to separate the action script from other data; and a second processor to convert a plurality of descriptive elements of the action script into a plurality of operational codes, and to perform an operation corresponding to an operational code of the plurality of operational codes using the corresponding data to generate pixel data for the graphical image. In exemplary embodiments the second processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: There is provided an information processing apparatus, including a first processing unit capable of processing an image, a second processing unit capable of processing the image in parallel for each unit dividing the image, and a controller section configured to perform a control to select one of the first processing unit, the second processing unit, and both of them as a subject or subjects processing the image, to divide, in a case where both the first processing unit and the second processing unit are selected, the image into a first region and a second region, and to assign processing of an image of the first region and processing of an image of the second region, which are obtained by the division, to the first processing unit and the second processing unit, respectively, to cause the first processing unit and the second processing unit to perform the processing.

Abstract: Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold.

Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: A DGS (discrete graphics system) unit is disclosed. The DGS unit includes a system chassis configured to house a GPU, the GPU for executing 3-D graphics instructions, and a GPU mounting unit coupled to the system chassis and configured to receive the GPU. A serial bus connector is coupled to the chassis and is coupled to the GPU mounting unit, wherein the serial bus connector is configured removably connect the GPU to a computer system to enable the GPU to access the computer system via the serial bus connector and execute the 3-D graphics instructions for the computer system. A power supply coupled to the system chassis for supplying power to the GPU independent of the computer system.

Abstract: Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: A variable rendering system is described that automatically transitions between hardware-accelerated rendering and software rendering of application data based on system performance and without user interaction or noticeable impact on the user experience. When hardware-accelerated rendering is available, the system renders application data using hardware-accelerated rendering. If an event occurs that causes hardware-accelerated rendering to fail, then the system dynamically transitions from hardware-accelerated rendering to software-accelerated rendering. Periodically, the system attempts to transition back to hardware-accelerated rendering.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image.

Abstract: A display controller which prevents the duplication of functional parts and processes and which displays dynamic content on a plurality of displays is provided. A terminal used as the controller has a shared dynamic image decoder which decodes the dynamic content. A first frame buffer used by the terminal stores the decoded dynamic content. A buffer transfer unit sends the dynamic content stored in the first frame buffer to a second frame buffer used by an external monitor. A terminal display displays the dynamic content stored in the first frame buffer on a display of the terminal. An external monitor interface displays the dynamic content stored in the second frame buffer on an external monitor.

Abstract: Techniques for GPU self throttling are described. In one or more embodiments, timing information for GPU frame processing is obtained using a timeline for the GPU. This may occur by inserting callbacks into the GPU processing timeline. An elapsed time for unpredictable work that is inserted into the GPU workload is determined based on the obtained timing information. A decision is then made regarding whether to “throttle” designated optional/non-critical portions of the work for a frame based on the amount of elapsed time. In one approach the elapsed time is compared to a configurable timing threshold. If the elapsed time exceeds the threshold, work is throttled by performing light or no processing for one or more optional portions of a frame. If the elapsed time is less than the threshold, heavy processing (e.g., “normal” work) is performed for the frame.

Abstract: A discrete graphics system (DGS) for executing 3D graphics instructions for a computer system is disclosed. The discrete graphics system includes a GPU for executing 3D graphics instructions and a DGS system chassis configured to house the GPU. A serial bus connector coupled is to the GPU and the DGS chassis. The serial bus connector is configured to removably connect the DGS and the GPU to the computer system. The GPU of the DGS accesses the computer system via the serial bus connector to execute the 3D graphics instructions for the computer system.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: A method is provided for optimizing computer processes executing on a graphics processing unit (GPU) and a central processing unit (CPU). Process data is subdivided into sequentially processed data and parallel processed data. The parallel processed data is subdivided into a plurality of data blocks assigned to a plurality of processing cores of the GPU. The data blocks on the GPU are processed with other data blocks in parallel on the plurality of processing cores. Sequentially processed data is processed on the CPU. Result data processed on the CPU is returned.

Abstract: Synchronized access to a shared surface from multiple rendering contexts is provided. Only one rendering context is allowed to access a shared surface at a given time to read from and write to the surface. Other non-owning rendering contexts are prevented from accessing and rendering to the shared surface while the surface is currently owned by another rendering context. A non-owning rendering context makes an acquire call and waits for the surface to be released. When the currently owning rendering context finishes rendering to the shared surface, it release the surface. The rendering context that made the acquire call then acquires access and renders to the shared surface.