Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: A DGS (discrete graphics system) unit is disclosed. The DGS unit includes a system chassis configured to house a GPU, the GPU for executing 3-D graphics instructions, and a GPU mounting unit coupled to the system chassis and configured to receive the GPU. A serial bus connector is coupled to the chassis and is coupled to the GPU mounting unit, wherein the serial bus connector is configured removably connect the GPU to a computer system to enable the GPU to access the computer system via the serial bus connector and execute the 3-D graphics instructions for the computer system. A power supply coupled to the system chassis for supplying power to the GPU independent of the computer system.

Abstract: Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image.

Abstract: A variable rendering system is described that automatically transitions between hardware-accelerated rendering and software rendering of application data based on system performance and without user interaction or noticeable impact on the user experience. When hardware-accelerated rendering is available, the system renders application data using hardware-accelerated rendering. If an event occurs that causes hardware-accelerated rendering to fail, then the system dynamically transitions from hardware-accelerated rendering to software-accelerated rendering. Periodically, the system attempts to transition back to hardware-accelerated rendering.

Abstract: A display controller which prevents the duplication of functional parts and processes and which displays dynamic content on a plurality of displays is provided. A terminal used as the controller has a shared dynamic image decoder which decodes the dynamic content. A first frame buffer used by the terminal stores the decoded dynamic content. A buffer transfer unit sends the dynamic content stored in the first frame buffer to a second frame buffer used by an external monitor. A terminal display displays the dynamic content stored in the first frame buffer on a display of the terminal. An external monitor interface displays the dynamic content stored in the second frame buffer on an external monitor.

Abstract: Techniques for GPU self throttling are described. In one or more embodiments, timing information for GPU frame processing is obtained using a timeline for the GPU. This may occur by inserting callbacks into the GPU processing timeline. An elapsed time for unpredictable work that is inserted into the GPU workload is determined based on the obtained timing information. A decision is then made regarding whether to “throttle” designated optional/non-critical portions of the work for a frame based on the amount of elapsed time. In one approach the elapsed time is compared to a configurable timing threshold. If the elapsed time exceeds the threshold, work is throttled by performing light or no processing for one or more optional portions of a frame. If the elapsed time is less than the threshold, heavy processing (e.g., “normal” work) is performed for the frame.

Abstract: A discrete graphics system (DGS) for executing 3D graphics instructions for a computer system is disclosed. The discrete graphics system includes a GPU for executing 3D graphics instructions and a DGS system chassis configured to house the GPU. A serial bus connector coupled is to the GPU and the DGS chassis. The serial bus connector is configured to removably connect the DGS and the GPU to the computer system. The GPU of the DGS accesses the computer system via the serial bus connector to execute the 3D graphics instructions for the computer system.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: A method is provided for optimizing computer processes executing on a graphics processing unit (GPU) and a central processing unit (CPU). Process data is subdivided into sequentially processed data and parallel processed data. The parallel processed data is subdivided into a plurality of data blocks assigned to a plurality of processing cores of the GPU. The data blocks on the GPU are processed with other data blocks in parallel on the plurality of processing cores. Sequentially processed data is processed on the CPU. Result data processed on the CPU is returned.

Abstract: Synchronized access to a shared surface from multiple rendering contexts is provided. Only one rendering context is allowed to access a shared surface at a given time to read from and write to the surface. Other non-owning rendering contexts are prevented from accessing and rendering to the shared surface while the surface is currently owned by another rendering context. A non-owning rendering context makes an acquire call and waits for the surface to be released. When the currently owning rendering context finishes rendering to the shared surface, it release the surface. The rendering context that made the acquire call then acquires access and renders to the shared surface.

Abstract: A video processing system, method, and computer program product are provided for encrypting communications between a plurality of graphics processors. A first graphics processor is provided. Additionally, a second graphics processor in communication with the first graphics processor is provided for collaboratively processing video data. Furthermore, such communication is encrypted.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: Example embodiments of the present invention include systems and methods for the efficient rendering of multiple light sources, each controlled individually, in a single pass. An example embodiment encodes the light sources in a texture map, such as DXT. Each channel of the multi-channel texture map encodes data associated with a light source. The pixel shader then renders multiple light sources according to the multiple channels of the texture. Additionally, the pixel shader may render multiple textures, and thus render an even greater number of individual light sources. In a further embodiment, the rendering of a plurality of individually controlled light sources is accomplished in a single pass.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: A DDA 34 notifies the coordinates of a rasterized pixel to an exclusive control part 40, acquires a unique identification number associated with the pixel position from the exclusive control part 40, and adds the identification number to pixel data and supplies it to a shader 20. A plurality of shader pipes 22 in the shader 20 perform arithmetic processing for rendering pixels in parallel, and writes the processing results to a frame buffer 50. When performing an arithmetic instruction that requires exclusive control over a pixel, each shader pipe 22 issues a request to lock the pixel by notifying the identification information added to that pixel to the exclusive control part 40. If the lock request is accepted, the shader pipe 22 performs the arithmetic processing on that pixel. If the lock request is rejected, the shader pipe suspends and puts the arithmetic processing on that pixel into a wait state, and executes arithmetic processing on another pixel in the interim.

Abstract: A method and an apparatus for determining a dependency relationship between graphics commands based on availability of graphics hardware resources to perform graphics processing operations according to the dependency relationship are described. The graphics commands may be received from graphics APIs (application programming interfaces) for rendering a graphics object. A graphics driver may transmit a portion or all of the received graphics commands to a graphics processing unit (GPU) or a media processor based on the determined dependency relationship between the graphics commands.

Abstract: One embodiment of the present invention sets forth a method for managing a power state of an audio device resident in a graphics processing unit. The method includes the steps of directing audio data originated from a client application via an audio path in an audio driver stack to the audio device, determining whether an active stream of audio data along the audio path is present in response to a notification of an attempt to shut down the graphics processing unit, and requesting a plug and play manager to disable the audio device, if no active stream of audio data is present along the audio path.

Abstract: Disclosed are an apparatus and a method for processing data, capable of controlling the use of a graphic controller based on data usage in a memory, a variation speed of a memory data value, and/or operating states/conditions of a system.

Abstract: A method of executing a physics simulation is performed in a system comprising a computational platform, a main application stored in the computational platform, a secondary application stored in the computational platform, and a cloth application programming interface (API) implemented in the computational platform. The method defines a cloth simulation call in the cloth API, and by operation of the main application, invokes a software routine using the cloth simulation call. Additionally, by operation of the secondary application, a state of the physics simulation is updated in response to the software routine.

Abstract: A system, method, and computer program product are provided for synchronizing operation of a first graphics processor and a second graphics processor in order to secure communication therebetween. A first graphics processor is provided for processing video data. In addition, a second graphics processor is provided for processing the video data. Furthermore, a data structure is provided for use in synchronizing operation of the first graphics processor and the second graphics processor in order to secure communication therebetween.

Abstract: A system for distributed of plane equation calculations. A work distribution unit is configured to receive a set of vertex data that includes meta data associated with each vertex in a modeled three-dimensional scene, to divide the set of vertex data into a plurality of batches of vertices, and to distribute the plurality of batches of vertices to one or more general processing clusters (GPCs). A processing cluster array includes the one or more (GPCs), where each GPC includes one or more shader-primitive-controller units (SPMs), and each SPM is configured to calculate plane equation coefficients for a subset of the vertices included in a batch of vertices. Advantageously, a distributed configuration of multiple plane equation calculation units decreases the size of the data bus that carries plane equation coefficients and increases overall processing throughput.

Abstract: A method and an apparatus are provided for combining multiple independent tile based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU.

Abstract: A three-dimensional graphics system is provided. The three-dimensional graphics system rasterizes each of a plurality of polygons generated from vertexes in an order adapted to characteristics of each polygon. The three-dimensional graphics system includes a rasterization engine including a polygon setup unit receiving the vertexes and generating the polygons and rasterization information for each polygon, and a rasterizer rasterizing pixels using the rasterization information received from the polygon setup unit in an order adapted to the characteristics of each polygon. Accordingly, the coherence of the pixels is increased and the hit ratio of cache memory is thus increased. As a result, the performance of the three-dimensional graphics system is improved. With the increase of the hit ratio of the cache memory, buss traffic in the system is reduced and power consumption is thus reduced.

Abstract: In a data processing system for determining intersections between geometric objects, the work is split between a CPU and a stream processor. The intersection determination is controlled by the CPU. Data processing intensive parts of intersection algorithms, such as checking possible overlap of objects, checking overlap of normal fields of objects, approximating the extent of an object, approximating the normal fields of an object, or making conjectures for intersection topology and/or geometry between objects, are run on the stream processor. The results of the algorithmic parts run on the stream processor are used by the part of the algorithms run on the CPU. In cases where conjectures for the computational result are processed on the stream processor, the conjectures are checked for correctness by algorithms run on the CPU. If the correctness check shows that the result found is incomplete or wrong, additional parts of the algorithm are run on the CPU and possibly on the stream processor.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: An expandable multi-core telecommunication and video processing apparatus includes a primary wireless telecommunications device having a microprocessor that can be programed for running a wide range of software application and includes a primary, or main, viewer touch screen interface and a plurality of ports for receiving one or more video core processors. Each video core processor is removably connectable to a port located along a surface of the primary telecommunications device for permitting a plurality of individual videos which can be interfaced by a user. The individual videos displaced by each connected video core processor can act in concert with, or independently of, the main, or primary, touch screen interface which is located on a front surface of the primary telecommunications device. The primary telecommunications device further includes a detachable storage bay for retaining video core processors when not connected with the primary telecommunications device.

Abstract: An image display method comprises uploading images from a terminal of users to a server via a network, storing the images uploaded by the users in the server, calculating a value of the stored images, displaying a predetermined number of images among the stored images at the terminal in a manner in accordance with the value of the images.

Abstract: One embodiment of the present invention sets forth a system that allows a software developer to perform shader debugging and performance tuning. The system includes an interception layer between the software application and the application programming interface (API). The interception layer is configured to intercept and store source code versions of the original shaders included in the application. For each object in the frame, the interception layer makes shader source code available to the developer, so that the developer can modify the source code as needed, re-compile only the modified shader source code, and run the application. Consequently, shader debugging and performance tuning may be carried out in a manner that is more efficient and effective relative to prior art approaches.

Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.

Abstract: A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: One embodiment of the present invention sets forth a technique for dynamically switching between a power-saving integrated graphics processing unit (IGPU) and a higher-performance discrete graphics processing unit (DGPU). This technique uses a single graphics driver and a single digital-to-analog converter (DAC) and leverages the GPU switching capability of the operating system to ensure a seamless transition. When additional graphics performance is desired, the system enters a hybrid graphics mode. In this mode, the DGPU is powered-up, and the graphics driver maintains the current display, while the operating system switches applications running on the IGPU to the DGPU. While in the hybrid graphics mode, the DGPU performs the graphics processing, and the graphics driver transmits the rendered images from the DGPU to the IGPU local memory and, then, to the IGPU DAC.

Abstract: Direct macroblock mode techniques for high performance hardware motion compensation are described. An embodiment includes a hardware motion compensation graphics display device driver. More specifically, an embodiment mitigates a macroblock data parsing bottleneck in the display device driver by directly generating macroblock instructions and storing them in a dedicated buffer. For example, an embodiment includes an independent direct memory access instruction execution buffer for macroblock instructions separate from the direct memory access instruction execution buffer for all other hardware motion compensation instructions. Other embodiments are described and claimed.

Abstract: A circuit monitors and resets a co-processor. The circuit includes a hang detector module for detecting a hang in co-processor. The circuit also includes a selective processor reset module for resetting the co-processor without resetting a processor in response to detecting a hang in the co-processor.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.

Abstract: Systems, methods, and articles of manufacture for optimizing task scheduling on an accelerated processing device (APD) device are provided. In an embodiment, a method comprises: enqueuing, using the APD, one or more tasks in a memory storage; and dequeuing, using the APD, the one or more tasks from the memory storage using a hardware-based command processor, wherein the command processor forwards the one or more tasks to a shader core.

Abstract: Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process.

Abstract: One embodiment of the present invention sets forth a technique for dynamically switching between a power-saving integrated graphics processing unit (IGPU) and a higher-performance discrete graphics processing unit (DGPU). This technique uses a single graphics driver and a single digital-to-analog converter (DAC) and leverages the GPU switching capability of the operating system to ensure a seamless transition. When additional graphics performance is desired, the system enters a hybrid graphics mode. In this mode, the DGPU is powered-up, and the graphics driver maintains the current display, while the operating system switches applications running on the IGPU to the DGPU. While in the hybrid graphics mode, the DGPU performs the graphics processing, and the graphics driver transmits the rendered images from the DGPU to the IGPU local memory and, then, to the IGPU DAC.

Abstract: Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device.

Abstract: A processing unit, method, and graphics processing system are provided for processing a plurality of frames of graphics data. For instance, the processing unit can include a first plurality of graphics processing units (GPUs), a second plurality of GPUs, and a plurality of compositors. The first plurality of GPUs can be configured to process a first frame of graphics data. Likewise, the second plurality of GPUs can be configured to process a second frame of graphics data. Further, each compositor in the plurality of compositors can be coupled to a respective GPU from the first and second pluralities of GPUs, where the plurality of compositors is configured to sequentially pass the first and second frames of graphics data to a display module.

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract: Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Abstract: A system, method, and computer program product are provided for adjusting at least one aspect of a programmable graphics and/or audio processor. In use, at least one input parameter and at least one output parameter of a programmable graphics and/or audio processor are identified. Thereafter, at least one aspect of the programmable graphics and/or audio processor may thus be dynamically adjusted. Such adjustment is performed as a function of both the at least one input parameter and the at least one output parameter.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.